1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=1 %s -o - | FileCheck %s 3--- 4name: add_B 5alignment: 4 6legalized: true 7regBankSelected: true 8tracksRegLiveness: true 9liveins: 10 - { reg: '$x0' } 11body: | 12 bb.1: 13 liveins: $x0 14 15 ; CHECK-LABEL: name: add_B 16 ; CHECK: liveins: $x0 17 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 18 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<16 x s8>)) 19 ; CHECK: [[ADDVv16i8v:%[0-9]+]]:fpr8 = ADDVv16i8v [[LDRQui]] 20 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[ADDVv16i8v]], %subreg.bsub 21 ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]] 22 ; CHECK: $w0 = COPY [[COPY1]] 23 ; CHECK: RET_ReallyLR implicit $w0 24 %0:gpr(p0) = COPY $x0 25 %1:fpr(<16 x s8>) = G_LOAD %0(p0) :: (load (<16 x s8>)) 26 %2:fpr(s8) = G_VECREDUCE_ADD %1(<16 x s8>) 27 %4:gpr(s8) = COPY %2(s8) 28 %3:gpr(s32) = G_ANYEXT %4(s8) 29 $w0 = COPY %3(s32) 30 RET_ReallyLR implicit $w0 31 32... 33--- 34name: add_H 35alignment: 4 36legalized: true 37regBankSelected: true 38tracksRegLiveness: true 39liveins: 40 - { reg: '$x0' } 41body: | 42 bb.1: 43 liveins: $x0 44 45 ; CHECK-LABEL: name: add_H 46 ; CHECK: liveins: $x0 47 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 48 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<8 x s16>)) 49 ; CHECK: [[ADDVv8i16v:%[0-9]+]]:fpr16 = ADDVv8i16v [[LDRQui]] 50 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, [[ADDVv8i16v]], %subreg.hsub 51 ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SUBREG_TO_REG]] 52 ; CHECK: $w0 = COPY [[COPY1]] 53 ; CHECK: RET_ReallyLR implicit $w0 54 %0:gpr(p0) = COPY $x0 55 %1:fpr(<8 x s16>) = G_LOAD %0(p0) :: (load (<8 x s16>)) 56 %2:fpr(s16) = G_VECREDUCE_ADD %1(<8 x s16>) 57 %4:gpr(s16) = COPY %2(s16) 58 %3:gpr(s32) = G_ANYEXT %4(s16) 59 $w0 = COPY %3(s32) 60 RET_ReallyLR implicit $w0 61 62... 63--- 64name: add_S 65alignment: 4 66legalized: true 67regBankSelected: true 68tracksRegLiveness: true 69liveins: 70 - { reg: '$x0' } 71body: | 72 bb.1: 73 liveins: $x0 74 75 ; CHECK-LABEL: name: add_S 76 ; CHECK: liveins: $x0 77 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 78 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<4 x s32>)) 79 ; CHECK: [[ADDVv4i32v:%[0-9]+]]:fpr32 = ADDVv4i32v [[LDRQui]] 80 ; CHECK: $w0 = COPY [[ADDVv4i32v]] 81 ; CHECK: RET_ReallyLR implicit $w0 82 %0:gpr(p0) = COPY $x0 83 %1:fpr(<4 x s32>) = G_LOAD %0(p0) :: (load (<4 x s32>)) 84 %2:fpr(s32) = G_VECREDUCE_ADD %1(<4 x s32>) 85 $w0 = COPY %2(s32) 86 RET_ReallyLR implicit $w0 87 88... 89--- 90name: add_S_v2i32 91alignment: 4 92legalized: true 93regBankSelected: true 94tracksRegLiveness: true 95liveins: 96 - { reg: '$x0' } 97body: | 98 bb.1: 99 liveins: $x0 100 101 ; CHECK-LABEL: name: add_S_v2i32 102 ; CHECK: liveins: $x0 103 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 104 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY]], 0 :: (load (<2 x s32>)) 105 ; CHECK: [[ADDPv2i32_:%[0-9]+]]:fpr64 = ADDPv2i32 [[LDRDui]], [[LDRDui]] 106 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[ADDPv2i32_]].ssub 107 ; CHECK: $w0 = COPY [[COPY1]] 108 ; CHECK: RET_ReallyLR implicit $w0 109 %0:gpr(p0) = COPY $x0 110 %1:fpr(<2 x s32>) = G_LOAD %0(p0) :: (load (<2 x s32>)) 111 %2:fpr(s32) = G_VECREDUCE_ADD %1(<2 x s32>) 112 $w0 = COPY %2(s32) 113 RET_ReallyLR implicit $w0 114 115... 116--- 117name: add_D 118alignment: 4 119legalized: true 120regBankSelected: true 121tracksRegLiveness: true 122liveins: 123 - { reg: '$x0' } 124body: | 125 bb.1: 126 liveins: $x0 127 128 ; CHECK-LABEL: name: add_D 129 ; CHECK: liveins: $x0 130 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 131 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[COPY]], 0 :: (load (<2 x s64>)) 132 ; CHECK: [[ADDPv2i64p:%[0-9]+]]:fpr64 = ADDPv2i64p [[LDRQui]] 133 ; CHECK: $x0 = COPY [[ADDPv2i64p]] 134 ; CHECK: RET_ReallyLR implicit $x0 135 %0:gpr(p0) = COPY $x0 136 %1:fpr(<2 x s64>) = G_LOAD %0(p0) :: (load (<2 x s64>)) 137 %2:fpr(s64) = G_VECREDUCE_ADD %1(<2 x s64>) 138 $x0 = COPY %2(s64) 139 RET_ReallyLR implicit $x0 140 141... 142