xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/select-mul.mir (revision b2b122ddfaa7e76a36d2a20a8d0a2dee5c49d5f2) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3---
4name:            mul_i64_sext_imm32
5legalized:       true
6regBankSelected: true
7
8registers:
9  - { id: 0, class: gpr }
10  - { id: 1, class: gpr }
11  - { id: 2, class: gpr }
12  - { id: 3, class: gpr }
13
14body:             |
15  bb.0:
16    liveins: $w0
17
18    ; Make sure InstructionSelector is able to match a pattern
19    ; with an SDNodeXForm, trunc_imm.
20    ; def : Pat<(i64 (mul (sext GPR32:$Rn), (s64imm_32bit:$C))),
21    ;             (SMADDLrrr GPR32:$Rn, (MOVi32imm (trunc_imm imm:$C)), XZR)>;
22    ; CHECK-LABEL: name: mul_i64_sext_imm32
23    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
24    ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 3
25    ; CHECK-NEXT: [[SMADDLrrr:%[0-9]+]]:gpr64 = SMADDLrrr [[COPY]], [[MOVi32imm]], $xzr
26    ; CHECK-NEXT: $x0 = COPY [[SMADDLrrr]]
27    %0:gpr(s32) = COPY $w0
28    %1:gpr(s64) = G_SEXT %0(s32)
29    %2:gpr(s64) = G_CONSTANT i64 3
30    %3:gpr(s64) = G_MUL %1, %2
31    $x0 = COPY %3(s64)
32...
33---
34name:            umulh_v8s16
35legalized:       true
36regBankSelected: true
37exposesReturnsTwice: false
38tracksRegLiveness: true
39liveins:
40  - { reg: '$q0', virtual-reg: '' }
41body:             |
42  bb.1:
43    liveins: $q0, $q1
44
45    ; CHECK-LABEL: name: umulh_v8s16
46    ; CHECK: liveins: $q0, $q1
47    ; CHECK-NEXT: {{  $}}
48    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
49    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
50    ; CHECK-NEXT: [[UMULLv8i16_v4i32_:%[0-9]+]]:fpr128 = UMULLv8i16_v4i32 [[COPY]], [[COPY1]]
51    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
52    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
53    ; CHECK-NEXT: [[UMULLv4i16_v4i32_:%[0-9]+]]:fpr128 = UMULLv4i16_v4i32 [[COPY3]], [[COPY2]]
54    ; CHECK-NEXT: %mul:fpr128 = UZP2v8i16 [[UMULLv4i16_v4i32_]], [[UMULLv8i16_v4i32_]]
55    ; CHECK-NEXT: $q0 = COPY %mul
56    ; CHECK-NEXT: RET_ReallyLR implicit $q0
57    %0:fpr(<8 x s16>) = COPY $q0
58    %1:fpr(<8 x s16>) = COPY $q1
59    %mul:fpr(<8 x s16>) = G_UMULH %0, %1
60    $q0 = COPY %mul(<8 x s16>)
61    RET_ReallyLR implicit $q0
62
63...
64---
65name:            umulh_v16s8
66legalized:       true
67regBankSelected: true
68exposesReturnsTwice: false
69tracksRegLiveness: true
70liveins:
71  - { reg: '$q0', virtual-reg: '' }
72body:             |
73  bb.1:
74    liveins: $q0, $q1
75
76    ; CHECK-LABEL: name: umulh_v16s8
77    ; CHECK: liveins: $q0, $q1
78    ; CHECK-NEXT: {{  $}}
79    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
80    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
81    ; CHECK-NEXT: [[UMULLv16i8_v8i16_:%[0-9]+]]:fpr128 = UMULLv16i8_v8i16 [[COPY]], [[COPY1]]
82    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
83    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
84    ; CHECK-NEXT: [[UMULLv8i8_v8i16_:%[0-9]+]]:fpr128 = UMULLv8i8_v8i16 [[COPY3]], [[COPY2]]
85    ; CHECK-NEXT: %mul:fpr128 = UZP2v16i8 [[UMULLv8i8_v8i16_]], [[UMULLv16i8_v8i16_]]
86    ; CHECK-NEXT: $q0 = COPY %mul
87    ; CHECK-NEXT: RET_ReallyLR implicit $q0
88    %0:fpr(<16 x s8>) = COPY $q0
89    %1:fpr(<16 x s8>) = COPY $q1
90    %mul:fpr(<16 x s8>) = G_UMULH %0, %1
91    $q0 = COPY %mul(<16 x s8>)
92    RET_ReallyLR implicit $q0
93
94...
95---
96name:            umulh_v4s32
97legalized:       true
98regBankSelected: true
99exposesReturnsTwice: false
100tracksRegLiveness: true
101liveins:
102  - { reg: '$q0', virtual-reg: '' }
103body:             |
104  bb.1:
105    liveins: $q0, $q1
106
107    ; CHECK-LABEL: name: umulh_v4s32
108    ; CHECK: liveins: $q0, $q1
109    ; CHECK-NEXT: {{  $}}
110    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
111    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
112    ; CHECK-NEXT: [[UMULLv4i32_v2i64_:%[0-9]+]]:fpr128 = UMULLv4i32_v2i64 [[COPY]], [[COPY1]]
113    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
114    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
115    ; CHECK-NEXT: [[UMULLv2i32_v2i64_:%[0-9]+]]:fpr128 = UMULLv2i32_v2i64 [[COPY3]], [[COPY2]]
116    ; CHECK-NEXT: %mul:fpr128 = UZP2v4i32 [[UMULLv2i32_v2i64_]], [[UMULLv4i32_v2i64_]]
117    ; CHECK-NEXT: $q0 = COPY %mul
118    ; CHECK-NEXT: RET_ReallyLR implicit $q0
119    %0:fpr(<4 x s32>) = COPY $q0
120    %1:fpr(<4 x s32>) = COPY $q1
121    %mul:fpr(<4 x s32>) = G_UMULH %0, %1
122    $q0 = COPY %mul(<4 x s32>)
123    RET_ReallyLR implicit $q0
124
125...
126---
127name:            smulh_v8s16
128legalized:       true
129regBankSelected: true
130exposesReturnsTwice: false
131tracksRegLiveness: true
132liveins:
133  - { reg: '$q0', virtual-reg: '' }
134body:             |
135  bb.1:
136    liveins: $q0, $q1
137
138    ; CHECK-LABEL: name: smulh_v8s16
139    ; CHECK: liveins: $q0, $q1
140    ; CHECK-NEXT: {{  $}}
141    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
142    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
143    ; CHECK-NEXT: [[SMULLv8i16_v4i32_:%[0-9]+]]:fpr128 = SMULLv8i16_v4i32 [[COPY]], [[COPY1]]
144    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
145    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
146    ; CHECK-NEXT: [[SMULLv4i16_v4i32_:%[0-9]+]]:fpr128 = SMULLv4i16_v4i32 [[COPY3]], [[COPY2]]
147    ; CHECK-NEXT: %mul:fpr128 = UZP2v8i16 [[SMULLv4i16_v4i32_]], [[SMULLv8i16_v4i32_]]
148    ; CHECK-NEXT: $q0 = COPY %mul
149    ; CHECK-NEXT: RET_ReallyLR implicit $q0
150    %0:fpr(<8 x s16>) = COPY $q0
151    %1:fpr(<8 x s16>) = COPY $q1
152    %mul:fpr(<8 x s16>) = G_SMULH %0, %1
153    $q0 = COPY %mul(<8 x s16>)
154    RET_ReallyLR implicit $q0
155
156...
157---
158name:            smulh_v16s8
159legalized:       true
160regBankSelected: true
161exposesReturnsTwice: false
162tracksRegLiveness: true
163liveins:
164  - { reg: '$q0', virtual-reg: '' }
165body:             |
166  bb.1:
167    liveins: $q0, $q1
168
169    ; CHECK-LABEL: name: smulh_v16s8
170    ; CHECK: liveins: $q0, $q1
171    ; CHECK-NEXT: {{  $}}
172    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
173    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
174    ; CHECK-NEXT: [[SMULLv16i8_v8i16_:%[0-9]+]]:fpr128 = SMULLv16i8_v8i16 [[COPY]], [[COPY1]]
175    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
176    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
177    ; CHECK-NEXT: [[SMULLv8i8_v8i16_:%[0-9]+]]:fpr128 = SMULLv8i8_v8i16 [[COPY3]], [[COPY2]]
178    ; CHECK-NEXT: %mul:fpr128 = UZP2v16i8 [[SMULLv8i8_v8i16_]], [[SMULLv16i8_v8i16_]]
179    ; CHECK-NEXT: $q0 = COPY %mul
180    ; CHECK-NEXT: RET_ReallyLR implicit $q0
181    %0:fpr(<16 x s8>) = COPY $q0
182    %1:fpr(<16 x s8>) = COPY $q1
183    %mul:fpr(<16 x s8>) = G_SMULH %0, %1
184    $q0 = COPY %mul(<16 x s8>)
185    RET_ReallyLR implicit $q0
186
187...
188---
189name:            smulh_v4s32
190legalized:       true
191regBankSelected: true
192exposesReturnsTwice: false
193tracksRegLiveness: true
194liveins:
195  - { reg: '$q0', virtual-reg: '' }
196body:             |
197  bb.1:
198    liveins: $q0, $q1
199
200    ; CHECK-LABEL: name: smulh_v4s32
201    ; CHECK: liveins: $q0, $q1
202    ; CHECK-NEXT: {{  $}}
203    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
204    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
205    ; CHECK-NEXT: [[SMULLv4i32_v2i64_:%[0-9]+]]:fpr128 = SMULLv4i32_v2i64 [[COPY]], [[COPY1]]
206    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[COPY1]].dsub
207    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:fpr64 = COPY [[COPY]].dsub
208    ; CHECK-NEXT: [[SMULLv2i32_v2i64_:%[0-9]+]]:fpr128 = SMULLv2i32_v2i64 [[COPY3]], [[COPY2]]
209    ; CHECK-NEXT: %mul:fpr128 = UZP2v4i32 [[SMULLv2i32_v2i64_]], [[SMULLv4i32_v2i64_]]
210    ; CHECK-NEXT: $q0 = COPY %mul
211    ; CHECK-NEXT: RET_ReallyLR implicit $q0
212    %0:fpr(<4 x s32>) = COPY $q0
213    %1:fpr(<4 x s32>) = COPY $q1
214    %mul:fpr(<4 x s32>) = G_SMULH %0, %1
215    $q0 = COPY %mul(<4 x s32>)
216    RET_ReallyLR implicit $q0
217
218...
219