1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3 4--- | 5 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" 6 7 define void @anyext_s64_from_s32() { ret void } 8 define void @anyext_s32_from_s8() { ret void } 9 define void @anyext_v8s16_from_v8s8() { ret void } 10 define void @anyext_v4s32_from_v4s16() { ret void } 11 define void @anyext_v2s64_from_v2s32() { ret void } 12 13 define void @zext_s64_from_s32() { ret void } 14 define void @zext_s32_from_s16() { ret void } 15 define void @zext_s32_from_s8() { ret void } 16 define void @zext_s16_from_s8() { ret void } 17 define void @zext_v8s16_from_v8s8() { ret void } 18 define void @zext_v4s32_from_v4s16() { ret void } 19 define void @zext_v2s64_from_v2s32() { ret void } 20 21 define void @sext_s64_from_s32() { ret void } 22 define void @sext_s32_from_s16() { ret void } 23 define void @sext_s32_from_s8() { ret void } 24 define void @sext_s16_from_s8() { ret void } 25 define void @sext_v8s16_from_v8s8() { ret void } 26 define void @sext_v4s32_from_v4s16() { ret void } 27 define void @sext_v2s64_from_v2s32() { ret void } 28... 29 30--- 31name: anyext_s64_from_s32 32legalized: true 33regBankSelected: true 34 35registers: 36 - { id: 0, class: gpr } 37 - { id: 1, class: gpr } 38 39body: | 40 bb.0: 41 liveins: $w0 42 43 ; CHECK-LABEL: name: anyext_s64_from_s32 44 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 45 ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF 46 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64all = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32 47 ; CHECK: $x0 = COPY [[INSERT_SUBREG]] 48 %0(s32) = COPY $w0 49 %1(s64) = G_ANYEXT %0 50 $x0 = COPY %1(s64) 51... 52 53--- 54name: anyext_s32_from_s8 55legalized: true 56regBankSelected: true 57 58registers: 59 - { id: 0, class: gpr } 60 - { id: 1, class: gpr } 61 62body: | 63 bb.0: 64 liveins: $w0 65 66 ; CHECK-LABEL: name: anyext_s32_from_s8 67 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 68 ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]] 69 ; CHECK: $w0 = COPY [[COPY1]] 70 %2:gpr(s32) = COPY $w0 71 %0(s8) = G_TRUNC %2 72 %1(s32) = G_ANYEXT %0 73 $w0 = COPY %1(s32) 74... 75 76--- 77name: anyext_v8s16_from_v8s8 78alignment: 4 79legalized: true 80regBankSelected: true 81tracksRegLiveness: true 82registers: 83 - { id: 0, class: fpr } 84 - { id: 1, class: fpr } 85machineFunctionInfo: {} 86body: | 87 bb.0: 88 liveins: $d0 89 90 ; CHECK-LABEL: name: anyext_v8s16_from_v8s8 91 ; CHECK: liveins: $d0 92 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 93 ; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0 94 ; CHECK: $q0 = COPY [[USHLLv8i8_shift]] 95 ; CHECK: RET_ReallyLR implicit $q0 96 %0:fpr(<8 x s8>) = COPY $d0 97 %1:fpr(<8 x s16>) = G_ANYEXT %0(<8 x s8>) 98 $q0 = COPY %1(<8 x s16>) 99 RET_ReallyLR implicit $q0 100... 101 102--- 103name: anyext_v4s32_from_v4s16 104alignment: 4 105legalized: true 106regBankSelected: true 107tracksRegLiveness: true 108registers: 109 - { id: 0, class: fpr } 110 - { id: 1, class: fpr } 111machineFunctionInfo: {} 112body: | 113 bb.0: 114 liveins: $d0 115 116 ; CHECK-LABEL: name: anyext_v4s32_from_v4s16 117 ; CHECK: liveins: $d0 118 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 119 ; CHECK: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0 120 ; CHECK: $q0 = COPY [[USHLLv4i16_shift]] 121 ; CHECK: RET_ReallyLR implicit $q0 122 %0:fpr(<4 x s16>) = COPY $d0 123 %1:fpr(<4 x s32>) = G_ANYEXT %0(<4 x s16>) 124 $q0 = COPY %1(<4 x s32>) 125 RET_ReallyLR implicit $q0 126... 127 128--- 129name: anyext_v2s64_from_v2s32 130alignment: 4 131legalized: true 132regBankSelected: true 133tracksRegLiveness: true 134registers: 135 - { id: 0, class: fpr } 136 - { id: 1, class: fpr } 137machineFunctionInfo: {} 138body: | 139 bb.0: 140 liveins: $d0 141 142 ; CHECK-LABEL: name: anyext_v2s64_from_v2s32 143 ; CHECK: liveins: $d0 144 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 145 ; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0 146 ; CHECK: $q0 = COPY [[USHLLv2i32_shift]] 147 ; CHECK: RET_ReallyLR implicit $q0 148 %0:fpr(<2 x s32>) = COPY $d0 149 %1:fpr(<2 x s64>) = G_ANYEXT %0(<2 x s32>) 150 $q0 = COPY %1(<2 x s64>) 151 RET_ReallyLR implicit $q0 152... 153 154--- 155name: zext_s64_from_s32 156legalized: true 157regBankSelected: true 158 159registers: 160 - { id: 0, class: gpr } 161 - { id: 1, class: gpr } 162 163body: | 164 bb.0: 165 liveins: $w0 166 167 ; CHECK-LABEL: name: zext_s64_from_s32 168 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 169 ; CHECK: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, [[COPY]], 0 170 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 171 ; CHECK: $x0 = COPY [[SUBREG_TO_REG]] 172 %0(s32) = COPY $w0 173 %1(s64) = G_ZEXT %0 174 $x0 = COPY %1(s64) 175... 176 177--- 178name: zext_s32_from_s16 179legalized: true 180regBankSelected: true 181 182registers: 183 - { id: 0, class: gpr } 184 - { id: 1, class: gpr } 185 186body: | 187 bb.0: 188 liveins: $w0 189 190 ; CHECK-LABEL: name: zext_s32_from_s16 191 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 192 ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15 193 ; CHECK: $w0 = COPY [[UBFMWri]] 194 %2:gpr(s32) = COPY $w0 195 %0(s16) = G_TRUNC %2 196 %1(s32) = G_ZEXT %0 197 $w0 = COPY %1 198... 199 200--- 201name: zext_s32_from_s8 202legalized: true 203regBankSelected: true 204 205registers: 206 - { id: 0, class: gpr } 207 - { id: 1, class: gpr } 208 209body: | 210 bb.0: 211 liveins: $w0 212 213 ; CHECK-LABEL: name: zext_s32_from_s8 214 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 215 ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15 216 ; CHECK: $w0 = COPY [[UBFMWri]] 217 %2:gpr(s32) = COPY $w0 218 %0(s16) = G_TRUNC %2 219 %1(s32) = G_ZEXT %0 220 $w0 = COPY %1(s32) 221... 222 223--- 224name: zext_s16_from_s8 225legalized: true 226regBankSelected: true 227 228registers: 229 - { id: 0, class: gpr } 230 - { id: 1, class: gpr } 231 232body: | 233 bb.0: 234 liveins: $w0 235 236 ; CHECK-LABEL: name: zext_s16_from_s8 237 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 238 ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 7 239 ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[UBFMWri]] 240 ; CHECK: $w0 = COPY [[COPY1]] 241 %2:gpr(s32) = COPY $w0 242 %0(s8) = G_TRUNC %2 243 %1(s16) = G_ZEXT %0 244 %3:gpr(s32) = G_ANYEXT %1 245 $w0 = COPY %3(s32) 246... 247 248--- 249name: zext_v8s16_from_v8s8 250alignment: 4 251legalized: true 252regBankSelected: true 253tracksRegLiveness: true 254registers: 255 - { id: 0, class: fpr } 256 - { id: 1, class: fpr } 257machineFunctionInfo: {} 258body: | 259 bb.0: 260 liveins: $d0 261 262 ; CHECK-LABEL: name: zext_v8s16_from_v8s8 263 ; CHECK: liveins: $d0 264 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 265 ; CHECK: [[USHLLv8i8_shift:%[0-9]+]]:fpr128 = USHLLv8i8_shift [[COPY]], 0 266 ; CHECK: $q0 = COPY [[USHLLv8i8_shift]] 267 ; CHECK: RET_ReallyLR implicit $q0 268 %0:fpr(<8 x s8>) = COPY $d0 269 %1:fpr(<8 x s16>) = G_ZEXT %0(<8 x s8>) 270 $q0 = COPY %1(<8 x s16>) 271 RET_ReallyLR implicit $q0 272 273... 274 275--- 276name: zext_v4s32_from_v4s16 277alignment: 4 278legalized: true 279regBankSelected: true 280tracksRegLiveness: true 281registers: 282 - { id: 0, class: fpr } 283 - { id: 1, class: fpr } 284machineFunctionInfo: {} 285body: | 286 bb.0: 287 liveins: $d0 288 289 ; CHECK-LABEL: name: zext_v4s32_from_v4s16 290 ; CHECK: liveins: $d0 291 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 292 ; CHECK: [[USHLLv4i16_shift:%[0-9]+]]:fpr128 = USHLLv4i16_shift [[COPY]], 0 293 ; CHECK: $q0 = COPY [[USHLLv4i16_shift]] 294 ; CHECK: RET_ReallyLR implicit $q0 295 %0:fpr(<4 x s16>) = COPY $d0 296 %1:fpr(<4 x s32>) = G_ZEXT %0(<4 x s16>) 297 $q0 = COPY %1(<4 x s32>) 298 RET_ReallyLR implicit $q0 299... 300 301--- 302name: zext_v2s64_from_v2s32 303alignment: 4 304legalized: true 305regBankSelected: true 306tracksRegLiveness: true 307registers: 308 - { id: 0, class: fpr } 309 - { id: 1, class: fpr } 310machineFunctionInfo: {} 311body: | 312 bb.0: 313 liveins: $d0 314 315 ; CHECK-LABEL: name: zext_v2s64_from_v2s32 316 ; CHECK: liveins: $d0 317 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 318 ; CHECK: [[USHLLv2i32_shift:%[0-9]+]]:fpr128 = USHLLv2i32_shift [[COPY]], 0 319 ; CHECK: $q0 = COPY [[USHLLv2i32_shift]] 320 ; CHECK: RET_ReallyLR implicit $q0 321 %0:fpr(<2 x s32>) = COPY $d0 322 %1:fpr(<2 x s64>) = G_ZEXT %0(<2 x s32>) 323 $q0 = COPY %1(<2 x s64>) 324 RET_ReallyLR implicit $q0 325... 326 327--- 328name: sext_s64_from_s32 329legalized: true 330regBankSelected: true 331 332registers: 333 - { id: 0, class: gpr } 334 - { id: 1, class: gpr } 335 336body: | 337 bb.0: 338 liveins: $w0 339 340 ; CHECK-LABEL: name: sext_s64_from_s32 341 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 342 ; CHECK: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF 343 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32 344 ; CHECK: [[SBFMXri:%[0-9]+]]:gpr64 = SBFMXri [[INSERT_SUBREG]], 0, 31 345 ; CHECK: $x0 = COPY [[SBFMXri]] 346 %0(s32) = COPY $w0 347 %1(s64) = G_SEXT %0 348 $x0 = COPY %1(s64) 349... 350 351--- 352name: sext_s32_from_s16 353legalized: true 354regBankSelected: true 355 356registers: 357 - { id: 0, class: gpr } 358 - { id: 1, class: gpr } 359 360body: | 361 bb.0: 362 liveins: $w0 363 364 ; CHECK-LABEL: name: sext_s32_from_s16 365 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 366 ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 15 367 ; CHECK: $w0 = COPY [[SBFMWri]] 368 %2:gpr(s32) = COPY $w0 369 %0(s16) = G_TRUNC %2 370 %1(s32) = G_SEXT %0 371 $w0 = COPY %1 372... 373 374--- 375name: sext_s32_from_s8 376legalized: true 377regBankSelected: true 378 379registers: 380 - { id: 0, class: gpr } 381 - { id: 1, class: gpr } 382 383body: | 384 bb.0: 385 liveins: $w0 386 387 ; CHECK-LABEL: name: sext_s32_from_s8 388 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 389 ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7 390 ; CHECK: $w0 = COPY [[SBFMWri]] 391 %2:gpr(s32) = COPY $w0 392 %0(s8) = G_TRUNC %2 393 %1(s32) = G_SEXT %0 394 $w0 = COPY %1(s32) 395... 396 397--- 398name: sext_s16_from_s8 399legalized: true 400regBankSelected: true 401 402registers: 403 - { id: 0, class: gpr } 404 - { id: 1, class: gpr } 405 406body: | 407 bb.0: 408 liveins: $w0 409 410 ; CHECK-LABEL: name: sext_s16_from_s8 411 ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 412 ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7 413 ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[SBFMWri]] 414 ; CHECK: $w0 = COPY [[COPY1]] 415 %2:gpr(s32) = COPY $w0 416 %0(s8) = G_TRUNC %2 417 %1(s16) = G_SEXT %0 418 %3:gpr(s32) = G_ANYEXT %1 419 $w0 = COPY %3(s32) 420... 421 422--- 423name: sext_v8s16_from_v8s8 424alignment: 4 425legalized: true 426regBankSelected: true 427tracksRegLiveness: true 428registers: 429 - { id: 0, class: fpr } 430 - { id: 1, class: fpr } 431machineFunctionInfo: {} 432body: | 433 bb.0: 434 liveins: $d0 435 436 ; CHECK-LABEL: name: sext_v8s16_from_v8s8 437 ; CHECK: liveins: $d0 438 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 439 ; CHECK: [[SSHLLv8i8_shift:%[0-9]+]]:fpr128 = SSHLLv8i8_shift [[COPY]], 0 440 ; CHECK: $q0 = COPY [[SSHLLv8i8_shift]] 441 ; CHECK: RET_ReallyLR implicit $q0 442 %0:fpr(<8 x s8>) = COPY $d0 443 %1:fpr(<8 x s16>) = G_SEXT %0(<8 x s8>) 444 $q0 = COPY %1(<8 x s16>) 445 RET_ReallyLR implicit $q0 446 447... 448 449--- 450name: sext_v4s32_from_v4s16 451alignment: 4 452legalized: true 453regBankSelected: true 454tracksRegLiveness: true 455registers: 456 - { id: 0, class: fpr } 457 - { id: 1, class: fpr } 458machineFunctionInfo: {} 459body: | 460 bb.0: 461 liveins: $d0 462 463 ; CHECK-LABEL: name: sext_v4s32_from_v4s16 464 ; CHECK: liveins: $d0 465 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 466 ; CHECK: [[SSHLLv4i16_shift:%[0-9]+]]:fpr128 = SSHLLv4i16_shift [[COPY]], 0 467 ; CHECK: $q0 = COPY [[SSHLLv4i16_shift]] 468 ; CHECK: RET_ReallyLR implicit $q0 469 %0:fpr(<4 x s16>) = COPY $d0 470 %1:fpr(<4 x s32>) = G_SEXT %0(<4 x s16>) 471 $q0 = COPY %1(<4 x s32>) 472 RET_ReallyLR implicit $q0 473... 474 475--- 476name: sext_v2s64_from_v2s32 477alignment: 4 478legalized: true 479regBankSelected: true 480tracksRegLiveness: true 481registers: 482 - { id: 0, class: fpr } 483 - { id: 1, class: fpr } 484machineFunctionInfo: {} 485body: | 486 bb.0: 487 liveins: $d0 488 489 ; CHECK-LABEL: name: sext_v2s64_from_v2s32 490 ; CHECK: liveins: $d0 491 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 492 ; CHECK: [[SSHLLv2i32_shift:%[0-9]+]]:fpr128 = SSHLLv2i32_shift [[COPY]], 0 493 ; CHECK: $q0 = COPY [[SSHLLv2i32_shift]] 494 ; CHECK: RET_ReallyLR implicit $q0 495 %0:fpr(<2 x s32>) = COPY $d0 496 %1:fpr(<2 x s64>) = G_SEXT %0(<2 x s32>) 497 $q0 = COPY %1(<2 x s64>) 498 RET_ReallyLR implicit $q0 499