xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir (revision ac321cbb0350996ceef4e6d9e8a1035880609288) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select %s -o - | FileCheck %s
3---
4name:            v16s8_gpr
5alignment:       4
6legalized:       true
7regBankSelected: true
8tracksRegLiveness: true
9body:             |
10  bb.0:
11    liveins: $q1, $w0
12
13    ; CHECK-LABEL: name: v16s8_gpr
14    ; CHECK: liveins: $q1, $w0
15    ; CHECK-NEXT: {{  $}}
16    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
17    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
18    ; CHECK-NEXT: [[INSvi8gpr:%[0-9]+]]:fpr128 = INSvi8gpr [[COPY1]], 1, [[COPY]]
19    ; CHECK-NEXT: $q0 = COPY [[INSvi8gpr]]
20    ; CHECK-NEXT: RET_ReallyLR implicit $q0
21    %0:gpr(s32) = COPY $w0
22    %trunc:gpr(s8) = G_TRUNC %0
23    %1:fpr(<16 x s8>) = COPY $q1
24    %3:gpr(s64) = G_CONSTANT i64 1
25    %4:gpr(s32) = G_ANYEXT %trunc
26    %2:fpr(<16 x s8>) = G_INSERT_VECTOR_ELT %1, %4:gpr(s32), %3:gpr(s64)
27    $q0 = COPY %2(<16 x s8>)
28    RET_ReallyLR implicit $q0
29
30...
31---
32name:            v8s8_gpr
33alignment:       4
34legalized:       true
35regBankSelected: true
36tracksRegLiveness: true
37body:             |
38  bb.0:
39    liveins: $d0, $w0
40
41    ; CHECK-LABEL: name: v8s8_gpr
42    ; CHECK: liveins: $d0, $w0
43    ; CHECK-NEXT: {{  $}}
44    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
45    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
46    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
47    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
48    ; CHECK-NEXT: [[INSvi8gpr:%[0-9]+]]:fpr128 = INSvi8gpr [[INSERT_SUBREG]], 1, [[COPY]]
49    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi8gpr]].dsub
50    ; CHECK-NEXT: $d0 = COPY [[COPY2]]
51    ; CHECK-NEXT: RET_ReallyLR implicit $d0
52    %0:gpr(s32) = COPY $w0
53    %trunc:gpr(s8) = G_TRUNC %0
54    %1:fpr(<8 x s8>) = COPY $d0
55    %3:gpr(s64) = G_CONSTANT i64 1
56    %4:gpr(s32) = G_ANYEXT %trunc
57    %2:fpr(<8 x s8>) = G_INSERT_VECTOR_ELT %1, %4(s32), %3(s64)
58    $d0 = COPY %2(<8 x s8>)
59    RET_ReallyLR implicit $d0
60
61...
62---
63name:            v8s16_gpr
64alignment:       4
65legalized:       true
66regBankSelected: true
67tracksRegLiveness: true
68body:             |
69  bb.0:
70    liveins: $q1, $w0
71
72    ; CHECK-LABEL: name: v8s16_gpr
73    ; CHECK: liveins: $q1, $w0
74    ; CHECK-NEXT: {{  $}}
75    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
76    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
77    ; CHECK-NEXT: [[INSvi16gpr:%[0-9]+]]:fpr128 = INSvi16gpr [[COPY1]], 1, [[COPY]]
78    ; CHECK-NEXT: $q0 = COPY [[INSvi16gpr]]
79    ; CHECK-NEXT: RET_ReallyLR implicit $q0
80    %0:gpr(s32) = COPY $w0
81    %trunc:gpr(s16) = G_TRUNC %0
82    %1:fpr(<8 x s16>) = COPY $q1
83    %3:gpr(s64) = G_CONSTANT i64 1
84    %4:gpr(s32) = G_ANYEXT %trunc
85    %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %4:gpr(s32), %3:gpr(s64)
86    $q0 = COPY %2(<8 x s16>)
87    RET_ReallyLR implicit $q0
88
89...
90---
91name:            v8s16_fpr
92alignment:       4
93legalized:       true
94regBankSelected: true
95tracksRegLiveness: true
96body:             |
97  bb.0:
98    liveins: $q1, $h0
99
100    ; CHECK-LABEL: name: v8s16_fpr
101    ; CHECK: liveins: $q1, $h0
102    ; CHECK-NEXT: {{  $}}
103    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
104    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
105    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
106    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.hsub
107    ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
108    ; CHECK-NEXT: $q0 = COPY [[INSvi16lane]]
109    ; CHECK-NEXT: RET_ReallyLR implicit $q0
110    %0:fpr(s16) = COPY $h0
111    %1:fpr(<8 x s16>) = COPY $q1
112    %3:gpr(s64) = G_CONSTANT i64 1
113    %2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %0(s16), %3(s64)
114    $q0 = COPY %2(<8 x s16>)
115    RET_ReallyLR implicit $q0
116
117...
118---
119name:            v4s32_fpr
120alignment:       4
121legalized:       true
122regBankSelected: true
123tracksRegLiveness: true
124body:             |
125  bb.0:
126    liveins: $q1, $s0
127
128    ; CHECK-LABEL: name: v4s32_fpr
129    ; CHECK: liveins: $q1, $s0
130    ; CHECK-NEXT: {{  $}}
131    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
132    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
133    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
134    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub
135    ; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
136    ; CHECK-NEXT: $q0 = COPY [[INSvi32lane]]
137    ; CHECK-NEXT: RET_ReallyLR implicit $q0
138    %0:fpr(s32) = COPY $s0
139    %1:fpr(<4 x s32>) = COPY $q1
140    %3:gpr(s64) = G_CONSTANT i64 1
141    %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64)
142    $q0 = COPY %2(<4 x s32>)
143    RET_ReallyLR implicit $q0
144
145...
146---
147name:            v4s32_gpr
148alignment:       4
149legalized:       true
150regBankSelected: true
151tracksRegLiveness: true
152body:             |
153  bb.0:
154    liveins: $q0, $w0
155
156    ; CHECK-LABEL: name: v4s32_gpr
157    ; CHECK: liveins: $q0, $w0
158    ; CHECK-NEXT: {{  $}}
159    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
160    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
161    ; CHECK-NEXT: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[COPY1]], 1, [[COPY]]
162    ; CHECK-NEXT: $q0 = COPY [[INSvi32gpr]]
163    ; CHECK-NEXT: RET_ReallyLR implicit $q0
164    %0:gpr(s32) = COPY $w0
165    %1:fpr(<4 x s32>) = COPY $q0
166    %3:gpr(s64) = G_CONSTANT i64 1
167    %2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64)
168    $q0 = COPY %2(<4 x s32>)
169    RET_ReallyLR implicit $q0
170
171...
172---
173name:            v4s16_gpr
174alignment:       4
175legalized:       true
176regBankSelected: true
177tracksRegLiveness: true
178body:             |
179  bb.0:
180    liveins: $d0, $w0
181
182    ; CHECK-LABEL: name: v4s16_gpr
183    ; CHECK: liveins: $d0, $w0
184    ; CHECK-NEXT: {{  $}}
185    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
186    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
187    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
188    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
189    ; CHECK-NEXT: [[INSvi16gpr:%[0-9]+]]:fpr128 = INSvi16gpr [[INSERT_SUBREG]], 1, [[COPY]]
190    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16gpr]].dsub
191    ; CHECK-NEXT: $d0 = COPY [[COPY2]]
192    ; CHECK-NEXT: RET_ReallyLR implicit $d0
193    %0:gpr(s32) = COPY $w0
194    %trunc:gpr(s16) = G_TRUNC %0
195    %1:fpr(<4 x s16>) = COPY $d0
196    %3:gpr(s64) = G_CONSTANT i64 1
197    %4:gpr(s32) = G_ANYEXT %trunc
198    %2:fpr(<4 x s16>) = G_INSERT_VECTOR_ELT %1, %4(s32), %3(s64)
199    $d0 = COPY %2(<4 x s16>)
200    RET_ReallyLR implicit $d0
201
202...
203---
204name:            v2s64_fpr
205alignment:       4
206legalized:       true
207regBankSelected: true
208tracksRegLiveness: true
209body:             |
210  bb.0:
211    liveins: $d0, $q1
212
213    ; CHECK-LABEL: name: v2s64_fpr
214    ; CHECK: liveins: $d0, $q1
215    ; CHECK-NEXT: {{  $}}
216    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
217    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
218    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
219    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
220    ; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
221    ; CHECK-NEXT: $q0 = COPY [[INSvi64lane]]
222    ; CHECK-NEXT: RET_ReallyLR implicit $q0
223    %0:fpr(s64) = COPY $d0
224    %1:fpr(<2 x s64>) = COPY $q1
225    %3:gpr(s64) = G_CONSTANT i64 1
226    %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s64)
227    $q0 = COPY %2(<2 x s64>)
228    RET_ReallyLR implicit $q0
229
230...
231---
232name:            v2s64_gpr
233alignment:       4
234legalized:       true
235regBankSelected: true
236tracksRegLiveness: true
237body:             |
238  bb.0:
239    liveins: $q0, $x0
240
241    ; CHECK-LABEL: name: v2s64_gpr
242    ; CHECK: liveins: $q0, $x0
243    ; CHECK-NEXT: {{  $}}
244    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
245    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
246    ; CHECK-NEXT: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[COPY1]], 0, [[COPY]]
247    ; CHECK-NEXT: $q0 = COPY [[INSvi64gpr]]
248    ; CHECK-NEXT: RET_ReallyLR implicit $q0
249    %0:gpr(s64) = COPY $x0
250    %1:fpr(<2 x s64>) = COPY $q0
251    %3:gpr(s64) = G_CONSTANT i64 0
252    %2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s64)
253    $q0 = COPY %2(<2 x s64>)
254    RET_ReallyLR implicit $q0
255
256...
257---
258name:            v2s32_fpr
259alignment:       4
260legalized:       true
261regBankSelected: true
262tracksRegLiveness: true
263body:             |
264  bb.0:
265    liveins: $d1, $s0
266
267    ; CHECK-LABEL: name: v2s32_fpr
268    ; CHECK: liveins: $d1, $s0
269    ; CHECK-NEXT: {{  $}}
270    ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
271    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
272    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
273    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub
274    ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
275    ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub
276    ; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG]], 0
277    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub
278    ; CHECK-NEXT: $d0 = COPY [[COPY2]]
279    ; CHECK-NEXT: RET_ReallyLR implicit $d0
280    %0:fpr(s32) = COPY $s0
281    %1:fpr(<2 x s32>) = COPY $d1
282    %3:gpr(s64) = G_CONSTANT i64 1
283    %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64)
284    $d0 = COPY %2(<2 x s32>)
285    RET_ReallyLR implicit $d0
286
287...
288---
289name:            v2s32_gpr
290alignment:       4
291legalized:       true
292regBankSelected: true
293tracksRegLiveness: true
294body:             |
295  bb.0:
296    liveins: $d0, $w0
297
298    ; CHECK-LABEL: name: v2s32_gpr
299    ; CHECK: liveins: $d0, $w0
300    ; CHECK-NEXT: {{  $}}
301    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
302    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
303    ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
304    ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
305    ; CHECK-NEXT: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[COPY]]
306    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
307    ; CHECK-NEXT: $d0 = COPY [[COPY2]]
308    ; CHECK-NEXT: RET_ReallyLR implicit $d0
309    %0:gpr(s32) = COPY $w0
310    %1:fpr(<2 x s32>) = COPY $d0
311    %3:gpr(s64) = G_CONSTANT i64 1
312    %2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s64)
313    $d0 = COPY %2(<2 x s32>)
314    RET_ReallyLR implicit $d0
315
316...
317