1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3 4--- 5name: v2s32_fmul_indexed 6alignment: 4 7legalized: true 8regBankSelected: true 9tracksRegLiveness: true 10liveins: 11 - { reg: '$d0' } 12 - { reg: '$x0' } 13frameInfo: 14 maxAlignment: 1 15body: | 16 bb.1: 17 liveins: $d0, $x0 18 19 ; CHECK-LABEL: name: v2s32_fmul_indexed 20 ; CHECK: liveins: $d0, $x0 21 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 22 ; CHECK: [[COPY1:%[0-9]+]]:gpr64sp = COPY $x0 23 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[COPY1]], 0 :: (load (<2 x s32>), align 4) 24 ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF 25 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[LDRDui]], %subreg.dsub 26 ; CHECK: [[FMULv2i32_indexed:%[0-9]+]]:fpr64 = nofpexcept FMULv2i32_indexed [[COPY]], [[INSERT_SUBREG]], 0 27 ; CHECK: $d0 = COPY [[FMULv2i32_indexed]] 28 ; CHECK: RET_ReallyLR implicit $d0 29 %0:fpr(<2 x s32>) = COPY $d0 30 %1:gpr(p0) = COPY $x0 31 %2:fpr(<2 x s32>) = G_LOAD %1(p0) :: (load (<2 x s32>), align 4) 32 %9:fpr(<2 x s32>) = G_IMPLICIT_DEF 33 %10:fpr(<4 x s32>) = G_CONCAT_VECTORS %2(<2 x s32>), %9(<2 x s32>) 34 %8:gpr(s64) = G_CONSTANT i64 0 35 %5:fpr(<2 x s32>) = G_DUPLANE32 %10, %8(s64) 36 %7:fpr(<2 x s32>) = G_FMUL %0, %5 37 $d0 = COPY %7(<2 x s32>) 38 RET_ReallyLR implicit $d0 39 40... 41