xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/select-extract-vector-elt-with-extend.mir (revision 661ab70314008b609dda792e2c9dc57afa1f8864) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name:            si64
6legalized:       true
7regBankSelected: true
8tracksRegLiveness: true
9body: |
10  bb.0:
11    liveins: $q0, $w0
12
13    ; CHECK-LABEL: name: si64
14    ; CHECK: liveins: $q0, $w0
15    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
16    ; CHECK: [[SMOVvi32to64_:%[0-9]+]]:gpr64 = SMOVvi32to64 [[COPY]], 1
17    ; CHECK: $x0 = COPY [[SMOVvi32to64_]]
18    ; CHECK: RET_ReallyLR implicit $x0
19    %0:fpr(<4 x s32>) = COPY $q0
20    %3:gpr(s64) = G_CONSTANT i64 1
21    %2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<4 x s32>), %3(s64)
22    %5:gpr(s32) = COPY %2(s32)
23    %4:gpr(s64) = G_SEXT %5(s32)
24    $x0 = COPY %4(s64)
25    RET_ReallyLR implicit $x0
26
27...
28---
29name:            si64_2
30legalized:       true
31regBankSelected: true
32tracksRegLiveness: true
33body: |
34  bb.0:
35    liveins: $d0, $w0
36
37    ; CHECK-LABEL: name: si64_2
38    ; CHECK: liveins: $d0, $w0
39    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
40    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
41    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
42    ; CHECK: [[SMOVvi32to64_:%[0-9]+]]:gpr64 = SMOVvi32to64 [[INSERT_SUBREG]], 1
43    ; CHECK: $x0 = COPY [[SMOVvi32to64_]]
44    ; CHECK: RET_ReallyLR implicit $x0
45    %0:fpr(<2 x s32>) = COPY $d0
46    %3:gpr(s64) = G_CONSTANT i64 1
47    %2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
48    %5:gpr(s32) = COPY %2(s32)
49    %4:gpr(s64) = G_SEXT %5(s32)
50    $x0 = COPY %4(s64)
51    RET_ReallyLR implicit $x0
52
53...
54---
55name:            zi64
56legalized:       true
57regBankSelected: true
58tracksRegLiveness: true
59body: |
60  bb.0:
61    liveins: $q0, $w0
62
63    ; CHECK-LABEL: name: zi64
64    ; CHECK: liveins: $q0, $w0
65    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
66    ; CHECK: [[UMOVvi32_:%[0-9]+]]:gpr32 = UMOVvi32 [[COPY]], 1
67    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[UMOVvi32_]], %subreg.sub_32
68    ; CHECK: $x0 = COPY [[SUBREG_TO_REG]]
69    ; CHECK: RET_ReallyLR implicit $x0
70    %0:fpr(<4 x s32>) = COPY $q0
71    %3:gpr(s64) = G_CONSTANT i64 1
72    %2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<4 x s32>), %3(s64)
73    %5:gpr(s32) = COPY %2(s32)
74    %4:gpr(s64) = G_ZEXT %5(s32)
75    $x0 = COPY %4(s64)
76    RET_ReallyLR implicit $x0
77
78...
79---
80name:            zi64_2
81legalized:       true
82regBankSelected: true
83tracksRegLiveness: true
84body: |
85  bb.0:
86    liveins: $d0, $w0
87
88    ; CHECK-LABEL: name: zi64_2
89    ; CHECK: liveins: $d0, $w0
90    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
91    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
92    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
93    ; CHECK: [[UMOVvi32_:%[0-9]+]]:gpr32 = UMOVvi32 [[INSERT_SUBREG]], 1
94    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[UMOVvi32_]], %subreg.sub_32
95    ; CHECK: $x0 = COPY [[SUBREG_TO_REG]]
96    ; CHECK: RET_ReallyLR implicit $x0
97     %0:fpr(<2 x s32>) = COPY $d0
98    %3:gpr(s64) = G_CONSTANT i64 1
99    %2:fpr(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %3(s64)
100    %5:gpr(s32) = COPY %2(s32)
101    %4:gpr(s64) = G_ZEXT %5(s32)
102    $x0 = COPY %4(s64)
103    RET_ReallyLR implicit $x0
104
105...
106---
107name:            si32
108legalized:       true
109regBankSelected: true
110tracksRegLiveness: true
111body: |
112  bb.0:
113    liveins: $q0, $w0
114
115    ; CHECK-LABEL: name: si32
116    ; CHECK: liveins: $q0, $w0
117    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
118    ; CHECK: [[SMOVvi16to32_:%[0-9]+]]:gpr32 = SMOVvi16to32 [[COPY]], 1
119    ; CHECK: $w0 = COPY [[SMOVvi16to32_]]
120    ; CHECK: RET_ReallyLR implicit $w0
121    %0:fpr(<8 x s16>) = COPY $q0
122    %4:gpr(s64) = G_CONSTANT i64 1
123    %3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)
124    %6:gpr(s16) = COPY %3(s16)
125    %5:gpr(s32) = G_SEXT %6(s16)
126    $w0 = COPY %5(s32)
127    RET_ReallyLR implicit $w0
128
129...
130---
131name:            zi32
132legalized:       true
133regBankSelected: true
134tracksRegLiveness: true
135body: |
136  bb.0:
137    liveins: $q0, $w0
138
139    ; CHECK-LABEL: name: zi32
140    ; CHECK: liveins: $q0, $w0
141    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
142    ; CHECK: [[UMOVvi16_:%[0-9]+]]:gpr32 = UMOVvi16 [[COPY]], 1
143    ; CHECK: $w0 = COPY [[UMOVvi16_]]
144    ; CHECK: RET_ReallyLR implicit $w0
145    %0:fpr(<8 x s16>) = COPY $q0
146    %4:gpr(s64) = G_CONSTANT i64 1
147    %3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<8 x s16>), %4(s64)
148    %6:gpr(s16) = COPY %3(s16)
149    %5:gpr(s32) = G_ZEXT %6(s16)
150    $w0 = COPY %5(s32)
151    RET_ReallyLR implicit $w0
152
153...
154---
155name:            si32_2
156legalized:       true
157regBankSelected: true
158tracksRegLiveness: true
159body: |
160  bb.0:
161    liveins: $d0, $w0
162
163    ; CHECK-LABEL: name: si32_2
164    ; CHECK: liveins: $d0, $w0
165    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
166    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
167    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
168    ; CHECK: [[SMOVvi16to32_:%[0-9]+]]:gpr32 = SMOVvi16to32 [[INSERT_SUBREG]], 1
169    ; CHECK: $w0 = COPY [[SMOVvi16to32_]]
170    ; CHECK: RET_ReallyLR implicit $w0
171    %0:fpr(<4 x s16>) = COPY $d0
172    %4:gpr(s64) = G_CONSTANT i64 1
173    %3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %4(s64)
174    %6:gpr(s16) = COPY %3(s16)
175    %5:gpr(s32) = G_SEXT %6(s16)
176    $w0 = COPY %5(s32)
177    RET_ReallyLR implicit $w0
178
179...
180---
181name:            zi32_2
182legalized:       true
183regBankSelected: true
184tracksRegLiveness: true
185body: |
186  bb.0:
187    liveins: $d0, $w0
188
189    ; CHECK-LABEL: name: zi32_2
190    ; CHECK: liveins: $d0, $w0
191    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
192    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
193    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
194    ; CHECK: [[UMOVvi16_:%[0-9]+]]:gpr32 = UMOVvi16 [[INSERT_SUBREG]], 1
195    ; CHECK: $w0 = COPY [[UMOVvi16_]]
196    ; CHECK: RET_ReallyLR implicit $w0
197    %0:fpr(<4 x s16>) = COPY $d0
198    %4:gpr(s64) = G_CONSTANT i64 1
199    %3:fpr(s16) = G_EXTRACT_VECTOR_ELT %0(<4 x s16>), %4(s64)
200    %6:gpr(s16) = COPY %3(s16)
201    %5:gpr(s32) = G_ZEXT %6(s16)
202    $w0 = COPY %5(s32)
203    RET_ReallyLR implicit $w0
204
205...
206---
207name:            si16
208legalized:       true
209regBankSelected: true
210tracksRegLiveness: true
211body: |
212  bb.0:
213    liveins: $q0, $w0
214
215    ; CHECK-LABEL: name: si16
216    ; CHECK: liveins: $q0, $w0
217    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
218    ; CHECK: [[SMOVvi8to32_:%[0-9]+]]:gpr32 = SMOVvi8to32 [[COPY]], 1
219    ; CHECK: $w0 = COPY [[SMOVvi8to32_]]
220    ; CHECK: RET_ReallyLR implicit $w0
221    %0:fpr(<16 x s8>) = COPY $q0
222    %4:gpr(s64) = G_CONSTANT i64 1
223    %3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<16 x s8>), %4(s64)
224    %7:gpr(s8) = COPY %3(s8)
225    %6:gpr(s32) = G_SEXT %7(s8)
226    $w0 = COPY %6(s32)
227    RET_ReallyLR implicit $w0
228...
229---
230name:            zi16
231legalized:       true
232regBankSelected: true
233tracksRegLiveness: true
234body: |
235  bb.0:
236    liveins: $q0, $w0
237
238    ; CHECK-LABEL: name: zi16
239    ; CHECK: liveins: $q0, $w0
240    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
241    ; CHECK: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[COPY]], 1
242    ; CHECK: $w0 = COPY [[UMOVvi8_]]
243    ; CHECK: RET_ReallyLR implicit $w0
244    %0:fpr(<16 x s8>) = COPY $q0
245    %4:gpr(s64) = G_CONSTANT i64 1
246    %3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<16 x s8>), %4(s64)
247    %7:gpr(s8) = COPY %3(s8)
248    %6:gpr(s32) = G_ZEXT %7(s8)
249    $w0 = COPY %6(s32)
250    RET_ReallyLR implicit $w0
251
252...
253---
254name:            si16_2
255legalized:       true
256regBankSelected: true
257tracksRegLiveness: true
258body: |
259  bb.0:
260    liveins: $d0, $w0
261
262    ; CHECK-LABEL: name: si16_2
263    ; CHECK: liveins: $d0, $w0
264    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
265    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
266    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
267    ; CHECK: [[SMOVvi8to32_:%[0-9]+]]:gpr32 = SMOVvi8to32 [[INSERT_SUBREG]], 1
268    ; CHECK: $w0 = COPY [[SMOVvi8to32_]]
269    ; CHECK: RET_ReallyLR implicit $w0
270    %0:fpr(<8 x s8>) = COPY $d0
271    %4:gpr(s64) = G_CONSTANT i64 1
272    %3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<8 x s8>), %4(s64)
273    %7:gpr(s8) = COPY %3(s8)
274    %6:gpr(s32) = G_SEXT %7(s8)
275    $w0 = COPY %6(s32)
276    RET_ReallyLR implicit $w0
277...
278---
279name:            zi16_2
280legalized:       true
281regBankSelected: true
282tracksRegLiveness: true
283body: |
284  bb.0:
285    liveins: $d0, $w0
286
287    ; CHECK-LABEL: name: zi16_2
288    ; CHECK: liveins: $d0, $w0
289    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
290    ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
291    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
292    ; CHECK: [[UMOVvi8_:%[0-9]+]]:gpr32 = UMOVvi8 [[INSERT_SUBREG]], 1
293    ; CHECK: $w0 = COPY [[UMOVvi8_]]
294    ; CHECK: RET_ReallyLR implicit $w0
295    %0:fpr(<8 x s8>) = COPY $d0
296    %4:gpr(s64) = G_CONSTANT i64 1
297    %3:fpr(s8) = G_EXTRACT_VECTOR_ELT %0(<8 x s8>), %4(s64)
298    %7:gpr(s8) = COPY %3(s8)
299    %6:gpr(s32) = G_ZEXT %7(s8)
300    $w0 = COPY %6(s32)
301    RET_ReallyLR implicit $w0
302
303...
304---
305name:            skip_anyext_to_16
306legalized:       true
307regBankSelected: true
308tracksRegLiveness: true
309body:             |
310  bb.1.entry:
311    %5:fpr(<16 x s8>) = G_IMPLICIT_DEF
312    %12:gpr(s64) = G_CONSTANT i64 0
313    %4:fpr(s8) = G_EXTRACT_VECTOR_ELT %5(<16 x s8>), %12(s64)
314    %11:gpr(s8) = COPY %4(s8)
315    %8:gpr(s16) = G_ANYEXT %11(s8)
316    %ext:gpr(s32) = G_ANYEXT %8(s16)
317    $w0 = COPY %ext(s32)
318...
319