xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/select-ext.mir (revision 69069509b2d3cb0e0bcf6e38e0ab05c432adc763)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3#
4# Test G_EXT selection using AArch64ext patterns.
5
6...
7---
8name:            v8s8_EXTv8i8
9alignment:       4
10legalized:       true
11regBankSelected: true
12tracksRegLiveness: true
13body:             |
14  bb.0:
15    liveins: $d0, $d1
16
17    ; CHECK-LABEL: name: v8s8_EXTv8i8
18    ; CHECK: liveins: $d0, $d1
19    ; CHECK: %v1:fpr64 = COPY $d0
20    ; CHECK: %v2:fpr64 = COPY $d1
21    ; CHECK: %shuf:fpr64 = EXTv8i8 %v1, %v2, 3
22    ; CHECK: $d0 = COPY %shuf
23    %v1:fpr(<8 x s8>) = COPY $d0
24    %v2:fpr(<8 x s8>) = COPY $d1
25    %3:gpr(s32) = G_CONSTANT i32 3
26    %shuf:fpr(<8 x s8>) = G_EXT %v1, %v2, %3(s32)
27    $d0 = COPY %shuf
28
29...
30---
31name:            v16s8_EXTv16i8
32alignment:       4
33legalized:       true
34regBankSelected: true
35tracksRegLiveness: true
36body:             |
37  bb.0:
38    liveins: $q0, $q1
39
40    ; CHECK-LABEL: name: v16s8_EXTv16i8
41    ; CHECK: liveins: $q0, $q1
42    ; CHECK: %v1:fpr128 = COPY $q0
43    ; CHECK: %v2:fpr128 = COPY $q1
44    ; CHECK: %shuf:fpr128 = EXTv16i8 %v1, %v2, 3
45    ; CHECK: $q0 = COPY %shuf
46    %v1:fpr(<16 x s8>) = COPY $q0
47    %v2:fpr(<16 x s8>) = COPY $q1
48    %3:gpr(s32) = G_CONSTANT i32 3
49    %shuf:fpr(<16 x s8>) = G_EXT %v1, %v2, %3(s32)
50    $q0 = COPY %shuf
51
52...
53---
54name:            v4s16_EXTv8i8
55alignment:       4
56legalized:       true
57regBankSelected: true
58tracksRegLiveness: true
59body:             |
60  bb.0:
61    liveins: $d0, $d1
62
63    ; CHECK-LABEL: name: v4s16_EXTv8i8
64    ; CHECK: liveins: $d0, $d1
65    ; CHECK: %v1:fpr64 = COPY $d0
66    ; CHECK: %v2:fpr64 = COPY $d1
67    ; CHECK: %shuf:fpr64 = EXTv8i8 %v1, %v2, 6
68    ; CHECK: $d0 = COPY %shuf
69    %v1:fpr(<4 x s16>) = COPY $d0
70    %v2:fpr(<4 x s16>) = COPY $d1
71    %3:gpr(s32) = G_CONSTANT i32 6
72    %shuf:fpr(<4 x s16>) = G_EXT %v1, %v2, %3(s32)
73    $d0 = COPY %shuf
74
75...
76---
77name:            v8s16_EXTv16i8
78alignment:       4
79legalized:       true
80regBankSelected: true
81tracksRegLiveness: true
82body:             |
83  bb.0:
84    liveins: $q0, $q1
85
86    ; CHECK-LABEL: name: v8s16_EXTv16i8
87    ; CHECK: liveins: $q0, $q1
88    ; CHECK: %v1:fpr128 = COPY $q0
89    ; CHECK: %v2:fpr128 = COPY $q1
90    ; CHECK: %shuf:fpr128 = EXTv16i8 %v2, %v1, 10
91    ; CHECK: $q0 = COPY %shuf
92    %v1:fpr(<8 x s16>) = COPY $q0
93    %v2:fpr(<8 x s16>) = COPY $q1
94    %3:gpr(s32) = G_CONSTANT i32 10
95    %shuf:fpr(<8 x s16>) = G_EXT %v2, %v1, %3(s32)
96    $q0 = COPY %shuf
97...
98
99...
100---
101name:            v4s32_EXTv16i8
102alignment:       4
103legalized:       true
104regBankSelected: true
105tracksRegLiveness: true
106body:             |
107  bb.0:
108    liveins: $q0, $q1
109
110    ; CHECK-LABEL: name: v4s32_EXTv16i8
111    ; CHECK: liveins: $q0, $q1
112    ; CHECK: %v1:fpr128 = COPY $q0
113    ; CHECK: %v2:fpr128 = COPY $q1
114    ; CHECK: %shuf:fpr128 = EXTv16i8 %v1, %v2, 12
115    ; CHECK: $q0 = COPY %shuf
116    %v1:fpr(<4 x s32>) = COPY $q0
117    %v2:fpr(<4 x s32>) = COPY $q1
118    %3:gpr(s32) = G_CONSTANT i32 12
119    %shuf:fpr(<4 x s32>) = G_EXT %v1, %v2, %3(s32)
120    $q0 = COPY %shuf
121
122...
123---
124name:            v2s32_EXTv8i8
125alignment:       4
126legalized:       true
127regBankSelected: true
128tracksRegLiveness: true
129body:             |
130  bb.0:
131    liveins: $d0, $d1
132
133    ; CHECK-LABEL: name: v2s32_EXTv8i8
134    ; CHECK: liveins: $d0, $d1
135    ; CHECK: %v1:fpr64 = COPY $d0
136    ; CHECK: %v2:fpr64 = COPY $d1
137    ; CHECK: %shuf:fpr64 = EXTv8i8 %v1, %v2, 2
138    ; CHECK: $d0 = COPY %shuf
139    %v1:fpr(<2 x s32>) = COPY $d0
140    %v2:fpr(<2 x s32>) = COPY $d1
141    %3:gpr(s32) = G_CONSTANT i32 2
142    %shuf:fpr(<2 x s32>) = G_EXT %v1, %v2, %3(s32)
143    $d0 = COPY %shuf
144
145...
146---
147name:            v2s64_EXTv16i8
148alignment:       4
149legalized:       true
150regBankSelected: true
151tracksRegLiveness: true
152body:             |
153  bb.0:
154    liveins: $q0, $q1
155
156    ; CHECK-LABEL: name: v2s64_EXTv16i8
157    ; CHECK: liveins: $q0, $q1
158    ; CHECK: %v1:fpr128 = COPY $q0
159    ; CHECK: %v2:fpr128 = COPY $q1
160    ; CHECK: %shuf:fpr128 = EXTv16i8 %v1, %v2, 2
161    ; CHECK: $q0 = COPY %shuf
162    %v1:fpr(<2 x s64>) = COPY $q0
163    %v2:fpr(<2 x s64>) = COPY $q1
164    %3:gpr(s32) = G_CONSTANT i32 2
165    %shuf:fpr(<2 x s64>) = G_EXT %v1, %v2, %3(s32)
166    $q0 = COPY %shuf
167...
168