1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3--- 4name: test_constant_vec_pool_v2f64 5alignment: 4 6legalized: true 7regBankSelected: true 8tracksRegLiveness: true 9liveins: 10 - { reg: '$x0' } 11frameInfo: 12 maxAlignment: 1 13machineFunctionInfo: {} 14body: | 15 bb.1: 16 liveins: $x0 17 18 ; CHECK-LABEL: name: test_constant_vec_pool_v2f64 19 ; CHECK: liveins: $x0 20 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 21 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 22 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 23 ; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<2 x s64>)) 24 ; CHECK: RET_ReallyLR 25 %0:gpr(p0) = COPY $x0 26 %3:fpr(s64) = G_FCONSTANT double 5.000000e-01 27 %2:fpr(s64) = G_FCONSTANT double 1.600000e+01 28 %1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64) 29 G_STORE %1(<2 x s64>), %0(p0) :: (store (<2 x s64>)) 30 RET_ReallyLR 31 32... 33--- 34name: test_constant_vec_pool_v4f32 35alignment: 4 36legalized: true 37regBankSelected: true 38tracksRegLiveness: true 39liveins: 40 - { reg: '$x0' } 41frameInfo: 42 maxAlignment: 1 43body: | 44 bb.1: 45 liveins: $x0 46 47 ; CHECK-LABEL: name: test_constant_vec_pool_v4f32 48 ; CHECK: liveins: $x0 49 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 50 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 51 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 52 ; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<4 x s32>)) 53 ; CHECK: RET_ReallyLR 54 %0:gpr(p0) = COPY $x0 55 %3:fpr(s32) = G_FCONSTANT float 5.000000e-01 56 %2:fpr(s32) = G_FCONSTANT float 1.600000e+01 57 %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32), %3(s32), %3(s32) 58 G_STORE %1(<4 x s32>), %0(p0) :: (store (<4 x s32>)) 59 RET_ReallyLR 60 61... 62--- 63name: test_constant_vec_pool_v2i64 64alignment: 4 65legalized: true 66regBankSelected: true 67tracksRegLiveness: true 68liveins: 69 - { reg: '$x0' } 70frameInfo: 71 maxAlignment: 1 72body: | 73 bb.1: 74 liveins: $x0 75 76 ; CHECK-LABEL: name: test_constant_vec_pool_v2i64 77 ; CHECK: liveins: $x0 78 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 79 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 80 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 81 ; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<2 x s64>)) 82 ; CHECK: RET_ReallyLR 83 %0:gpr(p0) = COPY $x0 84 %3:gpr(s64) = G_CONSTANT i64 67839 85 %2:gpr(s64) = G_CONSTANT i64 12375 86 %1:fpr(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64) 87 G_STORE %1(<2 x s64>), %0(p0) :: (store (<2 x s64>)) 88 RET_ReallyLR 89 90... 91--- 92name: test_constant_vec_pool_v4i32 93alignment: 4 94legalized: true 95regBankSelected: true 96tracksRegLiveness: true 97liveins: 98 - { reg: '$x0' } 99frameInfo: 100 maxAlignment: 1 101body: | 102 bb.1: 103 liveins: $x0 104 105 ; CHECK-LABEL: name: test_constant_vec_pool_v4i32 106 ; CHECK: liveins: $x0 107 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 108 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 109 ; CHECK: [[LDRQui:%[0-9]+]]:fpr128 = LDRQui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 110 ; CHECK: STRQui [[LDRQui]], [[COPY]], 0 :: (store (<4 x s32>)) 111 ; CHECK: RET_ReallyLR 112 %0:gpr(p0) = COPY $x0 113 %3:gpr(s32) = G_CONSTANT i32 67839 114 %2:gpr(s32) = G_CONSTANT i32 12375 115 %1:fpr(<4 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32), %2(s32), %3(s32) 116 G_STORE %1(<4 x s32>), %0(p0) :: (store (<4 x s32>)) 117 RET_ReallyLR 118 119... 120 121--- 122name: test_constant_vec_pool_v2i32 123alignment: 4 124legalized: true 125regBankSelected: true 126tracksRegLiveness: true 127liveins: 128 - { reg: '$x0' } 129frameInfo: 130 maxAlignment: 1 131body: | 132 bb.1: 133 liveins: $x0 134 135 ; CHECK-LABEL: name: test_constant_vec_pool_v2i32 136 ; CHECK: liveins: $x0 137 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 138 ; CHECK: [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) %const.0 139 ; CHECK: [[LDRDui:%[0-9]+]]:fpr64 = LDRDui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) %const.0 140 ; CHECK: STRDui [[LDRDui]], [[COPY]], 0 :: (store (<2 x s32>)) 141 ; CHECK: RET_ReallyLR 142 %0:gpr(p0) = COPY $x0 143 %3:gpr(s32) = G_CONSTANT i32 67839 144 %2:gpr(s32) = G_CONSTANT i32 12375 145 %1:fpr(<2 x s32>) = G_BUILD_VECTOR %2(s32), %3(s32) 146 G_STORE %1(<2 x s32>), %0(p0) :: (store (<2 x s32>)) 147 RET_ReallyLR 148 149... 150