1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3--- 4name: cmp_imm_32 5legalized: true 6regBankSelected: true 7tracksRegLiveness: true 8body: | 9 bb.1: 10 liveins: $w0 11 12 ; CHECK-LABEL: name: cmp_imm_32 13 ; CHECK: liveins: $w0 14 ; CHECK-NEXT: {{ $}} 15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 16 ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv 17 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv 18 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]] 19 ; CHECK-NEXT: RET_ReallyLR implicit $w0 20 %0:gpr(s32) = COPY $w0 21 %1:gpr(s32) = G_CONSTANT i32 42 22 %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %1 23 $w0 = COPY %5(s32) 24 RET_ReallyLR implicit $w0 25 26... 27--- 28name: cmp_imm_64 29legalized: true 30regBankSelected: true 31tracksRegLiveness: true 32body: | 33 bb.1: 34 liveins: $x0 35 36 ; CHECK-LABEL: name: cmp_imm_64 37 ; CHECK: liveins: $x0 38 ; CHECK-NEXT: {{ $}} 39 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 40 ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 42, 0, implicit-def $nzcv 41 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv 42 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]] 43 ; CHECK-NEXT: RET_ReallyLR implicit $w0 44 %0:gpr(s64) = COPY $x0 45 %1:gpr(s64) = G_CONSTANT i64 42 46 %5:gpr(s32) = G_ICMP intpred(eq), %0(s64), %1 47 $w0 = COPY %5(s32) 48 RET_ReallyLR implicit $w0 49 50... 51--- 52name: cmp_imm_out_of_range 53legalized: true 54regBankSelected: true 55tracksRegLiveness: true 56body: | 57 bb.1: 58 liveins: $x0 59 60 ; CHECK-LABEL: name: cmp_imm_out_of_range 61 ; CHECK: liveins: $x0 62 ; CHECK-NEXT: {{ $}} 63 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 64 ; CHECK-NEXT: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 13132 65 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 66 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[SUBREG_TO_REG]], implicit-def $nzcv 67 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv 68 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]] 69 ; CHECK-NEXT: RET_ReallyLR implicit $w0 70 %0:gpr(s64) = COPY $x0 71 %1:gpr(s64) = G_CONSTANT i64 13132 72 %5:gpr(s32) = G_ICMP intpred(eq), %0(s64), %1 73 $w0 = COPY %5(s32) 74 RET_ReallyLR implicit $w0 75 76... 77--- 78name: cmp_imm_lookthrough 79legalized: true 80regBankSelected: true 81tracksRegLiveness: true 82body: | 83 bb.1: 84 liveins: $w0 85 ; CHECK-LABEL: name: cmp_imm_lookthrough 86 ; CHECK: liveins: $w0 87 ; CHECK-NEXT: {{ $}} 88 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 89 ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 42, 0, implicit-def $nzcv 90 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv 91 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]] 92 ; CHECK-NEXT: RET_ReallyLR implicit $w0 93 %0:gpr(s32) = COPY $w0 94 %1:gpr(s64) = G_CONSTANT i64 42 95 %2:gpr(s32) = G_TRUNC %1(s64) 96 %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2 97 $w0 = COPY %5(s32) 98 RET_ReallyLR implicit $w0 99 100... 101--- 102name: cmp_imm_lookthrough_bad_trunc 103legalized: true 104regBankSelected: true 105tracksRegLiveness: true 106body: | 107 bb.1: 108 liveins: $w0 109 ; CHECK-LABEL: name: cmp_imm_lookthrough_bad_trunc 110 ; CHECK: liveins: $w0 111 ; CHECK-NEXT: {{ $}} 112 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 113 ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 0, 0, implicit-def $nzcv 114 ; CHECK-NEXT: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv 115 ; CHECK-NEXT: $w0 = COPY [[CSINCWr]] 116 ; CHECK-NEXT: RET_ReallyLR implicit $w0 117 %0:gpr(s32) = COPY $w0 118 %1:gpr(s64) = G_CONSTANT i64 68719476736 ; 0x1000000000 119 %2:gpr(s32) = G_TRUNC %1(s64) ; Value truncates to 0 120 %5:gpr(s32) = G_ICMP intpred(eq), %0(s32), %2 121 $w0 = COPY %5(s32) 122 RET_ReallyLR implicit $w0 123 124... 125--- 126name: cmp_neg_imm_32 127legalized: true 128regBankSelected: true 129tracksRegLiveness: true 130body: | 131 bb.1: 132 liveins: $w0 133 ; CHECK-LABEL: name: cmp_neg_imm_32 134 ; CHECK: liveins: $w0 135 ; CHECK-NEXT: {{ $}} 136 ; CHECK-NEXT: %reg0:gpr32sp = COPY $w0 137 ; CHECK-NEXT: [[ADDSWri:%[0-9]+]]:gpr32 = ADDSWri %reg0, 10, 0, implicit-def $nzcv 138 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv 139 ; CHECK-NEXT: $w0 = COPY %cmp 140 ; CHECK-NEXT: RET_ReallyLR implicit $w0 141 %reg0:gpr(s32) = COPY $w0 142 %cst:gpr(s32) = G_CONSTANT i32 -10 143 %cmp:gpr(s32) = G_ICMP intpred(eq), %reg0(s32), %cst 144 $w0 = COPY %cmp(s32) 145 RET_ReallyLR implicit $w0 146 147... 148--- 149name: cmp_neg_imm_64 150legalized: true 151regBankSelected: true 152tracksRegLiveness: true 153body: | 154 bb.1: 155 liveins: $x0 156 ; CHECK-LABEL: name: cmp_neg_imm_64 157 ; CHECK: liveins: $x0 158 ; CHECK-NEXT: {{ $}} 159 ; CHECK-NEXT: %reg0:gpr64sp = COPY $x0 160 ; CHECK-NEXT: [[ADDSXri:%[0-9]+]]:gpr64 = ADDSXri %reg0, 10, 0, implicit-def $nzcv 161 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv 162 ; CHECK-NEXT: $w0 = COPY %cmp 163 ; CHECK-NEXT: RET_ReallyLR implicit $w0 164 %reg0:gpr(s64) = COPY $x0 165 %cst:gpr(s64) = G_CONSTANT i64 -10 166 %cmp:gpr(s32) = G_ICMP intpred(eq), %reg0(s64), %cst 167 $w0 = COPY %cmp(s32) 168 RET_ReallyLR implicit $w0 169 170... 171--- 172name: cmp_neg_imm_invalid 173legalized: true 174regBankSelected: true 175tracksRegLiveness: true 176body: | 177 bb.1: 178 liveins: $w0 179 ; CHECK-LABEL: name: cmp_neg_imm_invalid 180 ; CHECK: liveins: $w0 181 ; CHECK-NEXT: {{ $}} 182 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0 183 ; CHECK-NEXT: %cst:gpr32 = MOVi32imm -5000 184 ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %reg0, %cst, implicit-def $nzcv 185 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv 186 ; CHECK-NEXT: $w0 = COPY %cmp 187 ; CHECK-NEXT: RET_ReallyLR implicit $w0 188 %reg0:gpr(s32) = COPY $w0 189 %cst:gpr(s32) = G_CONSTANT i32 -5000 190 %cmp:gpr(s32) = G_ICMP intpred(eq), %reg0(s32), %cst 191 $w0 = COPY %cmp(s32) 192 RET_ReallyLR implicit $w0 193... 194--- 195name: cmp_arith_extended_s64 196legalized: true 197regBankSelected: true 198tracksRegLiveness: true 199body: | 200 bb.0: 201 liveins: $w0, $x1 202 203 ; CHECK-LABEL: name: cmp_arith_extended_s64 204 ; CHECK: liveins: $w0, $x1 205 ; CHECK-NEXT: {{ $}} 206 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0 207 ; CHECK-NEXT: %reg1:gpr64sp = COPY $x1 208 ; CHECK-NEXT: [[SUBSXrx:%[0-9]+]]:gpr64 = SUBSXrx %reg1, %reg0, 18, implicit-def $nzcv 209 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv 210 ; CHECK-NEXT: $w0 = COPY %cmp 211 ; CHECK-NEXT: RET_ReallyLR implicit $w0 212 %reg0:gpr(s32) = COPY $w0 213 %reg1:gpr(s64) = COPY $x1 214 %ext:gpr(s64) = G_ZEXT %reg0(s32) 215 %cst:gpr(s64) = G_CONSTANT i64 2 216 %shift:gpr(s64) = G_SHL %ext, %cst(s64) 217 %cmp:gpr(s32) = G_ICMP intpred(ugt), %reg1(s64), %shift 218 $w0 = COPY %cmp(s32) 219 RET_ReallyLR implicit $w0 220 221... 222--- 223name: cmp_arith_extended_s32 224legalized: true 225regBankSelected: true 226tracksRegLiveness: true 227body: | 228 bb.0: 229 liveins: $w0, $w1, $h0 230 231 ; CHECK-LABEL: name: cmp_arith_extended_s32 232 ; CHECK: liveins: $w0, $w1, $h0 233 ; CHECK-NEXT: {{ $}} 234 ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:fpr32 = SUBREG_TO_REG 0, $h0, %subreg.hsub 235 ; CHECK-NEXT: %reg0:gpr32all = COPY [[SUBREG_TO_REG]] 236 ; CHECK-NEXT: %reg1:gpr32sp = COPY $w1 237 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY %reg0 238 ; CHECK-NEXT: [[SUBSWrx:%[0-9]+]]:gpr32 = SUBSWrx %reg1, [[COPY]], 10, implicit-def $nzcv 239 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv 240 ; CHECK-NEXT: $w0 = COPY %cmp 241 ; CHECK-NEXT: RET_ReallyLR implicit $w0 242 %reg0:gpr(s16) = COPY $h0 243 %reg1:gpr(s32) = COPY $w1 244 %ext:gpr(s32) = G_ZEXT %reg0(s16) 245 %cst:gpr(s32) = G_CONSTANT i32 2 246 %shift:gpr(s32) = G_SHL %ext, %cst(s32) 247 %cmp:gpr(s32) = G_ICMP intpred(ugt), %reg1(s32), %shift 248 $w0 = COPY %cmp(s32) 249 RET_ReallyLR implicit $w0 250 251... 252--- 253name: cmp_arith_extended_shl_too_large 254legalized: true 255regBankSelected: true 256tracksRegLiveness: true 257body: | 258 bb.0: 259 liveins: $w0, $x1 260 261 ; The constant on the G_SHL is > 4, so we won't sleect SUBSXrx 262 263 ; CHECK-LABEL: name: cmp_arith_extended_shl_too_large 264 ; CHECK: liveins: $w0, $x1 265 ; CHECK-NEXT: {{ $}} 266 ; CHECK-NEXT: %reg0:gpr32 = COPY $w0 267 ; CHECK-NEXT: %reg1:gpr64 = COPY $x1 268 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %reg0, 0 269 ; CHECK-NEXT: %ext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 270 ; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs %reg1, %ext, 5, implicit-def $nzcv 271 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 9, implicit $nzcv 272 ; CHECK-NEXT: $w0 = COPY %cmp 273 ; CHECK-NEXT: RET_ReallyLR implicit $w0 274 %reg0:gpr(s32) = COPY $w0 275 %reg1:gpr(s64) = COPY $x1 276 %ext:gpr(s64) = G_ZEXT %reg0(s32) 277 %cst:gpr(s64) = G_CONSTANT i64 5 278 %shift:gpr(s64) = G_SHL %ext, %cst(s64) 279 %cmp:gpr(s32) = G_ICMP intpred(ugt), %reg1(s64), %shift 280 $w0 = COPY %cmp(s32) 281 RET_ReallyLR implicit $w0 282 283... 284--- 285name: cmp_add_rhs 286legalized: true 287regBankSelected: true 288tracksRegLiveness: true 289machineFunctionInfo: {} 290body: | 291 bb.0: 292 liveins: $w0, $w1, $w2 293 294 ; The CSINC should use the add's RHS. 295 296 ; CHECK-LABEL: name: cmp_add_rhs 297 ; CHECK: liveins: $w0, $w1, $w2 298 ; CHECK-NEXT: {{ $}} 299 ; CHECK-NEXT: %cmp_lhs:gpr32 = COPY $w0 300 ; CHECK-NEXT: %cmp_rhs:gpr32 = COPY $w1 301 ; CHECK-NEXT: %add_rhs:gpr32 = COPY $w2 302 ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv 303 ; CHECK-NEXT: %add:gpr32 = CSINCWr %add_rhs, %add_rhs, 1, implicit $nzcv 304 ; CHECK-NEXT: $w0 = COPY %add 305 ; CHECK-NEXT: RET_ReallyLR implicit $w0 306 %cmp_lhs:gpr(s32) = COPY $w0 307 %cmp_rhs:gpr(s32) = COPY $w1 308 %add_rhs:gpr(s32) = COPY $w2 309 %cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s32), %cmp_rhs 310 %add:gpr(s32) = G_ADD %cmp, %add_rhs 311 $w0 = COPY %add(s32) 312 RET_ReallyLR implicit $w0 313 314... 315--- 316name: cmp_add_lhs 317legalized: true 318regBankSelected: true 319tracksRegLiveness: true 320machineFunctionInfo: {} 321body: | 322 bb.0: 323 liveins: $w0, $w1, $w2 324 325 ; The CSINC should use the add's LHS. 326 327 ; CHECK-LABEL: name: cmp_add_lhs 328 ; CHECK: liveins: $w0, $w1, $w2 329 ; CHECK-NEXT: {{ $}} 330 ; CHECK-NEXT: %cmp_lhs:gpr32 = COPY $w0 331 ; CHECK-NEXT: %cmp_rhs:gpr32 = COPY $w1 332 ; CHECK-NEXT: %add_lhs:gpr32 = COPY $w2 333 ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv 334 ; CHECK-NEXT: %add:gpr32 = CSINCWr %add_lhs, %add_lhs, 1, implicit $nzcv 335 ; CHECK-NEXT: $w0 = COPY %add 336 ; CHECK-NEXT: RET_ReallyLR implicit $w0 337 %cmp_lhs:gpr(s32) = COPY $w0 338 %cmp_rhs:gpr(s32) = COPY $w1 339 %add_lhs:gpr(s32) = COPY $w2 340 %cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s32), %cmp_rhs 341 %add:gpr(s32) = G_ADD %add_lhs, %cmp 342 $w0 = COPY %add(s32) 343 RET_ReallyLR implicit $w0 344 345... 346--- 347name: cmp_add_lhs_vector 348legalized: true 349regBankSelected: true 350tracksRegLiveness: true 351machineFunctionInfo: {} 352body: | 353 bb.0: 354 liveins: $q0, $q1, $q2 355 356 ; We don't emit CSINC with vectors, so there should be no optimization here. 357 358 ; CHECK-LABEL: name: cmp_add_lhs_vector 359 ; CHECK: liveins: $q0, $q1, $q2 360 ; CHECK-NEXT: {{ $}} 361 ; CHECK-NEXT: %cmp_lhs:fpr128 = COPY $q0 362 ; CHECK-NEXT: %cmp_rhs:fpr128 = COPY $q1 363 ; CHECK-NEXT: %add_lhs:fpr128 = COPY $q2 364 ; CHECK-NEXT: %cmp:fpr128 = CMEQv4i32 %cmp_lhs, %cmp_rhs 365 ; CHECK-NEXT: %add:fpr128 = ADDv4i32 %add_lhs, %cmp 366 ; CHECK-NEXT: $q0 = COPY %add 367 ; CHECK-NEXT: RET_ReallyLR implicit $q0 368 %cmp_lhs:fpr(<4 x s32>) = COPY $q0 369 %cmp_rhs:fpr(<4 x s32>) = COPY $q1 370 %add_lhs:fpr(<4 x s32>) = COPY $q2 371 %cmp:fpr(<4 x s32>) = G_ICMP intpred(eq), %cmp_lhs(<4 x s32>), %cmp_rhs 372 %add:fpr(<4 x s32>) = G_ADD %add_lhs, %cmp 373 $q0 = COPY %add(<4 x s32>) 374 RET_ReallyLR implicit $q0 375 376... 377--- 378name: cmp_add_rhs_64 379legalized: true 380regBankSelected: true 381tracksRegLiveness: true 382machineFunctionInfo: {} 383body: | 384 bb.0: 385 liveins: $x0, $x1, $x2 386 387 ; The CSINC should use the add's RHS. 388 ; CHECK-LABEL: name: cmp_add_rhs_64 389 ; CHECK: liveins: $x0, $x1, $x2 390 ; CHECK-NEXT: {{ $}} 391 ; CHECK-NEXT: %cmp_lhs:gpr64 = COPY $x0 392 ; CHECK-NEXT: %cmp_rhs:gpr64 = COPY $x1 393 ; CHECK-NEXT: %add_rhs:gpr64 = COPY $x2 394 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv 395 ; CHECK-NEXT: %add:gpr64 = CSINCXr %add_rhs, %add_rhs, 1, implicit $nzcv 396 ; CHECK-NEXT: $x0 = COPY %add 397 ; CHECK-NEXT: RET_ReallyLR implicit $x0 398 %cmp_lhs:gpr(s64) = COPY $x0 399 %cmp_rhs:gpr(s64) = COPY $x1 400 %add_rhs:gpr(s64) = COPY $x2 401 %cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs 402 %cmp_ext:gpr(s64) = G_ZEXT %cmp 403 %add:gpr(s64) = G_ADD %cmp_ext, %add_rhs 404 $x0 = COPY %add(s64) 405 RET_ReallyLR implicit $x0 406 407... 408--- 409name: cmp_add_rhs_64_zext_multi_use 410legalized: true 411regBankSelected: true 412tracksRegLiveness: true 413machineFunctionInfo: {} 414body: | 415 bb.0: 416 liveins: $x0, $x1, $x2 417 418 ; The ZExt is used more than once so don't fold. 419 ; CHECK-LABEL: name: cmp_add_rhs_64_zext_multi_use 420 ; CHECK: liveins: $x0, $x1, $x2 421 ; CHECK-NEXT: {{ $}} 422 ; CHECK-NEXT: %cmp_lhs:gpr64 = COPY $x0 423 ; CHECK-NEXT: %cmp_rhs:gpr64 = COPY $x1 424 ; CHECK-NEXT: %add_rhs:gpr64 = COPY $x2 425 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv 426 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv 427 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %cmp, 0 428 ; CHECK-NEXT: %cmp_ext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 429 ; CHECK-NEXT: %add:gpr64 = ADDXrr %cmp_ext, %add_rhs 430 ; CHECK-NEXT: %or:gpr64 = ORRXrr %add, %cmp_ext 431 ; CHECK-NEXT: $x0 = COPY %or 432 ; CHECK-NEXT: RET_ReallyLR implicit $x0 433 %cmp_lhs:gpr(s64) = COPY $x0 434 %cmp_rhs:gpr(s64) = COPY $x1 435 %add_rhs:gpr(s64) = COPY $x2 436 %cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs 437 %cmp_ext:gpr(s64) = G_ZEXT %cmp 438 %add:gpr(s64) = G_ADD %cmp_ext, %add_rhs 439 %or:gpr(s64) = G_OR %add, %cmp_ext 440 $x0 = COPY %or(s64) 441 RET_ReallyLR implicit $x0 442 443... 444--- 445name: cmp_add_rhs_64_cmp_multi_use 446legalized: true 447regBankSelected: true 448tracksRegLiveness: true 449machineFunctionInfo: {} 450body: | 451 bb.0: 452 liveins: $x0, $x1, $x2 453 454 ; The cmp is used more than once so don't fold. 455 ; CHECK-LABEL: name: cmp_add_rhs_64_cmp_multi_use 456 ; CHECK: liveins: $x0, $x1, $x2 457 ; CHECK-NEXT: {{ $}} 458 ; CHECK-NEXT: %cmp_lhs:gpr64 = COPY $x0 459 ; CHECK-NEXT: %cmp_rhs:gpr64 = COPY $x1 460 ; CHECK-NEXT: %add_rhs:gpr64 = COPY $x2 461 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr %cmp_lhs, %cmp_rhs, implicit-def $nzcv 462 ; CHECK-NEXT: %cmp:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv 463 ; CHECK-NEXT: [[ORRWrs:%[0-9]+]]:gpr32 = ORRWrs $wzr, %cmp, 0 464 ; CHECK-NEXT: %cmp_ext:gpr64 = SUBREG_TO_REG 0, [[ORRWrs]], %subreg.sub_32 465 ; CHECK-NEXT: %add:gpr64 = ADDXrr %cmp_ext, %add_rhs 466 ; CHECK-NEXT: [[DEF:%[0-9]+]]:gpr64all = IMPLICIT_DEF 467 ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gpr64 = INSERT_SUBREG [[DEF]], %cmp, %subreg.sub_32 468 ; CHECK-NEXT: %cmp_ext2:gpr64 = SBFMXri [[INSERT_SUBREG]], 0, 31 469 ; CHECK-NEXT: %or:gpr64 = ORRXrr %add, %cmp_ext2 470 ; CHECK-NEXT: $x0 = COPY %or 471 ; CHECK-NEXT: RET_ReallyLR implicit $x0 472 %cmp_lhs:gpr(s64) = COPY $x0 473 %cmp_rhs:gpr(s64) = COPY $x1 474 %add_rhs:gpr(s64) = COPY $x2 475 %cmp:gpr(s32) = G_ICMP intpred(eq), %cmp_lhs(s64), %cmp_rhs 476 %cmp_ext:gpr(s64) = G_ZEXT %cmp 477 %add:gpr(s64) = G_ADD %cmp_ext, %add_rhs 478 %cmp_ext2:gpr(s64) = G_SEXT %cmp 479 %or:gpr(s64) = G_OR %add, %cmp_ext2 480 $x0 = COPY %or(s64) 481 RET_ReallyLR implicit $x0 482