1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3--- 4name: test_f32 5alignment: 4 6exposesReturnsTwice: false 7legalized: true 8regBankSelected: true 9selected: false 10failedISel: false 11tracksRegLiveness: true 12body: | 13 bb.0: 14 liveins: $s0, $s1, $s2, $s3 15 16 ; CHECK-LABEL: name: test_f32 17 ; CHECK: liveins: $s0, $s1, $s2, $s3 18 ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 19 ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 20 ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s2 21 ; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY $s3 22 ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF 23 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub 24 ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF 25 ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.ssub 26 ; CHECK: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 27 ; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF 28 ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY2]], %subreg.ssub 29 ; CHECK: [[INSvi32lane1:%[0-9]+]]:fpr128 = INSvi32lane [[INSvi32lane]], 2, [[INSERT_SUBREG2]], 0 30 ; CHECK: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF 31 ; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[COPY3]], %subreg.ssub 32 ; CHECK: [[INSvi32lane2:%[0-9]+]]:fpr128 = INSvi32lane [[INSvi32lane1]], 3, [[INSERT_SUBREG3]], 0 33 ; CHECK: $q0 = COPY [[INSvi32lane2]] 34 ; CHECK: RET_ReallyLR implicit $q0 35 %0:fpr(s32) = COPY $s0 36 %1:fpr(s32) = COPY $s1 37 %2:fpr(s32) = COPY $s2 38 %3:fpr(s32) = COPY $s3 39 %4:fpr(<4 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32), %2(s32), %3(s32) 40 $q0 = COPY %4(<4 x s32>) 41 RET_ReallyLR implicit $q0 42 43... 44--- 45name: test_f64 46alignment: 4 47exposesReturnsTwice: false 48legalized: true 49regBankSelected: true 50selected: false 51failedISel: false 52tracksRegLiveness: true 53body: | 54 bb.0: 55 liveins: $d0, $d1, $d2, $d3 56 57 ; CHECK-LABEL: name: test_f64 58 ; CHECK: liveins: $d0, $d1, $d2, $d3 59 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 60 ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 61 ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF 62 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub 63 ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF 64 ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub 65 ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 66 ; CHECK: $q0 = COPY [[INSvi64lane]] 67 ; CHECK: RET_ReallyLR implicit $q0 68 %0:fpr(s64) = COPY $d0 69 %1:fpr(s64) = COPY $d1 70 %4:fpr(<2 x s64>) = G_BUILD_VECTOR %0(s64), %1(s64) 71 $q0 = COPY %4(<2 x s64>) 72 RET_ReallyLR implicit $q0 73 74... 75--- 76name: test_i32 77alignment: 4 78exposesReturnsTwice: false 79legalized: true 80regBankSelected: true 81selected: false 82failedISel: false 83tracksRegLiveness: true 84body: | 85 bb.0: 86 liveins: $w0, $w1, $w2, $w3 87 88 ; CHECK-LABEL: name: test_i32 89 ; CHECK: liveins: $w0, $w1, $w2, $w3 90 ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY $w0 91 ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 92 ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2 93 ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY $w3 94 ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF 95 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub 96 ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[COPY1]] 97 ; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSvi32gpr]], 2, [[COPY2]] 98 ; CHECK: [[INSvi32gpr2:%[0-9]+]]:fpr128 = INSvi32gpr [[INSvi32gpr1]], 3, [[COPY3]] 99 ; CHECK: $q0 = COPY [[INSvi32gpr2]] 100 ; CHECK: RET_ReallyLR implicit $q0 101 %0:gpr(s32) = COPY $w0 102 %1:gpr(s32) = COPY $w1 103 %2:gpr(s32) = COPY $w2 104 %3:gpr(s32) = COPY $w3 105 %4:fpr(<4 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32), %2(s32), %3(s32) 106 $q0 = COPY %4(<4 x s32>) 107 RET_ReallyLR implicit $q0 108 109... 110--- 111name: test_i64 112alignment: 4 113exposesReturnsTwice: false 114legalized: true 115regBankSelected: true 116selected: false 117failedISel: false 118tracksRegLiveness: true 119body: | 120 bb.0: 121 liveins: $x0, $x1 122 123 ; CHECK-LABEL: name: test_i64 124 ; CHECK: liveins: $x0, $x1 125 ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0 126 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 127 ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF 128 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub 129 ; CHECK: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[INSERT_SUBREG]], 1, [[COPY1]] 130 ; CHECK: $q0 = COPY [[INSvi64gpr]] 131 ; CHECK: RET_ReallyLR implicit $q0 132 %0:gpr(s64) = COPY $x0 133 %1:gpr(s64) = COPY $x1 134 %4:fpr(<2 x s64>) = G_BUILD_VECTOR %0(s64), %1(s64) 135 $q0 = COPY %4(<2 x s64>) 136 RET_ReallyLR implicit $q0 137 138... 139--- 140name: test_p0 141alignment: 4 142exposesReturnsTwice: false 143legalized: true 144regBankSelected: true 145selected: false 146failedISel: false 147tracksRegLiveness: true 148body: | 149 bb.0: 150 liveins: $x0, $x1 151 152 ; CHECK-LABEL: name: test_p0 153 ; CHECK: liveins: $x0, $x1 154 ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0 155 ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 156 ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF 157 ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub 158 ; CHECK: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[INSERT_SUBREG]], 1, [[COPY1]] 159 ; CHECK: $q0 = COPY [[INSvi64gpr]] 160 ; CHECK: RET_ReallyLR implicit $q0 161 %0:gpr(p0) = COPY $x0 162 %1:gpr(p0) = COPY $x1 163 %4:fpr(<2 x p0>) = G_BUILD_VECTOR %0(p0), %1(p0) 164 $q0 = COPY %4(<2 x p0>) 165 RET_ReallyLR implicit $q0 166 167... 168--- 169name: test_v4s32_zero 170legalized: true 171regBankSelected: true 172tracksRegLiveness: true 173liveins: 174 - { reg: '$x0' } 175frameInfo: 176 maxAlignment: 1 177machineFunctionInfo: {} 178body: | 179 bb.1: 180 liveins: $x0 181 182 ; CHECK-LABEL: name: test_v4s32_zero 183 ; CHECK: liveins: $x0 184 ; CHECK: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0 185 ; CHECK: $q0 = COPY [[MOVIv2d_ns]] 186 ; CHECK: RET_ReallyLR 187 %0:gpr(p0) = COPY $x0 188 %2:gpr(s32) = G_CONSTANT i32 0 189 %3:fpr(s32) = COPY %2(s32) 190 %4:fpr(s32) = COPY %2(s32) 191 %5:fpr(s32) = COPY %2(s32) 192 %6:fpr(s32) = COPY %2(s32) 193 %1:fpr(<4 x s32>) = G_BUILD_VECTOR %3(s32), %4(s32), %5(s32), %6(s32) 194 $q0 = COPY %1(<4 x s32>) 195 RET_ReallyLR 196... 197--- 198name: test_v8s8_zero 199legalized: true 200regBankSelected: true 201tracksRegLiveness: true 202liveins: 203 - { reg: '$x0' } 204frameInfo: 205 maxAlignment: 1 206machineFunctionInfo: {} 207body: | 208 bb.1: 209 liveins: $x0 210 211 ; CHECK-LABEL: name: test_v8s8_zero 212 ; CHECK: liveins: $x0 213 ; CHECK: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0 214 ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub 215 ; CHECK: $d0 = COPY [[COPY]] 216 ; CHECK: RET_ReallyLR 217 %0:gpr(p0) = COPY $x0 218 %2:gpr(s8) = G_CONSTANT i8 0 219 %3:fpr(s8) = COPY %2(s8) 220 %4:fpr(s8) = COPY %2(s8) 221 %5:fpr(s8) = COPY %2(s8) 222 %6:fpr(s8) = COPY %2(s8) 223 %7:fpr(s8) = COPY %2(s8) 224 %8:fpr(s8) = COPY %2(s8) 225 %9:fpr(s8) = COPY %2(s8) 226 %10:fpr(s8) = COPY %2(s8) 227 %1:fpr(<8 x s8>) = G_BUILD_VECTOR %3(s8), %4(s8), %5(s8), %6(s8), %7(s8), %8(s8), %9(s8), %10(s8) 228 $d0 = COPY %1(<8 x s8>) 229 RET_ReallyLR 230... 231--- 232name: undef_elts_to_subreg_to_reg 233legalized: true 234regBankSelected: true 235tracksRegLiveness: true 236body: | 237 bb.1: 238 liveins: $s0 239 ; We have a BUILD_VECTOR whose 0th element is a subregister of the wide 240 ; register class. Everything else is undef. This is a SUBREG_TO_REG. 241 242 ; CHECK-LABEL: name: undef_elts_to_subreg_to_reg 243 ; CHECK: liveins: $s0 244 ; CHECK: %val:fpr32 = COPY $s0 245 ; CHECK: %bv:fpr128 = SUBREG_TO_REG 0, %val, %subreg.ssub 246 ; CHECK: $q0 = COPY %bv 247 ; CHECK: RET_ReallyLR implicit $q0 248 %val:fpr(s32) = COPY $s0 249 %undef:fpr(s32) = G_IMPLICIT_DEF 250 %bv:fpr(<4 x s32>) = G_BUILD_VECTOR %val(s32), %undef(s32), %undef(s32), %undef(s32) 251 $q0 = COPY %bv(<4 x s32>) 252 RET_ReallyLR implicit $q0 253... 254... 255--- 256name: undef_elts_different_regbanks 257legalized: true 258regBankSelected: true 259tracksRegLiveness: true 260body: | 261 bb.1: 262 liveins: $w0 263 ; Element is not a subregister of the wide register class. This is not a 264 ; SUBREG_TO_REG. 265 266 ; CHECK-LABEL: name: undef_elts_different_regbanks 267 ; CHECK: liveins: $w0 268 ; CHECK: %val:gpr32all = COPY $w0 269 ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF 270 ; CHECK: %bv:fpr128 = INSERT_SUBREG [[DEF]], %val, %subreg.ssub 271 ; CHECK: $q0 = COPY %bv 272 ; CHECK: RET_ReallyLR implicit $q0 273 %val:gpr(s32) = COPY $w0 274 %undef:gpr(s32) = G_IMPLICIT_DEF 275 %bv:fpr(<4 x s32>) = G_BUILD_VECTOR %val(s32), %undef(s32), %undef(s32), %undef(s32) 276 $q0 = COPY %bv(<4 x s32>) 277 RET_ReallyLR implicit $q0 278... 279