xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/select-bitreverse.mir (revision 1b894ccdc9ee8419e81499b2d394a00c0b880db1) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple aarch64 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3
4...
5---
6name:            s32
7legalized:       true
8regBankSelected: true
9tracksRegLiveness: true
10body:             |
11  bb.0:
12    liveins: $w0
13
14    ; CHECK-LABEL: name: s32
15    ; CHECK: liveins: $w0
16    ; CHECK: %copy:gpr32 = COPY $w0
17    ; CHECK: %bitreverse:gpr32 = RBITWr %copy
18    ; CHECK: $w0 = COPY %bitreverse
19    ; CHECK: RET_ReallyLR implicit $w0
20    %copy:gpr(s32) = COPY $w0
21    %bitreverse:gpr(s32) = G_BITREVERSE %copy
22    $w0 = COPY %bitreverse(s32)
23    RET_ReallyLR implicit $w0
24
25...
26---
27name:            s64
28legalized:       true
29regBankSelected: true
30tracksRegLiveness: true
31body:             |
32  bb.0:
33    liveins: $x0
34
35    ; CHECK-LABEL: name: s64
36    ; CHECK: liveins: $x0
37    ; CHECK: %copy:gpr64 = COPY $x0
38    ; CHECK: %bitreverse:gpr64 = RBITXr %copy
39    ; CHECK: $x0 = COPY %bitreverse
40    ; CHECK: RET_ReallyLR implicit $x0
41    %copy:gpr(s64) = COPY $x0
42    %bitreverse:gpr(s64) = G_BITREVERSE %copy
43    $x0 = COPY %bitreverse(s64)
44    RET_ReallyLR implicit $x0
45
46...
47---
48name:            v8s8_legal
49legalized:       true
50regBankSelected: true
51tracksRegLiveness: true
52body:             |
53  bb.0:
54    liveins: $x0
55
56    ; CHECK-LABEL: name: v8s8_legal
57    ; CHECK: liveins: $x0
58    ; CHECK: %vec:fpr64 = IMPLICIT_DEF
59    ; CHECK: %bitreverse:fpr64 = RBITv8i8 %vec
60    ; CHECK: $x0 = COPY %bitreverse
61    ; CHECK: RET_ReallyLR implicit $x0
62    %vec:fpr(<8 x s8>) = G_IMPLICIT_DEF
63    %bitreverse:fpr(<8 x s8>) = G_BITREVERSE %vec
64    $x0 = COPY %bitreverse(<8 x s8>)
65    RET_ReallyLR implicit $x0
66
67...
68---
69name:            v16s8_legal
70legalized:       true
71regBankSelected: true
72tracksRegLiveness: true
73body:             |
74  bb.0:
75    liveins: $q0
76
77    ; CHECK-LABEL: name: v16s8_legal
78    ; CHECK: liveins: $q0
79    ; CHECK: %vec:fpr128 = IMPLICIT_DEF
80    ; CHECK: %bitreverse:fpr128 = RBITv16i8 %vec
81    ; CHECK: $q0 = COPY %bitreverse
82    ; CHECK: RET_ReallyLR implicit $q0
83    %vec:fpr(<16 x s8>) = G_IMPLICIT_DEF
84    %bitreverse:fpr(<16 x s8>) = G_BITREVERSE %vec
85    $q0 = COPY %bitreverse(<16 x s8>)
86    RET_ReallyLR implicit $q0
87
88...
89