1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3--- 4# Check that we select a 32-bit GPR G_ADD into ADDWrr on GPR32. 5# Also check that we constrain the register class of the COPY to GPR32. 6name: add_s32_gpr 7legalized: true 8regBankSelected: true 9 10registers: 11 - { id: 0, class: gpr } 12 - { id: 1, class: gpr } 13 - { id: 2, class: gpr } 14 15body: | 16 bb.0: 17 liveins: $w0, $w1 18 19 ; CHECK-LABEL: name: add_s32_gpr 20 ; CHECK: liveins: $w0, $w1 21 ; CHECK-NEXT: {{ $}} 22 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 23 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 24 ; CHECK-NEXT: [[ADDWrr:%[0-9]+]]:gpr32 = ADDWrr [[COPY]], [[COPY1]] 25 ; CHECK-NEXT: $w0 = COPY [[ADDWrr]] 26 %0(s32) = COPY $w0 27 %1(s32) = COPY $w1 28 %2(s32) = G_ADD %0, %1 29 $w0 = COPY %2(s32) 30... 31 32--- 33# Same as add_s32_gpr, for 64-bit operations. 34name: add_s64_gpr 35legalized: true 36regBankSelected: true 37 38registers: 39 - { id: 0, class: gpr } 40 - { id: 1, class: gpr } 41 - { id: 2, class: gpr } 42 43body: | 44 bb.0: 45 liveins: $x0, $x1 46 47 ; CHECK-LABEL: name: add_s64_gpr 48 ; CHECK: liveins: $x0, $x1 49 ; CHECK-NEXT: {{ $}} 50 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 51 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 52 ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[COPY1]] 53 ; CHECK-NEXT: $x0 = COPY [[ADDXrr]] 54 %0(s64) = COPY $x0 55 %1(s64) = COPY $x1 56 %2(s64) = G_ADD %0, %1 57 $x0 = COPY %2(s64) 58... 59 60--- 61name: add_imm_s32_gpr 62legalized: true 63regBankSelected: true 64 65registers: 66 - { id: 0, class: gpr } 67 - { id: 1, class: gpr } 68 - { id: 2, class: gpr } 69 70body: | 71 bb.0: 72 liveins: $w0, $w1 73 74 ; CHECK-LABEL: name: add_imm_s32_gpr 75 ; CHECK: liveins: $w0, $w1 76 ; CHECK-NEXT: {{ $}} 77 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 78 ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0 79 ; CHECK-NEXT: $w0 = COPY [[ADDWri]] 80 %0(s32) = COPY $w0 81 %1(s32) = G_CONSTANT i32 1 82 %2(s32) = G_ADD %0, %1 83 $w0 = COPY %2(s32) 84... 85 86--- 87name: add_imm_s64_gpr 88legalized: true 89regBankSelected: true 90 91registers: 92 - { id: 0, class: gpr } 93 - { id: 1, class: gpr } 94 - { id: 2, class: gpr } 95 96body: | 97 bb.0: 98 liveins: $x0, $w1 99 100 ; CHECK-LABEL: name: add_imm_s64_gpr 101 ; CHECK: liveins: $x0, $w1 102 ; CHECK-NEXT: {{ $}} 103 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 104 ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 1, 0 105 ; CHECK-NEXT: $x0 = COPY [[ADDXri]] 106 %0(s64) = COPY $x0 107 %1(s64) = G_CONSTANT i64 1 108 %2(s64) = G_ADD %0, %1 109 $x0 = COPY %2(s64) 110... 111 112--- 113name: add_neg_s32_gpr 114legalized: true 115regBankSelected: true 116 117registers: 118 - { id: 0, class: gpr } 119 - { id: 1, class: gpr } 120 - { id: 2, class: gpr } 121 122body: | 123 bb.0: 124 liveins: $w1, $w2 125 ; We should be able to turn the ADD into a SUB. 126 ; CHECK-LABEL: name: add_neg_s32_gpr 127 ; CHECK: liveins: $w1, $w2 128 ; CHECK-NEXT: {{ $}} 129 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w1 130 ; CHECK-NEXT: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def dead $nzcv 131 ; CHECK-NEXT: $w2 = COPY [[SUBSWri]] 132 %0(s32) = COPY $w1 133 %1(s32) = G_CONSTANT i32 -1 134 %2(s32) = G_ADD %0, %1 135 $w2 = COPY %2(s32) 136... 137 138--- 139name: add_neg_s64_gpr 140legalized: true 141regBankSelected: true 142 143registers: 144 - { id: 0, class: gpr } 145 - { id: 1, class: gpr } 146 - { id: 2, class: gpr } 147 148body: | 149 bb.0: 150 liveins: $x0, $x1 151 ; We should be able to turn the ADD into a SUB. 152 ; CHECK-LABEL: name: add_neg_s64_gpr 153 ; CHECK: liveins: $x0, $x1 154 ; CHECK-NEXT: {{ $}} 155 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 156 ; CHECK-NEXT: [[SUBSXri:%[0-9]+]]:gpr64 = SUBSXri [[COPY]], 1, 0, implicit-def dead $nzcv 157 ; CHECK-NEXT: $x0 = COPY [[SUBSXri]] 158 %0(s64) = COPY $x0 159 %1(s64) = G_CONSTANT i64 -1 160 %2(s64) = G_ADD %0, %1 161 $x0 = COPY %2(s64) 162... 163 164--- 165name: add_neg_invalid_immed_s32 166legalized: true 167regBankSelected: true 168 169registers: 170 - { id: 0, class: gpr } 171 - { id: 1, class: gpr } 172 - { id: 2, class: gpr } 173 174body: | 175 bb.0: 176 liveins: $x0, $x1 177 ; We can't select this if the value is out of range. 178 ; CHECK-LABEL: name: add_neg_invalid_immed_s32 179 ; CHECK: liveins: $x0, $x1 180 ; CHECK-NEXT: {{ $}} 181 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 182 ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -5000 183 ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[MOVi64imm]] 184 ; CHECK-NEXT: $x0 = COPY [[ADDXrr]] 185 %0(s64) = COPY $x0 186 %1(s64) = G_CONSTANT i64 -5000 187 %2(s64) = G_ADD %0, %1 188 $x0 = COPY %2(s64) 189... 190 191--- 192name: add_neg_invalid_immed_s64 193legalized: true 194regBankSelected: true 195 196registers: 197 - { id: 0, class: gpr } 198 - { id: 1, class: gpr } 199 - { id: 2, class: gpr } 200 201body: | 202 bb.0: 203 liveins: $x0, $x1 204 ; We can't select this if the value is out of range. 205 ; CHECK-LABEL: name: add_neg_invalid_immed_s64 206 ; CHECK: liveins: $x0, $x1 207 ; CHECK-NEXT: {{ $}} 208 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 209 ; CHECK-NEXT: [[MOVi64imm:%[0-9]+]]:gpr64 = MOVi64imm -5000 210 ; CHECK-NEXT: [[ADDXrr:%[0-9]+]]:gpr64 = ADDXrr [[COPY]], [[MOVi64imm]] 211 ; CHECK-NEXT: $x0 = COPY [[ADDXrr]] 212 %0(s64) = COPY $x0 213 %1(s64) = G_CONSTANT i64 -5000 214 %2(s64) = G_ADD %0, %1 215 $x0 = COPY %2(s64) 216... 217 218--- 219name: add_imm_0_s32 220legalized: true 221regBankSelected: true 222 223registers: 224 - { id: 0, class: gpr } 225 - { id: 1, class: gpr } 226 - { id: 2, class: gpr } 227 228body: | 229 bb.0: 230 liveins: $x0, $x1 231 ; We shouldn't get a SUB here, because "cmp wN, $0" and "cmp wN, #0" have 232 ; opposite effects on the C flag. 233 ; CHECK-LABEL: name: add_imm_0_s32 234 ; CHECK: liveins: $x0, $x1 235 ; CHECK-NEXT: {{ $}} 236 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 237 ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 0, 0 238 ; CHECK-NEXT: $x0 = COPY [[ADDXri]] 239 %0(s64) = COPY $x0 240 %1(s64) = G_CONSTANT i64 0 241 %2(s64) = G_ADD %0, %1 242 $x0 = COPY %2(s64) 243... 244 245--- 246name: add_imm_0_s64 247legalized: true 248regBankSelected: true 249 250registers: 251 - { id: 0, class: gpr } 252 - { id: 1, class: gpr } 253 - { id: 2, class: gpr } 254 255body: | 256 bb.0: 257 liveins: $x0, $x1 258 ; We shouldn't get a SUB here, because "cmp xN, $0" and "cmp xN, #0" have 259 ; opposite effects on the C flag. 260 ; CHECK-LABEL: name: add_imm_0_s64 261 ; CHECK: liveins: $x0, $x1 262 ; CHECK-NEXT: {{ $}} 263 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 264 ; CHECK-NEXT: [[ADDXri:%[0-9]+]]:gpr64sp = ADDXri [[COPY]], 0, 0 265 ; CHECK-NEXT: $x0 = COPY [[ADDXri]] 266 %0(s64) = COPY $x0 267 %1(s64) = G_CONSTANT i64 0 268 %2(s64) = G_ADD %0, %1 269 $x0 = COPY %2(s64) 270... 271 272--- 273name: add_imm_s32_gpr_bb 274legalized: true 275regBankSelected: true 276 277registers: 278 - { id: 0, class: gpr } 279 - { id: 1, class: gpr } 280 - { id: 2, class: gpr } 281 282body: | 283 ; CHECK-LABEL: name: add_imm_s32_gpr_bb 284 ; CHECK: bb.0: 285 ; CHECK-NEXT: successors: %bb.1(0x80000000) 286 ; CHECK-NEXT: liveins: $w0, $w1 287 ; CHECK-NEXT: {{ $}} 288 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32sp = COPY $w0 289 ; CHECK-NEXT: B %bb.1 290 ; CHECK-NEXT: {{ $}} 291 ; CHECK-NEXT: bb.1: 292 ; CHECK-NEXT: [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[COPY]], 1, 0 293 ; CHECK-NEXT: $w0 = COPY [[ADDWri]] 294 bb.0: 295 liveins: $w0, $w1 296 successors: %bb.1 297 298 %0(s32) = COPY $w0 299 %1(s32) = G_CONSTANT i32 1 300 G_BR %bb.1 301 302 bb.1: 303 %2(s32) = G_ADD %0, %1 304 $w0 = COPY %2(s32) 305... 306 307--- 308# Same as add_s32_gpr, for G_SUB operations. 309name: sub_s32_gpr 310legalized: true 311regBankSelected: true 312 313registers: 314 - { id: 0, class: gpr } 315 - { id: 1, class: gpr } 316 - { id: 2, class: gpr } 317 318body: | 319 bb.0: 320 liveins: $w0, $w1 321 322 ; CHECK-LABEL: name: sub_s32_gpr 323 ; CHECK: liveins: $w0, $w1 324 ; CHECK-NEXT: {{ $}} 325 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 326 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 327 ; CHECK-NEXT: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[COPY1]], implicit-def dead $nzcv 328 ; CHECK-NEXT: $w0 = COPY [[SUBSWrr]] 329 %0(s32) = COPY $w0 330 %1(s32) = COPY $w1 331 %2(s32) = G_SUB %0, %1 332 $w0 = COPY %2(s32) 333... 334 335--- 336# Same as add_s64_gpr, for G_SUB operations. 337name: sub_s64_gpr 338legalized: true 339regBankSelected: true 340 341registers: 342 - { id: 0, class: gpr } 343 - { id: 1, class: gpr } 344 - { id: 2, class: gpr } 345 346body: | 347 bb.0: 348 liveins: $x0, $x1 349 350 ; CHECK-LABEL: name: sub_s64_gpr 351 ; CHECK: liveins: $x0, $x1 352 ; CHECK-NEXT: {{ $}} 353 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 354 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 355 ; CHECK-NEXT: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def dead $nzcv 356 ; CHECK-NEXT: $x0 = COPY [[SUBSXrr]] 357 %0(s64) = COPY $x0 358 %1(s64) = COPY $x1 359 %2(s64) = G_SUB %0, %1 360 $x0 = COPY %2(s64) 361... 362 363--- 364# Same as add_s32_gpr, for G_OR operations. 365name: or_s32_gpr 366legalized: true 367regBankSelected: true 368 369registers: 370 - { id: 0, class: gpr } 371 - { id: 1, class: gpr } 372 - { id: 2, class: gpr } 373 374body: | 375 bb.0: 376 liveins: $w0, $w1 377 378 ; CHECK-LABEL: name: or_s32_gpr 379 ; CHECK: liveins: $w0, $w1 380 ; CHECK-NEXT: {{ $}} 381 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 382 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 383 ; CHECK-NEXT: [[ORRWrr:%[0-9]+]]:gpr32 = ORRWrr [[COPY]], [[COPY1]] 384 ; CHECK-NEXT: $w0 = COPY [[ORRWrr]] 385 %0(s32) = COPY $w0 386 %1(s32) = COPY $w1 387 %2(s32) = G_OR %0, %1 388 $w0 = COPY %2(s32) 389... 390 391--- 392# Same as add_s64_gpr, for G_OR operations. 393name: or_s64_gpr 394legalized: true 395regBankSelected: true 396 397registers: 398 - { id: 0, class: gpr } 399 - { id: 1, class: gpr } 400 - { id: 2, class: gpr } 401 402body: | 403 bb.0: 404 liveins: $x0, $x1 405 406 ; CHECK-LABEL: name: or_s64_gpr 407 ; CHECK: liveins: $x0, $x1 408 ; CHECK-NEXT: {{ $}} 409 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 410 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 411 ; CHECK-NEXT: [[ORRXrr:%[0-9]+]]:gpr64 = ORRXrr [[COPY]], [[COPY1]] 412 ; CHECK-NEXT: $x0 = COPY [[ORRXrr]] 413 %0(s64) = COPY $x0 414 %1(s64) = COPY $x1 415 %2(s64) = G_OR %0, %1 416 $x0 = COPY %2(s64) 417... 418 419--- 420# 64-bit G_OR on vector registers. 421name: or_v2s32_fpr 422legalized: true 423regBankSelected: true 424# 425registers: 426 - { id: 0, class: fpr } 427 - { id: 1, class: fpr } 428 - { id: 2, class: fpr } 429 430# The actual OR does not matter as long as it is operating 431# on 64-bit width vector. 432body: | 433 bb.0: 434 liveins: $d0, $d1 435 436 ; CHECK-LABEL: name: or_v2s32_fpr 437 ; CHECK: liveins: $d0, $d1 438 ; CHECK-NEXT: {{ $}} 439 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 440 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 441 ; CHECK-NEXT: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]] 442 ; CHECK-NEXT: $d0 = COPY [[ORRv8i8_]] 443 %0(<2 x s32>) = COPY $d0 444 %1(<2 x s32>) = COPY $d1 445 %2(<2 x s32>) = G_OR %0, %1 446 $d0 = COPY %2(<2 x s32>) 447... 448 449--- 450# Same as add_s32_gpr, for G_AND operations. 451name: and_s32_gpr 452legalized: true 453regBankSelected: true 454 455registers: 456 - { id: 0, class: gpr } 457 - { id: 1, class: gpr } 458 - { id: 2, class: gpr } 459 460body: | 461 bb.0: 462 liveins: $w0, $w1 463 464 ; CHECK-LABEL: name: and_s32_gpr 465 ; CHECK: liveins: $w0, $w1 466 ; CHECK-NEXT: {{ $}} 467 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 468 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 469 ; CHECK-NEXT: [[ANDWrr:%[0-9]+]]:gpr32 = ANDWrr [[COPY]], [[COPY1]] 470 ; CHECK-NEXT: $w0 = COPY [[ANDWrr]] 471 %0(s32) = COPY $w0 472 %1(s32) = COPY $w1 473 %2(s32) = G_AND %0, %1 474 $w0 = COPY %2(s32) 475... 476 477--- 478# Same as add_s64_gpr, for G_AND operations. 479name: and_s64_gpr 480legalized: true 481regBankSelected: true 482 483registers: 484 - { id: 0, class: gpr } 485 - { id: 1, class: gpr } 486 - { id: 2, class: gpr } 487 488body: | 489 bb.0: 490 liveins: $x0, $x1 491 492 ; CHECK-LABEL: name: and_s64_gpr 493 ; CHECK: liveins: $x0, $x1 494 ; CHECK-NEXT: {{ $}} 495 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 496 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 497 ; CHECK-NEXT: [[ANDXrr:%[0-9]+]]:gpr64 = ANDXrr [[COPY]], [[COPY1]] 498 ; CHECK-NEXT: $x0 = COPY [[ANDXrr]] 499 %0(s64) = COPY $x0 500 %1(s64) = COPY $x1 501 %2(s64) = G_AND %0, %1 502 $x0 = COPY %2(s64) 503... 504 505--- 506# Same as add_s32_gpr, for G_SHL operations. 507name: shl_s32_gpr 508legalized: true 509regBankSelected: true 510 511registers: 512 - { id: 0, class: gpr } 513 - { id: 1, class: gpr } 514 - { id: 2, class: gpr } 515 516body: | 517 bb.0: 518 liveins: $w0, $w1 519 520 ; CHECK-LABEL: name: shl_s32_gpr 521 ; CHECK: liveins: $w0, $w1 522 ; CHECK-NEXT: {{ $}} 523 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 524 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 525 ; CHECK-NEXT: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY1]] 526 ; CHECK-NEXT: $w0 = COPY [[LSLVWr]] 527 %0(s32) = COPY $w0 528 %1(s32) = COPY $w1 529 %2(s32) = G_SHL %0, %1 530 $w0 = COPY %2(s32) 531... 532 533--- 534name: shl_s32_64_gpr 535legalized: true 536regBankSelected: true 537 538registers: 539 - { id: 0, class: gpr } 540 - { id: 1, class: gpr } 541 - { id: 2, class: gpr } 542 543body: | 544 bb.0: 545 liveins: $w0, $x1 546 547 ; CHECK-LABEL: name: shl_s32_64_gpr 548 ; CHECK: liveins: $w0, $x1 549 ; CHECK-NEXT: {{ $}} 550 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 551 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64all = COPY $x1 552 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]].sub_32 553 ; CHECK-NEXT: [[LSLVWr:%[0-9]+]]:gpr32 = LSLVWr [[COPY]], [[COPY2]] 554 ; CHECK-NEXT: $w0 = COPY [[LSLVWr]] 555 %0(s32) = COPY $w0 556 %1(s64) = COPY $x1 557 %2(s32) = G_SHL %0, %1 558 $w0 = COPY %2(s32) 559... 560 561--- 562# Same as add_s64_gpr, for G_SHL operations. 563name: shl_s64_gpr 564legalized: true 565regBankSelected: true 566 567registers: 568 - { id: 0, class: gpr } 569 - { id: 1, class: gpr } 570 - { id: 2, class: gpr } 571 572body: | 573 bb.0: 574 liveins: $x0, $x1 575 576 ; CHECK-LABEL: name: shl_s64_gpr 577 ; CHECK: liveins: $x0, $x1 578 ; CHECK-NEXT: {{ $}} 579 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 580 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 581 ; CHECK-NEXT: [[LSLVXr:%[0-9]+]]:gpr64 = LSLVXr [[COPY]], [[COPY1]] 582 ; CHECK-NEXT: $x0 = COPY [[LSLVXr]] 583 %0(s64) = COPY $x0 584 %1(s64) = COPY $x1 585 %2(s64) = G_SHL %0, %1 586 $x0 = COPY %2(s64) 587... 588 589--- 590# Same as add_s32_gpr, for G_LSHR operations. 591name: lshr_s32_gpr 592legalized: true 593regBankSelected: true 594 595registers: 596 - { id: 0, class: gpr } 597 - { id: 1, class: gpr } 598 - { id: 2, class: gpr } 599 600body: | 601 bb.0: 602 liveins: $w0, $w1 603 604 ; CHECK-LABEL: name: lshr_s32_gpr 605 ; CHECK: liveins: $w0, $w1 606 ; CHECK-NEXT: {{ $}} 607 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 608 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 609 ; CHECK-NEXT: [[LSRVWr:%[0-9]+]]:gpr32 = LSRVWr [[COPY]], [[COPY1]] 610 ; CHECK-NEXT: $w0 = COPY [[LSRVWr]] 611 %0(s32) = COPY $w0 612 %1(s32) = COPY $w1 613 %2(s32) = G_LSHR %0, %1 614 $w0 = COPY %2(s32) 615... 616 617--- 618# Same as add_s64_gpr, for G_LSHR operations. 619name: lshr_s64_gpr 620legalized: true 621regBankSelected: true 622 623registers: 624 - { id: 0, class: gpr } 625 - { id: 1, class: gpr } 626 - { id: 2, class: gpr } 627 628body: | 629 bb.0: 630 liveins: $x0, $x1 631 632 ; CHECK-LABEL: name: lshr_s64_gpr 633 ; CHECK: liveins: $x0, $x1 634 ; CHECK-NEXT: {{ $}} 635 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 636 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 637 ; CHECK-NEXT: [[LSRVXr:%[0-9]+]]:gpr64 = LSRVXr [[COPY]], [[COPY1]] 638 ; CHECK-NEXT: $x0 = COPY [[LSRVXr]] 639 %0(s64) = COPY $x0 640 %1(s64) = COPY $x1 641 %2(s64) = G_LSHR %0, %1 642 $x0 = COPY %2(s64) 643... 644 645--- 646# Same as add_s32_gpr, for G_ASHR operations. 647name: ashr_s32_gpr 648legalized: true 649regBankSelected: true 650 651registers: 652 - { id: 0, class: gpr } 653 - { id: 1, class: gpr } 654 - { id: 2, class: gpr } 655 656body: | 657 bb.0: 658 liveins: $w0, $w1 659 660 ; CHECK-LABEL: name: ashr_s32_gpr 661 ; CHECK: liveins: $w0, $w1 662 ; CHECK-NEXT: {{ $}} 663 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 664 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 665 ; CHECK-NEXT: [[ASRVWr:%[0-9]+]]:gpr32 = ASRVWr [[COPY]], [[COPY1]] 666 ; CHECK-NEXT: $w0 = COPY [[ASRVWr]] 667 %0(s32) = COPY $w0 668 %1(s32) = COPY $w1 669 %2(s32) = G_ASHR %0, %1 670 $w0 = COPY %2(s32) 671... 672 673--- 674# Same as add_s64_gpr, for G_ASHR operations. 675name: ashr_s64_gpr 676legalized: true 677regBankSelected: true 678 679registers: 680 - { id: 0, class: gpr } 681 - { id: 1, class: gpr } 682 - { id: 2, class: gpr } 683 684body: | 685 bb.0: 686 liveins: $x0, $x1 687 688 ; CHECK-LABEL: name: ashr_s64_gpr 689 ; CHECK: liveins: $x0, $x1 690 ; CHECK-NEXT: {{ $}} 691 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 692 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 693 ; CHECK-NEXT: [[ASRVXr:%[0-9]+]]:gpr64 = ASRVXr [[COPY]], [[COPY1]] 694 ; CHECK-NEXT: $x0 = COPY [[ASRVXr]] 695 %0(s64) = COPY $x0 696 %1(s64) = COPY $x1 697 %2(s64) = G_ASHR %0, %1 698 $x0 = COPY %2(s64) 699... 700 701--- 702# Check that we select s32 GPR G_MUL. This is trickier than other binops because 703# there is only MADDWrrr, and we have to use the WZR physreg. 704name: mul_s32_gpr 705legalized: true 706regBankSelected: true 707 708registers: 709 - { id: 0, class: gpr } 710 - { id: 1, class: gpr } 711 - { id: 2, class: gpr } 712 713body: | 714 bb.0: 715 liveins: $w0, $w1 716 717 ; CHECK-LABEL: name: mul_s32_gpr 718 ; CHECK: liveins: $w0, $w1 719 ; CHECK-NEXT: {{ $}} 720 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 721 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 722 ; CHECK-NEXT: [[MADDWrrr:%[0-9]+]]:gpr32 = MADDWrrr [[COPY]], [[COPY1]], $wzr 723 ; CHECK-NEXT: $w0 = COPY [[MADDWrrr]] 724 %0(s32) = COPY $w0 725 %1(s32) = COPY $w1 726 %2(s32) = G_MUL %0, %1 727 $w0 = COPY %2(s32) 728... 729 730--- 731# Same as mul_s32_gpr for the s64 type. 732name: mul_s64_gpr 733legalized: true 734regBankSelected: true 735 736registers: 737 - { id: 0, class: gpr } 738 - { id: 1, class: gpr } 739 - { id: 2, class: gpr } 740 741body: | 742 bb.0: 743 liveins: $x0, $x1 744 745 ; CHECK-LABEL: name: mul_s64_gpr 746 ; CHECK: liveins: $x0, $x1 747 ; CHECK-NEXT: {{ $}} 748 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 749 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 750 ; CHECK-NEXT: [[MADDXrrr:%[0-9]+]]:gpr64 = MADDXrrr [[COPY]], [[COPY1]], $xzr 751 ; CHECK-NEXT: $x0 = COPY [[MADDXrrr]] 752 %0(s64) = COPY $x0 753 %1(s64) = COPY $x1 754 %2(s64) = G_MUL %0, %1 755 $x0 = COPY %2(s64) 756... 757 758--- 759# Same as mul_s32_gpr for the s64 type. 760name: mulh_s64_gpr 761legalized: true 762regBankSelected: true 763 764 765body: | 766 bb.0: 767 liveins: $x0, $x1 768 769 ; CHECK-LABEL: name: mulh_s64_gpr 770 ; CHECK: liveins: $x0, $x1 771 ; CHECK-NEXT: {{ $}} 772 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 773 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 774 ; CHECK-NEXT: [[SMULHrr:%[0-9]+]]:gpr64 = SMULHrr [[COPY]], [[COPY1]] 775 ; CHECK-NEXT: [[UMULHrr:%[0-9]+]]:gpr64 = UMULHrr [[COPY]], [[COPY1]] 776 ; CHECK-NEXT: $x0 = COPY [[SMULHrr]] 777 ; CHECK-NEXT: $x0 = COPY [[UMULHrr]] 778 %0:gpr(s64) = COPY $x0 779 %1:gpr(s64) = COPY $x1 780 %2:gpr(s64) = G_SMULH %0, %1 781 %3:gpr(s64) = G_UMULH %0, %1 782 $x0 = COPY %2(s64) 783 $x0 = COPY %3(s64) 784... 785 786--- 787# Same as add_s32_gpr, for G_SDIV operations. 788name: sdiv_s32_gpr 789legalized: true 790regBankSelected: true 791 792registers: 793 - { id: 0, class: gpr } 794 - { id: 1, class: gpr } 795 - { id: 2, class: gpr } 796 797body: | 798 bb.0: 799 liveins: $w0, $w1 800 801 ; CHECK-LABEL: name: sdiv_s32_gpr 802 ; CHECK: liveins: $w0, $w1 803 ; CHECK-NEXT: {{ $}} 804 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 805 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 806 ; CHECK-NEXT: [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[COPY]], [[COPY1]] 807 ; CHECK-NEXT: $w0 = COPY [[SDIVWr]] 808 %0(s32) = COPY $w0 809 %1(s32) = COPY $w1 810 %2(s32) = G_SDIV %0, %1 811 $w0 = COPY %2(s32) 812... 813 814--- 815# Same as add_s64_gpr, for G_SDIV operations. 816name: sdiv_s64_gpr 817legalized: true 818regBankSelected: true 819 820registers: 821 - { id: 0, class: gpr } 822 - { id: 1, class: gpr } 823 - { id: 2, class: gpr } 824 825body: | 826 bb.0: 827 liveins: $x0, $x1 828 829 ; CHECK-LABEL: name: sdiv_s64_gpr 830 ; CHECK: liveins: $x0, $x1 831 ; CHECK-NEXT: {{ $}} 832 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 833 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 834 ; CHECK-NEXT: [[SDIVXr:%[0-9]+]]:gpr64 = SDIVXr [[COPY]], [[COPY1]] 835 ; CHECK-NEXT: $x0 = COPY [[SDIVXr]] 836 %0(s64) = COPY $x0 837 %1(s64) = COPY $x1 838 %2(s64) = G_SDIV %0, %1 839 $x0 = COPY %2(s64) 840... 841 842--- 843# Same as add_s32_gpr, for G_UDIV operations. 844name: udiv_s32_gpr 845legalized: true 846regBankSelected: true 847 848registers: 849 - { id: 0, class: gpr } 850 - { id: 1, class: gpr } 851 - { id: 2, class: gpr } 852 853body: | 854 bb.0: 855 liveins: $w0, $w1 856 857 ; CHECK-LABEL: name: udiv_s32_gpr 858 ; CHECK: liveins: $w0, $w1 859 ; CHECK-NEXT: {{ $}} 860 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 861 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 862 ; CHECK-NEXT: [[UDIVWr:%[0-9]+]]:gpr32 = UDIVWr [[COPY]], [[COPY1]] 863 ; CHECK-NEXT: $w0 = COPY [[UDIVWr]] 864 %0(s32) = COPY $w0 865 %1(s32) = COPY $w1 866 %2(s32) = G_UDIV %0, %1 867 $w0 = COPY %2(s32) 868... 869 870--- 871# Same as add_s64_gpr, for G_UDIV operations. 872name: udiv_s64_gpr 873legalized: true 874regBankSelected: true 875 876registers: 877 - { id: 0, class: gpr } 878 - { id: 1, class: gpr } 879 - { id: 2, class: gpr } 880 881body: | 882 bb.0: 883 liveins: $x0, $x1 884 885 ; CHECK-LABEL: name: udiv_s64_gpr 886 ; CHECK: liveins: $x0, $x1 887 ; CHECK-NEXT: {{ $}} 888 ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 889 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 890 ; CHECK-NEXT: [[UDIVXr:%[0-9]+]]:gpr64 = UDIVXr [[COPY]], [[COPY1]] 891 ; CHECK-NEXT: $x0 = COPY [[UDIVXr]] 892 %0(s64) = COPY $x0 893 %1(s64) = COPY $x1 894 %2(s64) = G_UDIV %0, %1 895 $x0 = COPY %2(s64) 896... 897 898--- 899# Check that we select a s32 FPR G_FADD into FADDSrr. 900name: fadd_s32_fpr 901legalized: true 902regBankSelected: true 903 904registers: 905 - { id: 0, class: fpr } 906 - { id: 1, class: fpr } 907 - { id: 2, class: fpr } 908 909body: | 910 bb.0: 911 liveins: $s0, $s1 912 913 ; CHECK-LABEL: name: fadd_s32_fpr 914 ; CHECK: liveins: $s0, $s1 915 ; CHECK-NEXT: {{ $}} 916 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 917 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 918 ; CHECK-NEXT: [[FADDSrr:%[0-9]+]]:fpr32 = nofpexcept FADDSrr [[COPY]], [[COPY1]], implicit $fpcr 919 ; CHECK-NEXT: $s0 = COPY [[FADDSrr]] 920 %0(s32) = COPY $s0 921 %1(s32) = COPY $s1 922 %2(s32) = G_FADD %0, %1 923 $s0 = COPY %2(s32) 924... 925 926--- 927name: fadd_s64_fpr 928legalized: true 929regBankSelected: true 930 931registers: 932 - { id: 0, class: fpr } 933 - { id: 1, class: fpr } 934 - { id: 2, class: fpr } 935 936body: | 937 bb.0: 938 liveins: $d0, $d1 939 940 ; CHECK-LABEL: name: fadd_s64_fpr 941 ; CHECK: liveins: $d0, $d1 942 ; CHECK-NEXT: {{ $}} 943 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 944 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 945 ; CHECK-NEXT: [[FADDDrr:%[0-9]+]]:fpr64 = nofpexcept FADDDrr [[COPY]], [[COPY1]], implicit $fpcr 946 ; CHECK-NEXT: $d0 = COPY [[FADDDrr]] 947 %0(s64) = COPY $d0 948 %1(s64) = COPY $d1 949 %2(s64) = G_FADD %0, %1 950 $d0 = COPY %2(s64) 951... 952 953--- 954name: fsub_s32_fpr 955legalized: true 956regBankSelected: true 957 958registers: 959 - { id: 0, class: fpr } 960 - { id: 1, class: fpr } 961 - { id: 2, class: fpr } 962 963body: | 964 bb.0: 965 liveins: $s0, $s1 966 967 ; CHECK-LABEL: name: fsub_s32_fpr 968 ; CHECK: liveins: $s0, $s1 969 ; CHECK-NEXT: {{ $}} 970 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 971 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 972 ; CHECK-NEXT: [[FSUBSrr:%[0-9]+]]:fpr32 = nofpexcept FSUBSrr [[COPY]], [[COPY1]], implicit $fpcr 973 ; CHECK-NEXT: $s0 = COPY [[FSUBSrr]] 974 %0(s32) = COPY $s0 975 %1(s32) = COPY $s1 976 %2(s32) = G_FSUB %0, %1 977 $s0 = COPY %2(s32) 978... 979 980--- 981name: fsub_s64_fpr 982legalized: true 983regBankSelected: true 984 985registers: 986 - { id: 0, class: fpr } 987 - { id: 1, class: fpr } 988 - { id: 2, class: fpr } 989 990body: | 991 bb.0: 992 liveins: $d0, $d1 993 994 ; CHECK-LABEL: name: fsub_s64_fpr 995 ; CHECK: liveins: $d0, $d1 996 ; CHECK-NEXT: {{ $}} 997 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 998 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 999 ; CHECK-NEXT: [[FSUBDrr:%[0-9]+]]:fpr64 = nofpexcept FSUBDrr [[COPY]], [[COPY1]], implicit $fpcr 1000 ; CHECK-NEXT: $d0 = COPY [[FSUBDrr]] 1001 %0(s64) = COPY $d0 1002 %1(s64) = COPY $d1 1003 %2(s64) = G_FSUB %0, %1 1004 $d0 = COPY %2(s64) 1005... 1006 1007--- 1008name: fmul_s32_fpr 1009legalized: true 1010regBankSelected: true 1011 1012registers: 1013 - { id: 0, class: fpr } 1014 - { id: 1, class: fpr } 1015 - { id: 2, class: fpr } 1016 1017body: | 1018 bb.0: 1019 liveins: $s0, $s1 1020 1021 ; CHECK-LABEL: name: fmul_s32_fpr 1022 ; CHECK: liveins: $s0, $s1 1023 ; CHECK-NEXT: {{ $}} 1024 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 1025 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 1026 ; CHECK-NEXT: [[FMULSrr:%[0-9]+]]:fpr32 = nofpexcept FMULSrr [[COPY]], [[COPY1]], implicit $fpcr 1027 ; CHECK-NEXT: $s0 = COPY [[FMULSrr]] 1028 %0(s32) = COPY $s0 1029 %1(s32) = COPY $s1 1030 %2(s32) = G_FMUL %0, %1 1031 $s0 = COPY %2(s32) 1032... 1033 1034--- 1035name: fmul_s64_fpr 1036legalized: true 1037regBankSelected: true 1038 1039registers: 1040 - { id: 0, class: fpr } 1041 - { id: 1, class: fpr } 1042 - { id: 2, class: fpr } 1043 1044body: | 1045 bb.0: 1046 liveins: $d0, $d1 1047 1048 ; CHECK-LABEL: name: fmul_s64_fpr 1049 ; CHECK: liveins: $d0, $d1 1050 ; CHECK-NEXT: {{ $}} 1051 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1052 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1053 ; CHECK-NEXT: [[FMULDrr:%[0-9]+]]:fpr64 = nofpexcept FMULDrr [[COPY]], [[COPY1]], implicit $fpcr 1054 ; CHECK-NEXT: $d0 = COPY [[FMULDrr]] 1055 %0(s64) = COPY $d0 1056 %1(s64) = COPY $d1 1057 %2(s64) = G_FMUL %0, %1 1058 $d0 = COPY %2(s64) 1059... 1060 1061--- 1062name: fdiv_s32_fpr 1063legalized: true 1064regBankSelected: true 1065 1066registers: 1067 - { id: 0, class: fpr } 1068 - { id: 1, class: fpr } 1069 - { id: 2, class: fpr } 1070 1071body: | 1072 bb.0: 1073 liveins: $s0, $s1 1074 1075 ; CHECK-LABEL: name: fdiv_s32_fpr 1076 ; CHECK: liveins: $s0, $s1 1077 ; CHECK-NEXT: {{ $}} 1078 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 1079 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 1080 ; CHECK-NEXT: [[FDIVSrr:%[0-9]+]]:fpr32 = nofpexcept FDIVSrr [[COPY]], [[COPY1]], implicit $fpcr 1081 ; CHECK-NEXT: $s0 = COPY [[FDIVSrr]] 1082 %0(s32) = COPY $s0 1083 %1(s32) = COPY $s1 1084 %2(s32) = G_FDIV %0, %1 1085 $s0 = COPY %2(s32) 1086... 1087 1088--- 1089name: fdiv_s64_fpr 1090legalized: true 1091regBankSelected: true 1092 1093registers: 1094 - { id: 0, class: fpr } 1095 - { id: 1, class: fpr } 1096 - { id: 2, class: fpr } 1097 1098body: | 1099 bb.0: 1100 liveins: $d0, $d1 1101 1102 ; CHECK-LABEL: name: fdiv_s64_fpr 1103 ; CHECK: liveins: $d0, $d1 1104 ; CHECK-NEXT: {{ $}} 1105 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1106 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1107 ; CHECK-NEXT: [[FDIVDrr:%[0-9]+]]:fpr64 = nofpexcept FDIVDrr [[COPY]], [[COPY1]], implicit $fpcr 1108 ; CHECK-NEXT: $d0 = COPY [[FDIVDrr]] 1109 %0(s64) = COPY $d0 1110 %1(s64) = COPY $d1 1111 %2(s64) = G_FDIV %0, %1 1112 $d0 = COPY %2(s64) 1113... 1114--- 1115name: add_v8i16 1116alignment: 4 1117legalized: true 1118regBankSelected: true 1119tracksRegLiveness: true 1120registers: 1121 - { id: 0, class: fpr } 1122 - { id: 1, class: fpr } 1123 - { id: 2, class: fpr } 1124machineFunctionInfo: {} 1125body: | 1126 bb.1: 1127 liveins: $q0, $q1 1128 1129 ; CHECK-LABEL: name: add_v8i16 1130 ; CHECK: liveins: $q0, $q1 1131 ; CHECK-NEXT: {{ $}} 1132 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1133 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1134 ; CHECK-NEXT: [[ADDv8i16_:%[0-9]+]]:fpr128 = ADDv8i16 [[COPY]], [[COPY1]] 1135 ; CHECK-NEXT: $q0 = COPY [[ADDv8i16_]] 1136 ; CHECK-NEXT: RET_ReallyLR implicit $q0 1137 %0:fpr(<8 x s16>) = COPY $q0 1138 %1:fpr(<8 x s16>) = COPY $q1 1139 %2:fpr(<8 x s16>) = G_ADD %0, %1 1140 $q0 = COPY %2(<8 x s16>) 1141 RET_ReallyLR implicit $q0 1142 1143... 1144--- 1145name: add_v16i8 1146alignment: 4 1147legalized: true 1148regBankSelected: true 1149tracksRegLiveness: true 1150registers: 1151 - { id: 0, class: fpr } 1152 - { id: 1, class: fpr } 1153 - { id: 2, class: fpr } 1154machineFunctionInfo: {} 1155body: | 1156 bb.1: 1157 liveins: $q0, $q1 1158 1159 ; CHECK-LABEL: name: add_v16i8 1160 ; CHECK: liveins: $q0, $q1 1161 ; CHECK-NEXT: {{ $}} 1162 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr128 = COPY $q0 1163 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 1164 ; CHECK-NEXT: [[ADDv16i8_:%[0-9]+]]:fpr128 = ADDv16i8 [[COPY]], [[COPY1]] 1165 ; CHECK-NEXT: $q0 = COPY [[ADDv16i8_]] 1166 ; CHECK-NEXT: RET_ReallyLR implicit $q0 1167 %0:fpr(<16 x s8>) = COPY $q0 1168 %1:fpr(<16 x s8>) = COPY $q1 1169 %2:fpr(<16 x s8>) = G_ADD %0, %1 1170 $q0 = COPY %2(<16 x s8>) 1171 RET_ReallyLR implicit $q0 1172 1173... 1174--- 1175name: add_v4i16 1176legalized: true 1177regBankSelected: true 1178tracksRegLiveness: true 1179body: | 1180 bb.1: 1181 liveins: $d0, $d1 1182 1183 ; CHECK-LABEL: name: add_v4i16 1184 ; CHECK: liveins: $d0, $d1 1185 ; CHECK-NEXT: {{ $}} 1186 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1187 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1188 ; CHECK-NEXT: [[ADDv4i16_:%[0-9]+]]:fpr64 = ADDv4i16 [[COPY]], [[COPY1]] 1189 ; CHECK-NEXT: $d0 = COPY [[ADDv4i16_]] 1190 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1191 %0:fpr(<4 x s16>) = COPY $d0 1192 %1:fpr(<4 x s16>) = COPY $d1 1193 %2:fpr(<4 x s16>) = G_ADD %0, %1 1194 $d0 = COPY %2(<4 x s16>) 1195 RET_ReallyLR implicit $d0 1196... 1197--- 1198name: or_v4i16 1199legalized: true 1200regBankSelected: true 1201tracksRegLiveness: true 1202body: | 1203 bb.1: 1204 liveins: $d0, $d1 1205 1206 ; CHECK-LABEL: name: or_v4i16 1207 ; CHECK: liveins: $d0, $d1 1208 ; CHECK-NEXT: {{ $}} 1209 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1210 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1211 ; CHECK-NEXT: [[ORRv8i8_:%[0-9]+]]:fpr64 = ORRv8i8 [[COPY]], [[COPY1]] 1212 ; CHECK-NEXT: $d0 = COPY [[ORRv8i8_]] 1213 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1214 %0:fpr(<4 x s16>) = COPY $d0 1215 %1:fpr(<4 x s16>) = COPY $d1 1216 %2:fpr(<4 x s16>) = G_OR %0, %1 1217 $d0 = COPY %2(<4 x s16>) 1218 RET_ReallyLR implicit $d0 1219... 1220--- 1221name: xor_v4i16 1222legalized: true 1223regBankSelected: true 1224tracksRegLiveness: true 1225body: | 1226 bb.1: 1227 liveins: $d0, $d1 1228 1229 ; CHECK-LABEL: name: xor_v4i16 1230 ; CHECK: liveins: $d0, $d1 1231 ; CHECK-NEXT: {{ $}} 1232 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1233 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1234 ; CHECK-NEXT: [[EORv8i8_:%[0-9]+]]:fpr64 = EORv8i8 [[COPY]], [[COPY1]] 1235 ; CHECK-NEXT: $d0 = COPY [[EORv8i8_]] 1236 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1237 %0:fpr(<4 x s16>) = COPY $d0 1238 %1:fpr(<4 x s16>) = COPY $d1 1239 %2:fpr(<4 x s16>) = G_XOR %0, %1 1240 $d0 = COPY %2(<4 x s16>) 1241 RET_ReallyLR implicit $d0 1242... 1243--- 1244name: mul_v4i16 1245legalized: true 1246regBankSelected: true 1247tracksRegLiveness: true 1248body: | 1249 bb.1: 1250 liveins: $d0, $d1 1251 1252 ; CHECK-LABEL: name: mul_v4i16 1253 ; CHECK: liveins: $d0, $d1 1254 ; CHECK-NEXT: {{ $}} 1255 ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 1256 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 1257 ; CHECK-NEXT: [[MULv4i16_:%[0-9]+]]:fpr64 = MULv4i16 [[COPY]], [[COPY1]] 1258 ; CHECK-NEXT: $d0 = COPY [[MULv4i16_]] 1259 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1260 %0:fpr(<4 x s16>) = COPY $d0 1261 %1:fpr(<4 x s16>) = COPY $d1 1262 %2:fpr(<4 x s16>) = G_MUL %0, %1 1263 $d0 = COPY %2(<4 x s16>) 1264 RET_ReallyLR implicit $d0 1265... 1266