1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-- -mattr=+lse -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s 3 4--- | 5 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" 6 7 define void @atomicrmw_xchg_i64(ptr %addr) { ret void } 8 define void @atomicrmw_add_i64(ptr %addr) { ret void } 9 define void @atomicrmw_add_i32(ptr %addr) { ret void } 10 define void @atomicrmw_sub_i32(ptr %addr) { ret void } 11 define void @atomicrmw_and_i32(ptr %addr) { ret void } 12 ; nand isn't legal 13 define void @atomicrmw_or_i32(ptr %addr) { ret void } 14 define void @atomicrmw_xor_i32(ptr %addr) { ret void } 15 define void @atomicrmw_min_i32(ptr %addr) { ret void } 16 define void @atomicrmw_max_i32(ptr %addr) { ret void } 17 define void @atomicrmw_umin_i32(ptr %addr) { ret void } 18 define void @atomicrmw_umax_i32(ptr %addr) { ret void } 19... 20 21--- 22name: atomicrmw_xchg_i64 23legalized: true 24regBankSelected: true 25 26body: | 27 bb.0: 28 liveins: $x0 29 30 ; CHECK-LABEL: name: atomicrmw_xchg_i64 31 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 32 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 33 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 34 ; CHECK: [[SWPX:%[0-9]+]]:gpr64 = SWPX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (s64) on %ir.addr) 35 ; CHECK: $x0 = COPY [[SWPX]] 36 %0:gpr(p0) = COPY $x0 37 %1:gpr(s64) = G_CONSTANT i64 1 38 %2:gpr(s64) = G_ATOMICRMW_XCHG %0, %1 :: (load store monotonic (s64) on %ir.addr) 39 $x0 = COPY %2(s64) 40... 41--- 42name: atomicrmw_add_i64 43legalized: true 44regBankSelected: true 45 46body: | 47 bb.0: 48 liveins: $x0 49 50 ; CHECK-LABEL: name: atomicrmw_add_i64 51 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 52 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 53 ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[MOVi32imm]], %subreg.sub_32 54 ; CHECK: [[LDADDX:%[0-9]+]]:gpr64 = LDADDX [[SUBREG_TO_REG]], [[COPY]] :: (load store monotonic (s64) on %ir.addr) 55 ; CHECK: $x0 = COPY [[LDADDX]] 56 %0:gpr(p0) = COPY $x0 57 %1:gpr(s64) = G_CONSTANT i64 1 58 %2:gpr(s64) = G_ATOMICRMW_ADD %0, %1 :: (load store monotonic (s64) on %ir.addr) 59 $x0 = COPY %2(s64) 60... 61--- 62name: atomicrmw_add_i32 63legalized: true 64regBankSelected: true 65 66body: | 67 bb.0: 68 liveins: $x0 69 70 ; CHECK-LABEL: name: atomicrmw_add_i32 71 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 72 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 73 ; CHECK: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[MOVi32imm]], [[COPY]] :: (load store seq_cst (s32) on %ir.addr) 74 ; CHECK: $w0 = COPY [[LDADDALW]] 75 %0:gpr(p0) = COPY $x0 76 %1:gpr(s32) = G_CONSTANT i32 1 77 %2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst (s32) on %ir.addr) 78 $w0 = COPY %2(s32) 79... 80 81--- 82name: atomicrmw_sub_i32 83legalized: true 84regBankSelected: true 85 86body: | 87 bb.0: 88 liveins: $x0 89 90 ; CHECK-LABEL: name: atomicrmw_sub_i32 91 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 92 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 93 ; CHECK: [[LDADDALW:%[0-9]+]]:gpr32 = LDADDALW [[MOVi32imm]], [[COPY]] :: (load store seq_cst (s32) on %ir.addr) 94 ; CHECK: $w0 = COPY [[LDADDALW]] 95 %0:gpr(p0) = COPY $x0 96 %1:gpr(s32) = G_CONSTANT i32 1 97 %2:gpr(s32) = G_ATOMICRMW_ADD %0, %1 :: (load store seq_cst (s32) on %ir.addr) 98 $w0 = COPY %2(s32) 99... 100 101--- 102name: atomicrmw_and_i32 103legalized: true 104regBankSelected: true 105 106body: | 107 bb.0: 108 liveins: $x0 109 110 ; CHECK-LABEL: name: atomicrmw_and_i32 111 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 112 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 113 ; CHECK: [[ORNWrr:%[0-9]+]]:gpr32 = ORNWrr $wzr, [[MOVi32imm]] 114 ; CHECK: [[LDCLRAW:%[0-9]+]]:gpr32 = LDCLRAW [[ORNWrr]], [[COPY]] :: (load store acquire (s32) on %ir.addr) 115 ; CHECK: $w0 = COPY [[LDCLRAW]] 116 %0:gpr(p0) = COPY $x0 117 %1:gpr(s32) = G_CONSTANT i32 1 118 %2:gpr(s32) = G_ATOMICRMW_AND %0, %1 :: (load store acquire (s32) on %ir.addr) 119 $w0 = COPY %2(s32) 120... 121 122--- 123name: atomicrmw_or_i32 124legalized: true 125regBankSelected: true 126 127body: | 128 bb.0: 129 liveins: $x0 130 131 ; CHECK-LABEL: name: atomicrmw_or_i32 132 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 133 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 134 ; CHECK: [[LDSETLW:%[0-9]+]]:gpr32 = LDSETLW [[MOVi32imm]], [[COPY]] :: (load store release (s32) on %ir.addr) 135 ; CHECK: $w0 = COPY [[LDSETLW]] 136 %0:gpr(p0) = COPY $x0 137 %1:gpr(s32) = G_CONSTANT i32 1 138 %2:gpr(s32) = G_ATOMICRMW_OR %0, %1 :: (load store release (s32) on %ir.addr) 139 $w0 = COPY %2(s32) 140... 141 142--- 143name: atomicrmw_xor_i32 144legalized: true 145regBankSelected: true 146 147body: | 148 bb.0: 149 liveins: $x0 150 151 ; CHECK-LABEL: name: atomicrmw_xor_i32 152 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 153 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 154 ; CHECK: [[LDEORALW:%[0-9]+]]:gpr32 = LDEORALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr) 155 ; CHECK: $w0 = COPY [[LDEORALW]] 156 %0:gpr(p0) = COPY $x0 157 %1:gpr(s32) = G_CONSTANT i32 1 158 %2:gpr(s32) = G_ATOMICRMW_XOR %0, %1 :: (load store acq_rel (s32) on %ir.addr) 159 $w0 = COPY %2(s32) 160... 161 162--- 163name: atomicrmw_min_i32 164legalized: true 165regBankSelected: true 166 167body: | 168 bb.0: 169 liveins: $x0 170 171 ; CHECK-LABEL: name: atomicrmw_min_i32 172 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 173 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 174 ; CHECK: [[LDSMINALW:%[0-9]+]]:gpr32 = LDSMINALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr) 175 ; CHECK: $w0 = COPY [[LDSMINALW]] 176 %0:gpr(p0) = COPY $x0 177 %1:gpr(s32) = G_CONSTANT i32 1 178 %2:gpr(s32) = G_ATOMICRMW_MIN %0, %1 :: (load store acq_rel (s32) on %ir.addr) 179 $w0 = COPY %2(s32) 180... 181 182--- 183name: atomicrmw_max_i32 184legalized: true 185regBankSelected: true 186 187body: | 188 bb.0: 189 liveins: $x0 190 191 ; CHECK-LABEL: name: atomicrmw_max_i32 192 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 193 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 194 ; CHECK: [[LDSMAXALW:%[0-9]+]]:gpr32 = LDSMAXALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr) 195 ; CHECK: $w0 = COPY [[LDSMAXALW]] 196 %0:gpr(p0) = COPY $x0 197 %1:gpr(s32) = G_CONSTANT i32 1 198 %2:gpr(s32) = G_ATOMICRMW_MAX %0, %1 :: (load store acq_rel (s32) on %ir.addr) 199 $w0 = COPY %2(s32) 200... 201 202--- 203name: atomicrmw_umin_i32 204legalized: true 205regBankSelected: true 206 207body: | 208 bb.0: 209 liveins: $x0 210 211 ; CHECK-LABEL: name: atomicrmw_umin_i32 212 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 213 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 214 ; CHECK: [[LDUMINALW:%[0-9]+]]:gpr32 = LDUMINALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr) 215 ; CHECK: $w0 = COPY [[LDUMINALW]] 216 %0:gpr(p0) = COPY $x0 217 %1:gpr(s32) = G_CONSTANT i32 1 218 %2:gpr(s32) = G_ATOMICRMW_UMIN %0, %1 :: (load store acq_rel (s32) on %ir.addr) 219 $w0 = COPY %2(s32) 220... 221 222--- 223name: atomicrmw_umax_i32 224legalized: true 225regBankSelected: true 226 227body: | 228 bb.0: 229 liveins: $x0 230 231 ; CHECK-LABEL: name: atomicrmw_umax_i32 232 ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0 233 ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1 234 ; CHECK: [[LDUMAXALW:%[0-9]+]]:gpr32 = LDUMAXALW [[MOVi32imm]], [[COPY]] :: (load store acq_rel (s32) on %ir.addr) 235 ; CHECK: $w0 = COPY [[LDUMAXALW]] 236 %0:gpr(p0) = COPY $x0 237 %1:gpr(s32) = G_CONSTANT i32 1 238 %2:gpr(s32) = G_ATOMICRMW_UMAX %0, %1 :: (load store acq_rel (s32) on %ir.addr) 239 $w0 = COPY %2(s32) 240... 241