xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-shifted-reg.mir (revision 490a867f16c064b774aeae9661dc699a65909ce2) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name:            add_shl_s64_rhs
6legalized:       true
7regBankSelected: true
8tracksRegLiveness: true
9body:             |
10  bb.0:
11    liveins: $x0
12    ; CHECK-LABEL: name: add_shl_s64_rhs
13    ; CHECK: liveins: $x0
14    ; CHECK-NEXT: {{  $}}
15    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
16    ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY]], [[COPY]], 8
17    ; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
18    ; CHECK-NEXT: RET_ReallyLR implicit $x0
19    %0:gpr(s64) = COPY $x0
20    %1:gpr(s64) = G_CONSTANT i64 8
21    %2:gpr(s64) = G_SHL %0, %1:gpr(s64)
22    %3:gpr(s64) = G_ADD %0, %2:gpr(s64)
23    $x0 = COPY %3:gpr(s64)
24    RET_ReallyLR implicit $x0
25
26...
27---
28name:            add_shl_s64_lhs
29legalized:       true
30regBankSelected: true
31tracksRegLiveness: true
32body:             |
33  bb.0:
34    liveins: $x0, $x1
35    ; CHECK-LABEL: name: add_shl_s64_lhs
36    ; CHECK: liveins: $x0, $x1
37    ; CHECK-NEXT: {{  $}}
38    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
39    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
40    ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY1]], [[COPY]], 8
41    ; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
42    ; CHECK-NEXT: RET_ReallyLR implicit $x0
43    %0:gpr(s64) = COPY $x0
44    %4:gpr(s64) = COPY $x1
45    %1:gpr(s64) = G_CONSTANT i64 8
46    %2:gpr(s64) = G_SHL %0, %1:gpr(s64)
47    %3:gpr(s64) = G_ADD %2, %4:gpr(s64)
48    $x0 = COPY %3:gpr(s64)
49    RET_ReallyLR implicit $x0
50
51...
52---
53name:            sub_shl_s64_rhs
54legalized:       true
55regBankSelected: true
56tracksRegLiveness: true
57body:             |
58  bb.0:
59    liveins: $x0
60    ; CHECK-LABEL: name: sub_shl_s64_rhs
61    ; CHECK: liveins: $x0
62    ; CHECK-NEXT: {{  $}}
63    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
64    ; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 8, implicit-def dead $nzcv
65    ; CHECK-NEXT: $x0 = COPY [[SUBSXrs]]
66    ; CHECK-NEXT: RET_ReallyLR implicit $x0
67    %0:gpr(s64) = COPY $x0
68    %1:gpr(s64) = G_CONSTANT i64 8
69    %2:gpr(s64) = G_SHL %0, %1:gpr(s64)
70    %3:gpr(s64) = G_SUB %0, %2:gpr(s64)
71    $x0 = COPY %3:gpr(s64)
72    RET_ReallyLR implicit $x0
73
74---
75name:            add_lshr_s64_rhs
76legalized:       true
77regBankSelected: true
78tracksRegLiveness: true
79body:             |
80  bb.0:
81    liveins: $x0
82    %0:gpr(s64) = COPY $x0
83    %1:gpr(s64) = G_CONSTANT i64 8
84    %2:gpr(s64) = G_LSHR %0, %1:gpr(s64)
85    %3:gpr(s64) = G_ADD %0, %2:gpr(s64)
86    $x0 = COPY %3:gpr(s64)
87    RET_ReallyLR implicit $x0
88
89...
90---
91name:            add_lshr_s64_lhs
92legalized:       true
93regBankSelected: true
94tracksRegLiveness: true
95body:             |
96  bb.0:
97    liveins: $x0, $x1
98    ; CHECK-LABEL: name: add_lshr_s64_lhs
99    ; CHECK: liveins: $x0, $x1
100    ; CHECK-NEXT: {{  $}}
101    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
102    ; CHECK-NEXT: %param2:gpr64 = COPY $x1
103    ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs %param2, [[COPY]], 72
104    ; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
105    ; CHECK-NEXT: RET_ReallyLR implicit $x0
106    %0:gpr(s64) = COPY $x0
107    %param2:gpr(s64) = COPY $x1
108    %1:gpr(s64) = G_CONSTANT i64 8
109    %2:gpr(s64) = G_LSHR %0, %1:gpr(s64)
110    %3:gpr(s64) = G_ADD %2, %param2:gpr(s64)
111    $x0 = COPY %3:gpr(s64)
112    RET_ReallyLR implicit $x0
113
114...
115---
116name:            sub_lshr_s64_rhs
117legalized:       true
118regBankSelected: true
119tracksRegLiveness: true
120body:             |
121  bb.0:
122    liveins: $x0
123    ; CHECK-LABEL: name: sub_lshr_s64_rhs
124    ; CHECK: liveins: $x0
125    ; CHECK-NEXT: {{  $}}
126    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
127    ; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 72, implicit-def dead $nzcv
128    ; CHECK-NEXT: $x0 = COPY [[SUBSXrs]]
129    ; CHECK-NEXT: RET_ReallyLR implicit $x0
130    %0:gpr(s64) = COPY $x0
131    %1:gpr(s64) = G_CONSTANT i64 8
132    %2:gpr(s64) = G_LSHR %0, %1:gpr(s64)
133    %3:gpr(s64) = G_SUB %0, %2:gpr(s64)
134    $x0 = COPY %3:gpr(s64)
135    RET_ReallyLR implicit $x0
136
137...
138---
139name:            add_ashr_s64_rhs
140legalized:       true
141regBankSelected: true
142tracksRegLiveness: true
143body:             |
144  bb.0:
145    liveins: $x0
146    ; CHECK-LABEL: name: add_ashr_s64_rhs
147    ; CHECK: liveins: $x0
148    ; CHECK-NEXT: {{  $}}
149    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
150    ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs [[COPY]], [[COPY]], 136
151    ; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
152    ; CHECK-NEXT: RET_ReallyLR implicit $x0
153    %0:gpr(s64) = COPY $x0
154    %1:gpr(s64) = G_CONSTANT i64 8
155    %2:gpr(s64) = G_ASHR %0, %1:gpr(s64)
156    %3:gpr(s64) = G_ADD %0, %2:gpr(s64)
157    $x0 = COPY %3:gpr(s64)
158    RET_ReallyLR implicit $x0
159
160...
161---
162name:            add_ashr_s64_lhs
163legalized:       true
164regBankSelected: true
165tracksRegLiveness: true
166body:             |
167  bb.0:
168    liveins: $x0, $x1
169    ; CHECK-LABEL: name: add_ashr_s64_lhs
170    ; CHECK: liveins: $x0, $x1
171    ; CHECK-NEXT: {{  $}}
172    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
173    ; CHECK-NEXT: %param2:gpr64 = COPY $x1
174    ; CHECK-NEXT: [[ADDXrs:%[0-9]+]]:gpr64 = ADDXrs %param2, [[COPY]], 136
175    ; CHECK-NEXT: $x0 = COPY [[ADDXrs]]
176    ; CHECK-NEXT: RET_ReallyLR implicit $x0
177    %0:gpr(s64) = COPY $x0
178    %param2:gpr(s64) = COPY $x1
179    %1:gpr(s64) = G_CONSTANT i64 8
180    %2:gpr(s64) = G_ASHR %0, %1:gpr(s64)
181    %3:gpr(s64) = G_ADD %2, %param2:gpr(s64)
182    $x0 = COPY %3:gpr(s64)
183    RET_ReallyLR implicit $x0
184
185...
186---
187name:            sub_ashr_s64_rhs
188legalized:       true
189regBankSelected: true
190tracksRegLiveness: true
191body:             |
192  bb.0:
193    liveins: $x0
194    ; CHECK-LABEL: name: sub_ashr_s64_rhs
195    ; CHECK: liveins: $x0
196    ; CHECK-NEXT: {{  $}}
197    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
198    ; CHECK-NEXT: [[SUBSXrs:%[0-9]+]]:gpr64 = SUBSXrs [[COPY]], [[COPY]], 136, implicit-def dead $nzcv
199    ; CHECK-NEXT: $x0 = COPY [[SUBSXrs]]
200    ; CHECK-NEXT: RET_ReallyLR implicit $x0
201    %0:gpr(s64) = COPY $x0
202    %1:gpr(s64) = G_CONSTANT i64 8
203    %2:gpr(s64) = G_ASHR %0, %1:gpr(s64)
204    %3:gpr(s64) = G_SUB %0, %2:gpr(s64)
205    $x0 = COPY %3:gpr(s64)
206    RET_ReallyLR implicit $x0
207
208---
209name:            add_shl_s32_rhs
210legalized:       true
211regBankSelected: true
212tracksRegLiveness: true
213body:             |
214  bb.0:
215    liveins: $w0
216    %0:gpr(s32) = COPY $w0
217    %1:gpr(s32) = G_CONSTANT i32 8
218    %2:gpr(s32) = G_SHL %0, %1:gpr(s32)
219    %3:gpr(s32) = G_ADD %0, %2:gpr(s32)
220    $w0 = COPY %3:gpr(s32)
221    RET_ReallyLR implicit $w0
222
223...
224---
225name:            add_shl_s32_lhs
226legalized:       true
227regBankSelected: true
228tracksRegLiveness: true
229body:             |
230  bb.0:
231    liveins: $w0, $w1
232    ; CHECK-LABEL: name: add_shl_s32_lhs
233    ; CHECK: liveins: $w0, $w1
234    ; CHECK-NEXT: {{  $}}
235    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
236    ; CHECK-NEXT: %param2:gpr32 = COPY $w1
237    ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 8
238    ; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
239    ; CHECK-NEXT: RET_ReallyLR implicit $w0
240    %0:gpr(s32) = COPY $w0
241    %param2:gpr(s32) = COPY $w1
242    %1:gpr(s32) = G_CONSTANT i32 8
243    %2:gpr(s32) = G_SHL %0, %1:gpr(s32)
244    %3:gpr(s32) = G_ADD %2, %param2:gpr(s32)
245    $w0 = COPY %3:gpr(s32)
246    RET_ReallyLR implicit $w0
247
248...
249---
250name:            sub_shl_s32_rhs
251legalized:       true
252regBankSelected: true
253tracksRegLiveness: true
254body:             |
255  bb.0:
256    liveins: $w0
257    ; CHECK-LABEL: name: sub_shl_s32_rhs
258    ; CHECK: liveins: $w0
259    ; CHECK-NEXT: {{  $}}
260    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
261    ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 8, implicit-def dead $nzcv
262    ; CHECK-NEXT: $w0 = COPY [[SUBSWrs]]
263    ; CHECK-NEXT: RET_ReallyLR implicit $w0
264    %0:gpr(s32) = COPY $w0
265    %1:gpr(s32) = G_CONSTANT i32 8
266    %2:gpr(s32) = G_SHL %0, %1:gpr(s32)
267    %3:gpr(s32) = G_SUB %0, %2:gpr(s32)
268    $w0 = COPY %3:gpr(s32)
269    RET_ReallyLR implicit $w0
270
271...
272---
273name:            add_lshr_s32_rhs
274legalized:       true
275regBankSelected: true
276tracksRegLiveness: true
277body:             |
278  bb.0:
279    liveins: $w0
280    ; CHECK-LABEL: name: add_lshr_s32_rhs
281    ; CHECK: liveins: $w0
282    ; CHECK-NEXT: {{  $}}
283    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
284    ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs [[COPY]], [[COPY]], 72
285    ; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
286    ; CHECK-NEXT: RET_ReallyLR implicit $w0
287    %0:gpr(s32) = COPY $w0
288    %1:gpr(s32) = G_CONSTANT i32 8
289    %2:gpr(s32) = G_LSHR %0, %1:gpr(s32)
290    %3:gpr(s32) = G_ADD %0, %2:gpr(s32)
291    $w0 = COPY %3:gpr(s32)
292    RET_ReallyLR implicit $w0
293
294...
295---
296name:            add_lshr_s32_lhs
297legalized:       true
298regBankSelected: true
299tracksRegLiveness: true
300body:             |
301  bb.0:
302    liveins: $w0, $w1
303    ; CHECK-LABEL: name: add_lshr_s32_lhs
304    ; CHECK: liveins: $w0, $w1
305    ; CHECK-NEXT: {{  $}}
306    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
307    ; CHECK-NEXT: %param2:gpr32 = COPY $w1
308    ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 72
309    ; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
310    ; CHECK-NEXT: RET_ReallyLR implicit $w0
311    %0:gpr(s32) = COPY $w0
312    %param2:gpr(s32) = COPY $w1
313    %1:gpr(s32) = G_CONSTANT i32 8
314    %2:gpr(s32) = G_LSHR %0, %1:gpr(s32)
315    %3:gpr(s32) = G_ADD %2, %param2:gpr(s32)
316    $w0 = COPY %3:gpr(s32)
317    RET_ReallyLR implicit $w0
318
319...
320---
321name:            sub_lshr_s32_rhs
322legalized:       true
323regBankSelected: true
324tracksRegLiveness: true
325body:             |
326  bb.0:
327    liveins: $w0
328    ; CHECK-LABEL: name: sub_lshr_s32_rhs
329    ; CHECK: liveins: $w0
330    ; CHECK-NEXT: {{  $}}
331    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
332    ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 72, implicit-def dead $nzcv
333    ; CHECK-NEXT: $w0 = COPY [[SUBSWrs]]
334    ; CHECK-NEXT: RET_ReallyLR implicit $w0
335    %0:gpr(s32) = COPY $w0
336    %1:gpr(s32) = G_CONSTANT i32 8
337    %2:gpr(s32) = G_LSHR %0, %1:gpr(s32)
338    %3:gpr(s32) = G_SUB %0, %2:gpr(s32)
339    $w0 = COPY %3:gpr(s32)
340    RET_ReallyLR implicit $w0
341
342...
343---
344name:            add_ashr_s32_rhs
345legalized:       true
346regBankSelected: true
347tracksRegLiveness: true
348body:             |
349  bb.0:
350    liveins: $w0
351    ; CHECK-LABEL: name: add_ashr_s32_rhs
352    ; CHECK: liveins: $w0
353    ; CHECK-NEXT: {{  $}}
354    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
355    ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs [[COPY]], [[COPY]], 136
356    ; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
357    ; CHECK-NEXT: RET_ReallyLR implicit $w0
358    %0:gpr(s32) = COPY $w0
359    %1:gpr(s32) = G_CONSTANT i32 8
360    %2:gpr(s32) = G_ASHR %0, %1:gpr(s32)
361    %3:gpr(s32) = G_ADD %0, %2:gpr(s32)
362    $w0 = COPY %3:gpr(s32)
363    RET_ReallyLR implicit $w0
364
365...
366---
367name:            add_ashr_s32_lhs
368legalized:       true
369regBankSelected: true
370tracksRegLiveness: true
371body:             |
372  bb.0:
373    liveins: $w0, $w1
374    ; CHECK-LABEL: name: add_ashr_s32_lhs
375    ; CHECK: liveins: $w0, $w1
376    ; CHECK-NEXT: {{  $}}
377    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
378    ; CHECK-NEXT: %param2:gpr32 = COPY $w1
379    ; CHECK-NEXT: [[ADDWrs:%[0-9]+]]:gpr32 = ADDWrs %param2, [[COPY]], 136
380    ; CHECK-NEXT: $w0 = COPY [[ADDWrs]]
381    ; CHECK-NEXT: RET_ReallyLR implicit $w0
382    %0:gpr(s32) = COPY $w0
383    %param2:gpr(s32) = COPY $w1
384    %1:gpr(s32) = G_CONSTANT i32 8
385    %2:gpr(s32) = G_ASHR %0, %1:gpr(s32)
386    %3:gpr(s32) = G_ADD %2, %param2:gpr(s32)
387    $w0 = COPY %3:gpr(s32)
388    RET_ReallyLR implicit $w0
389
390...
391---
392name:            sub_ashr_s32_rhs
393legalized:       true
394regBankSelected: true
395tracksRegLiveness: true
396body:             |
397  bb.0:
398    liveins: $w0
399    ; CHECK-LABEL: name: sub_ashr_s32_rhs
400    ; CHECK: liveins: $w0
401    ; CHECK-NEXT: {{  $}}
402    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
403    ; CHECK-NEXT: [[SUBSWrs:%[0-9]+]]:gpr32 = SUBSWrs [[COPY]], [[COPY]], 136, implicit-def dead $nzcv
404    ; CHECK-NEXT: $w0 = COPY [[SUBSWrs]]
405    ; CHECK-NEXT: RET_ReallyLR implicit $w0
406    %0:gpr(s32) = COPY $w0
407    %1:gpr(s32) = G_CONSTANT i32 8
408    %2:gpr(s32) = G_ASHR %0, %1:gpr(s32)
409    %3:gpr(s32) = G_SUB %0, %2:gpr(s32)
410    $w0 = COPY %3:gpr(s32)
411    RET_ReallyLR implicit $w0
412