xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/select-arith-extended-reg.mir (revision 490a867f16c064b774aeae9661dc699a65909ce2) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
3
4---
5name:            add_sext_s32_to_s64
6alignment:       4
7legalized:       true
8regBankSelected: true
9tracksRegLiveness: true
10machineFunctionInfo: {}
11body:             |
12  bb.0:
13    liveins: $w1, $x2
14    ; CHECK-LABEL: name: add_sext_s32_to_s64
15    ; CHECK: liveins: $w1, $x2
16    ; CHECK-NEXT: {{  $}}
17    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
18    ; CHECK-NEXT: %add_lhs:gpr64sp = COPY $x2
19    ; CHECK-NEXT: %res:gpr64sp = ADDXrx %add_lhs, [[COPY]], 48
20    ; CHECK-NEXT: $x3 = COPY %res
21    ; CHECK-NEXT: RET_ReallyLR implicit $x3
22    %1:gpr(s32) = COPY $w1
23    %ext:gpr(s64) = G_SEXT %1(s32)
24    %add_lhs:gpr(s64) = COPY $x2
25    %res:gpr(s64) = G_ADD %add_lhs, %ext
26    $x3 = COPY %res(s64)
27    RET_ReallyLR implicit $x3
28...
29---
30name:            add_and_s32_to_s64
31alignment:       4
32legalized:       true
33regBankSelected: true
34tracksRegLiveness: true
35machineFunctionInfo: {}
36body:             |
37  bb.0:
38    liveins: $x1, $x2
39    ; CHECK-LABEL: name: add_and_s32_to_s64
40    ; CHECK: liveins: $x1, $x2
41    ; CHECK-NEXT: {{  $}}
42    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64all = COPY $x1
43    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]].sub_32
44    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
45    ; CHECK-NEXT: %add_lhs:gpr64sp = COPY $x2
46    ; CHECK-NEXT: %res:gpr64sp = ADDXrx %add_lhs, [[COPY2]], 16
47    ; CHECK-NEXT: $x3 = COPY %res
48    ; CHECK-NEXT: RET_ReallyLR implicit $x3
49    %1:gpr(s64) = COPY $x1
50    %mask:gpr(s64) = G_CONSTANT i64 4294967295 ; 0xffff
51    %ext:gpr(s64) = G_AND %1(s64), %mask
52    %add_lhs:gpr(s64) = COPY $x2
53    %res:gpr(s64) = G_ADD %add_lhs, %ext
54    $x3 = COPY %res(s64)
55    RET_ReallyLR implicit $x3
56...
57---
58name:            add_sext_s16_to_s32
59alignment:       4
60legalized:       true
61regBankSelected: true
62tracksRegLiveness: true
63machineFunctionInfo: {}
64body:             |
65  bb.0:
66    liveins: $w1, $w2, $x2
67    ; CHECK-LABEL: name: add_sext_s16_to_s32
68    ; CHECK: liveins: $w1, $w2, $x2
69    ; CHECK-NEXT: {{  $}}
70    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
71    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
72    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 40
73    ; CHECK-NEXT: $w3 = COPY %res
74    ; CHECK-NEXT: RET_ReallyLR implicit $w3
75    %wide_1:gpr(s32) = COPY $w1
76    %1:gpr(s16) = G_TRUNC %wide_1
77    %ext:gpr(s32) = G_SEXT %1(s16)
78    %add_lhs:gpr(s32) = COPY $w2
79    %res:gpr(s32) = G_ADD %add_lhs, %ext
80    $w3 = COPY %res(s32)
81    RET_ReallyLR implicit $w3
82...
83---
84name:            add_zext_s16_to_s32
85alignment:       4
86legalized:       true
87regBankSelected: true
88tracksRegLiveness: true
89machineFunctionInfo: {}
90body:             |
91  bb.0:
92    liveins: $w1, $w2, $x2
93    ; CHECK-LABEL: name: add_zext_s16_to_s32
94    ; CHECK: liveins: $w1, $w2, $x2
95    ; CHECK-NEXT: {{  $}}
96    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
97    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
98    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 8
99    ; CHECK-NEXT: $w3 = COPY %res
100    ; CHECK-NEXT: RET_ReallyLR implicit $w3
101    %wide_1:gpr(s32) = COPY $w1
102    %1:gpr(s16) = G_TRUNC %wide_1
103    %ext:gpr(s32) = G_ZEXT %1(s16)
104    %add_lhs:gpr(s32) = COPY $w2
105    %res:gpr(s32) = G_ADD %add_lhs, %ext
106    $w3 = COPY %res(s32)
107    RET_ReallyLR implicit $w3
108...
109---
110name:            add_anyext_s16_to_s32
111alignment:       4
112legalized:       true
113regBankSelected: true
114tracksRegLiveness: true
115machineFunctionInfo: {}
116body:             |
117  bb.0:
118    liveins: $w1, $w2, $x2
119    ; CHECK-LABEL: name: add_anyext_s16_to_s32
120    ; CHECK: liveins: $w1, $w2, $x2
121    ; CHECK-NEXT: {{  $}}
122    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
123    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
124    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 8
125    ; CHECK-NEXT: $w3 = COPY %res
126    ; CHECK-NEXT: RET_ReallyLR implicit $w3
127    %wide_1:gpr(s32) = COPY $w1
128    %1:gpr(s16) = G_TRUNC %wide_1
129    %ext:gpr(s32) = G_ANYEXT %1(s16)
130    %add_lhs:gpr(s32) = COPY $w2
131    %res:gpr(s32) = G_ADD %add_lhs, %ext
132    $w3 = COPY %res(s32)
133    RET_ReallyLR implicit $w3
134...
135---
136name:            add_and_s16_to_s32_uxtb
137alignment:       4
138legalized:       true
139regBankSelected: true
140tracksRegLiveness: true
141machineFunctionInfo: {}
142body:             |
143  bb.0:
144    liveins: $w1, $w2, $x2
145    ; CHECK-LABEL: name: add_and_s16_to_s32_uxtb
146    ; CHECK: liveins: $w1, $w2, $x2
147    ; CHECK-NEXT: {{  $}}
148    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
149    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
150    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 0
151    ; CHECK-NEXT: $w3 = COPY %res
152    ; CHECK-NEXT: RET_ReallyLR implicit $w3
153    %1:gpr(s32) = COPY $w1
154    %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
155    %ext:gpr(s32) = G_AND %1(s32), %mask
156    %add_lhs:gpr(s32) = COPY $w2
157    %res:gpr(s32) = G_ADD %add_lhs, %ext
158    $w3 = COPY %res(s32)
159    RET_ReallyLR implicit $w3
160...
161---
162name:            add_and_s16_to_s32_uxth
163alignment:       4
164legalized:       true
165regBankSelected: true
166tracksRegLiveness: true
167machineFunctionInfo: {}
168body:             |
169  bb.0:
170    liveins: $w1, $w2, $x2
171    ; CHECK-LABEL: name: add_and_s16_to_s32_uxth
172    ; CHECK: liveins: $w1, $w2, $x2
173    ; CHECK-NEXT: {{  $}}
174    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
175    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
176    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 8
177    ; CHECK-NEXT: $w3 = COPY %res
178    ; CHECK-NEXT: RET_ReallyLR implicit $w3
179    %1:gpr(s32) = COPY $w1
180    %mask:gpr(s32) = G_CONSTANT i32 65535 ; 0xffff
181    %ext:gpr(s32) = G_AND %1(s32), %mask
182    %add_lhs:gpr(s32) = COPY $w2
183    %res:gpr(s32) = G_ADD %add_lhs, %ext
184    $w3 = COPY %res(s32)
185    RET_ReallyLR implicit $w3
186...
187---
188name:            add_sext_s8_to_s32
189alignment:       4
190legalized:       true
191regBankSelected: true
192tracksRegLiveness: true
193machineFunctionInfo: {}
194body:             |
195  bb.0:
196    liveins: $w1, $w2, $x2
197    ; CHECK-LABEL: name: add_sext_s8_to_s32
198    ; CHECK: liveins: $w1, $w2, $x2
199    ; CHECK-NEXT: {{  $}}
200    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
201    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
202    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 32
203    ; CHECK-NEXT: $w3 = COPY %res
204    ; CHECK-NEXT: RET_ReallyLR implicit $w3
205    %wide_1:gpr(s32) = COPY $w1
206    %1:gpr(s8) = G_TRUNC %wide_1
207    %ext:gpr(s32) = G_SEXT %1(s8)
208    %add_lhs:gpr(s32) = COPY $w2
209    %res:gpr(s32) = G_ADD %add_lhs, %ext
210    $w3 = COPY %res(s32)
211    RET_ReallyLR implicit $w3
212...
213---
214name:            add_zext_s8_to_s32
215alignment:       4
216legalized:       true
217regBankSelected: true
218tracksRegLiveness: true
219machineFunctionInfo: {}
220body:             |
221  bb.0:
222    liveins: $w1, $w2, $x2
223    ; CHECK-LABEL: name: add_zext_s8_to_s32
224    ; CHECK: liveins: $w1, $w2, $x2
225    ; CHECK-NEXT: {{  $}}
226    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
227    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
228    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0
229    ; CHECK-NEXT: $w3 = COPY %res
230    ; CHECK-NEXT: RET_ReallyLR implicit $w3
231    %wide_1:gpr(s32) = COPY $w1
232    %1:gpr(s8) = G_TRUNC %wide_1
233    %ext:gpr(s32) = G_ZEXT %1(s8)
234    %add_lhs:gpr(s32) = COPY $w2
235    %res:gpr(s32) = G_ADD %add_lhs, %ext
236    $w3 = COPY %res(s32)
237    RET_ReallyLR implicit $w3
238...
239---
240name:            add_anyext_s8_to_s32
241alignment:       4
242legalized:       true
243regBankSelected: true
244tracksRegLiveness: true
245machineFunctionInfo: {}
246body:             |
247  bb.0:
248    liveins: $w1, $w2, $x2
249    ; CHECK-LABEL: name: add_anyext_s8_to_s32
250    ; CHECK: liveins: $w1, $w2, $x2
251    ; CHECK-NEXT: {{  $}}
252    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
253    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
254    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 0
255    ; CHECK-NEXT: $w3 = COPY %res
256    ; CHECK-NEXT: RET_ReallyLR implicit $w3
257    %wide_1:gpr(s32) = COPY $w1
258    %1:gpr(s8) = G_TRUNC %wide_1
259    %ext:gpr(s32) = G_ANYEXT %1(s8)
260    %add_lhs:gpr(s32) = COPY $w2
261    %res:gpr(s32) = G_ADD %add_lhs, %ext
262    $w3 = COPY %res(s32)
263    RET_ReallyLR implicit $w3
264...
265---
266name:            add_sext_with_shl
267alignment:       4
268legalized:       true
269regBankSelected: true
270tracksRegLiveness: true
271machineFunctionInfo: {}
272body:             |
273  bb.0:
274    liveins: $w1, $w2, $x2
275    ; CHECK-LABEL: name: add_sext_with_shl
276    ; CHECK: liveins: $w1, $w2, $x2
277    ; CHECK-NEXT: {{  $}}
278    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
279    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
280    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, %wide_1, 43
281    ; CHECK-NEXT: $w3 = COPY %res
282    ; CHECK-NEXT: RET_ReallyLR implicit $w3
283    %wide_1:gpr(s32) = COPY $w1
284    %1:gpr(s16) = G_TRUNC %wide_1
285    %ext:gpr(s32) = G_SEXT %1(s16)
286    %imm:gpr(s32) = G_CONSTANT i32 3
287    %shl:gpr(s32) = G_SHL %ext, %imm
288    %add_lhs:gpr(s32) = COPY $w2
289    %res:gpr(s32) = G_ADD %add_lhs, %shl
290    $w3 = COPY %res(s32)
291    RET_ReallyLR implicit $w3
292...
293---
294name:            add_and_with_shl
295alignment:       4
296legalized:       true
297regBankSelected: true
298tracksRegLiveness: true
299machineFunctionInfo: {}
300body:             |
301  bb.0:
302    liveins: $w1, $w2, $x2
303    ; CHECK-LABEL: name: add_and_with_shl
304    ; CHECK: liveins: $w1, $w2, $x2
305    ; CHECK-NEXT: {{  $}}
306    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
307    ; CHECK-NEXT: %add_lhs:gpr32sp = COPY $w2
308    ; CHECK-NEXT: %res:gpr32sp = ADDWrx %add_lhs, [[COPY]], 3
309    ; CHECK-NEXT: $w3 = COPY %res
310    ; CHECK-NEXT: RET_ReallyLR implicit $w3
311    %1:gpr(s32) = COPY $w1
312    %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
313    %ext:gpr(s32) = G_AND %1(s32), %mask
314    %imm:gpr(s32) = G_CONSTANT i32 3
315    %shl:gpr(s32) = G_SHL %ext, %imm
316    %add_lhs:gpr(s32) = COPY $w2
317    %res:gpr(s32) = G_ADD %add_lhs, %shl
318    $w3 = COPY %res(s32)
319    RET_ReallyLR implicit $w3
320...
321---
322name:            dont_fold_invalid_mask
323alignment:       4
324legalized:       true
325regBankSelected: true
326tracksRegLiveness: true
327machineFunctionInfo: {}
328body:             |
329  bb.0:
330    ; Check that we only fold when we have a supported AND mask.
331    liveins: $w1, $w2, $x2
332    ; CHECK-LABEL: name: dont_fold_invalid_mask
333    ; CHECK: liveins: $w1, $w2, $x2
334    ; CHECK-NEXT: {{  $}}
335    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
336    ; CHECK-NEXT: %mask:gpr32 = MOVi32imm 42
337    ; CHECK-NEXT: %ext:gpr32 = ANDWrr [[COPY]], %mask
338    ; CHECK-NEXT: %add_lhs:gpr32 = COPY $w2
339    ; CHECK-NEXT: %res:gpr32 = ADDWrr %add_lhs, %ext
340    ; CHECK-NEXT: $w3 = COPY %res
341    ; CHECK-NEXT: RET_ReallyLR implicit $w3
342    %1:gpr(s32) = COPY $w1
343    %mask:gpr(s32) = G_CONSTANT i32 42
344    %ext:gpr(s32) = G_AND %1(s32), %mask
345    %add_lhs:gpr(s32) = COPY $w2
346    %res:gpr(s32) = G_ADD %add_lhs, %ext
347    $w3 = COPY %res(s32)
348    RET_ReallyLR implicit $w3
349...
350---
351name:            dont_fold_invalid_shl
352alignment:       4
353legalized:       true
354regBankSelected: true
355tracksRegLiveness: true
356machineFunctionInfo: {}
357body:             |
358  bb.0:
359    liveins: $w1, $w2, $x2
360    ; CHECK-LABEL: name: dont_fold_invalid_shl
361    ; CHECK: liveins: $w1, $w2, $x2
362    ; CHECK-NEXT: {{  $}}
363    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
364    ; CHECK-NEXT: %ext:gpr32 = SBFMWri %wide_1, 0, 15
365    ; CHECK-NEXT: %add_lhs:gpr32 = COPY $w2
366    ; CHECK-NEXT: %res:gpr32 = ADDWrs %add_lhs, %ext, 5
367    ; CHECK-NEXT: $w3 = COPY %res
368    ; CHECK-NEXT: RET_ReallyLR implicit $w3
369    %wide_1:gpr(s32) = COPY $w1
370    %1:gpr(s16) = G_TRUNC %wide_1
371    %ext:gpr(s32) = G_SEXT %1(s16)
372    %imm:gpr(s32) = G_CONSTANT i32 5
373    %shl:gpr(s32) = G_SHL %ext, %imm
374    %add_lhs:gpr(s32) = COPY $w2
375    %res:gpr(s32) = G_ADD %add_lhs, %shl
376    $w3 = COPY %res(s32)
377    RET_ReallyLR implicit $w3
378...
379---
380name:            sub_sext_s32_to_s64
381alignment:       4
382legalized:       true
383regBankSelected: true
384tracksRegLiveness: true
385machineFunctionInfo: {}
386body:             |
387  bb.0:
388    liveins: $w1, $x2
389    ; CHECK-LABEL: name: sub_sext_s32_to_s64
390    ; CHECK: liveins: $w1, $x2
391    ; CHECK-NEXT: {{  $}}
392    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
393    ; CHECK-NEXT: %sub_lhs:gpr64sp = COPY $x2
394    ; CHECK-NEXT: %res:gpr64 = SUBSXrx %sub_lhs, [[COPY]], 48, implicit-def dead $nzcv
395    ; CHECK-NEXT: $x3 = COPY %res
396    ; CHECK-NEXT: RET_ReallyLR implicit $x3
397    %1:gpr(s32) = COPY $w1
398    %ext:gpr(s64) = G_SEXT %1(s32)
399    %sub_lhs:gpr(s64) = COPY $x2
400    %res:gpr(s64) = G_SUB %sub_lhs, %ext
401    $x3 = COPY %res(s64)
402    RET_ReallyLR implicit $x3
403...
404---
405name:            sub_sext_s16_to_s32
406alignment:       4
407legalized:       true
408regBankSelected: true
409tracksRegLiveness: true
410machineFunctionInfo: {}
411body:             |
412  bb.0:
413    liveins: $w1, $w2, $x2
414    ; CHECK-LABEL: name: sub_sext_s16_to_s32
415    ; CHECK: liveins: $w1, $w2, $x2
416    ; CHECK-NEXT: {{  $}}
417    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
418    ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
419    ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 40, implicit-def dead $nzcv
420    ; CHECK-NEXT: $w3 = COPY %res
421    ; CHECK-NEXT: RET_ReallyLR implicit $w3
422    %wide_1:gpr(s32) = COPY $w1
423    %1:gpr(s16) = G_TRUNC %wide_1
424    %ext:gpr(s32) = G_SEXT %1(s16)
425    %sub_lhs:gpr(s32) = COPY $w2
426    %res:gpr(s32) = G_SUB %sub_lhs, %ext
427    $w3 = COPY %res(s32)
428    RET_ReallyLR implicit $w3
429...
430---
431name:            sub_zext_s16_to_s32
432alignment:       4
433legalized:       true
434regBankSelected: true
435tracksRegLiveness: true
436machineFunctionInfo: {}
437body:             |
438  bb.0:
439    liveins: $w1, $w2, $x2
440    ; CHECK-LABEL: name: sub_zext_s16_to_s32
441    ; CHECK: liveins: $w1, $w2, $x2
442    ; CHECK-NEXT: {{  $}}
443    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
444    ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
445    ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def dead $nzcv
446    ; CHECK-NEXT: $w3 = COPY %res
447    ; CHECK-NEXT: RET_ReallyLR implicit $w3
448    %wide_1:gpr(s32) = COPY $w1
449    %1:gpr(s16) = G_TRUNC %wide_1
450    %ext:gpr(s32) = G_ZEXT %1(s16)
451    %sub_lhs:gpr(s32) = COPY $w2
452    %res:gpr(s32) = G_SUB %sub_lhs, %ext
453    $w3 = COPY %res(s32)
454    RET_ReallyLR implicit $w3
455...
456---
457name:            sub_anyext_s16_to_s32
458alignment:       4
459legalized:       true
460regBankSelected: true
461tracksRegLiveness: true
462machineFunctionInfo: {}
463body:             |
464  bb.0:
465    liveins: $w1, $w2, $x2
466    ; CHECK-LABEL: name: sub_anyext_s16_to_s32
467    ; CHECK: liveins: $w1, $w2, $x2
468    ; CHECK-NEXT: {{  $}}
469    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
470    ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
471    ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 8, implicit-def dead $nzcv
472    ; CHECK-NEXT: $w3 = COPY %res
473    ; CHECK-NEXT: RET_ReallyLR implicit $w3
474    %wide_1:gpr(s32) = COPY $w1
475    %1:gpr(s16) = G_TRUNC %wide_1
476    %ext:gpr(s32) = G_ANYEXT %1(s16)
477    %sub_lhs:gpr(s32) = COPY $w2
478    %res:gpr(s32) = G_SUB %sub_lhs, %ext
479    $w3 = COPY %res(s32)
480    RET_ReallyLR implicit $w3
481...
482---
483name:            sub_and_s16_to_s32_uxtb
484alignment:       4
485legalized:       true
486regBankSelected: true
487tracksRegLiveness: true
488machineFunctionInfo: {}
489body:             |
490  bb.0:
491    liveins: $w1, $w2, $x2
492    ; CHECK-LABEL: name: sub_and_s16_to_s32_uxtb
493    ; CHECK: liveins: $w1, $w2, $x2
494    ; CHECK-NEXT: {{  $}}
495    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
496    ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
497    ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 0, implicit-def dead $nzcv
498    ; CHECK-NEXT: $w3 = COPY %res
499    ; CHECK-NEXT: RET_ReallyLR implicit $w3
500    %1:gpr(s32) = COPY $w1
501    %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
502    %ext:gpr(s32) = G_AND %1(s32), %mask
503    %sub_lhs:gpr(s32) = COPY $w2
504    %res:gpr(s32) = G_SUB %sub_lhs, %ext
505    $w3 = COPY %res(s32)
506    RET_ReallyLR implicit $w3
507...
508---
509name:            sub_and_s16_to_s32_uxth
510alignment:       4
511legalized:       true
512regBankSelected: true
513tracksRegLiveness: true
514machineFunctionInfo: {}
515body:             |
516  bb.0:
517    liveins: $w1, $w2, $x2
518    ; CHECK-LABEL: name: sub_and_s16_to_s32_uxth
519    ; CHECK: liveins: $w1, $w2, $x2
520    ; CHECK-NEXT: {{  $}}
521    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
522    ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
523    ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 8, implicit-def dead $nzcv
524    ; CHECK-NEXT: $w3 = COPY %res
525    ; CHECK-NEXT: RET_ReallyLR implicit $w3
526    %1:gpr(s32) = COPY $w1
527    %mask:gpr(s32) = G_CONSTANT i32 65535 ; 0xffff
528    %ext:gpr(s32) = G_AND %1(s32), %mask
529    %sub_lhs:gpr(s32) = COPY $w2
530    %res:gpr(s32) = G_SUB %sub_lhs, %ext
531    $w3 = COPY %res(s32)
532    RET_ReallyLR implicit $w3
533---
534name:            sub_sext_s8_to_s32
535alignment:       4
536legalized:       true
537regBankSelected: true
538tracksRegLiveness: true
539machineFunctionInfo: {}
540body:             |
541  bb.0:
542    liveins: $w1, $w2, $x2
543    %wide_1:gpr(s32) = COPY $w1
544    %1:gpr(s8) = G_TRUNC %wide_1
545    %ext:gpr(s32) = G_SEXT %1(s8)
546    %sub_lhs:gpr(s32) = COPY $w2
547    %res:gpr(s32) = G_SUB %sub_lhs, %ext
548    $w3 = COPY %res(s32)
549    RET_ReallyLR implicit $w3
550...
551---
552name:            sub_zext_s8_to_s32
553alignment:       4
554legalized:       true
555regBankSelected: true
556tracksRegLiveness: true
557machineFunctionInfo: {}
558body:             |
559  bb.0:
560    liveins: $w1, $w2, $x2
561    ; CHECK-LABEL: name: sub_zext_s8_to_s32
562    ; CHECK: liveins: $w1, $w2, $x2
563    ; CHECK-NEXT: {{  $}}
564    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
565    ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
566    ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def dead $nzcv
567    ; CHECK-NEXT: $w3 = COPY %res
568    ; CHECK-NEXT: RET_ReallyLR implicit $w3
569    %wide_1:gpr(s32) = COPY $w1
570    %1:gpr(s8) = G_TRUNC %wide_1
571    %ext:gpr(s32) = G_ZEXT %1(s8)
572    %sub_lhs:gpr(s32) = COPY $w2
573    %res:gpr(s32) = G_SUB %sub_lhs, %ext
574    $w3 = COPY %res(s32)
575    RET_ReallyLR implicit $w3
576...
577---
578name:            sub_anyext_s8_to_s32
579alignment:       4
580legalized:       true
581regBankSelected: true
582tracksRegLiveness: true
583machineFunctionInfo: {}
584body:             |
585  bb.0:
586    liveins: $w1, $w2, $x2
587    ; CHECK-LABEL: name: sub_anyext_s8_to_s32
588    ; CHECK: liveins: $w1, $w2, $x2
589    ; CHECK-NEXT: {{  $}}
590    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
591    ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
592    ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 0, implicit-def dead $nzcv
593    ; CHECK-NEXT: $w3 = COPY %res
594    ; CHECK-NEXT: RET_ReallyLR implicit $w3
595    %wide_1:gpr(s32) = COPY $w1
596    %1:gpr(s8) = G_TRUNC %wide_1
597    %ext:gpr(s32) = G_ANYEXT %1(s8)
598    %sub_lhs:gpr(s32) = COPY $w2
599    %res:gpr(s32) = G_SUB %sub_lhs, %ext
600    $w3 = COPY %res(s32)
601    RET_ReallyLR implicit $w3
602---
603...
604---
605name:            sub_sext_with_shl
606alignment:       4
607legalized:       true
608regBankSelected: true
609tracksRegLiveness: true
610machineFunctionInfo: {}
611body:             |
612  bb.0:
613    liveins: $w1, $w2, $x2
614    ; CHECK-LABEL: name: sub_sext_with_shl
615    ; CHECK: liveins: $w1, $w2, $x2
616    ; CHECK-NEXT: {{  $}}
617    ; CHECK-NEXT: %wide_1:gpr32 = COPY $w1
618    ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
619    ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, %wide_1, 43, implicit-def dead $nzcv
620    ; CHECK-NEXT: $w3 = COPY %res
621    ; CHECK-NEXT: RET_ReallyLR implicit $w3
622    %wide_1:gpr(s32) = COPY $w1
623    %1:gpr(s16) = G_TRUNC %wide_1
624    %ext:gpr(s32) = G_SEXT %1(s16)
625    %imm:gpr(s32) = G_CONSTANT i32 3
626    %shl:gpr(s32) = G_SHL %ext, %imm
627    %sub_lhs:gpr(s32) = COPY $w2
628    %res:gpr(s32) = G_SUB %sub_lhs, %shl
629    $w3 = COPY %res(s32)
630    RET_ReallyLR implicit $w3
631...
632---
633name:            sub_and_with_shl
634alignment:       4
635legalized:       true
636regBankSelected: true
637tracksRegLiveness: true
638machineFunctionInfo: {}
639body:             |
640  bb.0:
641    liveins: $w1, $w2, $x2
642    ; CHECK-LABEL: name: sub_and_with_shl
643    ; CHECK: liveins: $w1, $w2, $x2
644    ; CHECK-NEXT: {{  $}}
645    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
646    ; CHECK-NEXT: %sub_lhs:gpr32sp = COPY $w2
647    ; CHECK-NEXT: %res:gpr32 = SUBSWrx %sub_lhs, [[COPY]], 3, implicit-def dead $nzcv
648    ; CHECK-NEXT: $w3 = COPY %res
649    ; CHECK-NEXT: RET_ReallyLR implicit $w3
650    %1:gpr(s32) = COPY $w1
651    %mask:gpr(s32) = G_CONSTANT i32 255 ; 0xff
652    %ext:gpr(s32) = G_AND %1(s32), %mask
653    %imm:gpr(s32) = G_CONSTANT i32 3
654    %shl:gpr(s32) = G_SHL %ext, %imm
655    %sub_lhs:gpr(s32) = COPY $w2
656    %res:gpr(s32) = G_SUB %sub_lhs, %shl
657    $w3 = COPY %res(s32)
658    RET_ReallyLR implicit $w3
659...
660---
661name:            store_16b_zext
662alignment:       4
663legalized:       true
664regBankSelected: true
665tracksRegLiveness: true
666liveins:
667  - { reg: '$x0' }
668  - { reg: '$w1' }
669  - { reg: '$x2' }
670body:             |
671  bb.1.entry:
672    liveins: $x0, $x1, $x2
673
674    ; CHECK-LABEL: name: store_16b_zext
675    ; CHECK: liveins: $x0, $x1, $x2
676    ; CHECK-NEXT: {{  $}}
677    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
678    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
679    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
680    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32
681    ; CHECK-NEXT: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 15
682    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
683    ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
684    ; CHECK-NEXT: RET_ReallyLR
685    %0:gpr(p0) = COPY $x0
686    %1:gpr(s32) = COPY $w1
687    %2:gpr(p0) = COPY $x2
688    %small:gpr(s16) = G_TRUNC %1
689    %zext:gpr(s64) = G_ZEXT %small(s16)
690    %cst:gpr(s64) = G_CONSTANT i64 3
691    %shl:gpr(s64) = G_SHL %zext, %cst(s64)
692    %gep:gpr(p0) = G_PTR_ADD %0, %shl(s64)
693    G_STORE %2(p0), %gep(p0) :: (store (p0))
694    RET_ReallyLR
695...
696---
697name:            store_8b_zext
698alignment:       4
699legalized:       true
700regBankSelected: true
701tracksRegLiveness: true
702liveins:
703  - { reg: '$x0' }
704  - { reg: '$w1' }
705  - { reg: '$x2' }
706body:             |
707  bb.1.entry:
708    liveins: $x0, $x1, $x2
709
710    ; CHECK-LABEL: name: store_8b_zext
711    ; CHECK: liveins: $x0, $x1, $x2
712    ; CHECK-NEXT: {{  $}}
713    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
714    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
715    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
716    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32
717    ; CHECK-NEXT: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 7
718    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
719    ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
720    ; CHECK-NEXT: RET_ReallyLR
721    %0:gpr(p0) = COPY $x0
722    %1:gpr(s32) = COPY $w1
723    %2:gpr(p0) = COPY $x2
724    %small:gpr(s8) = G_TRUNC %1
725    %zext:gpr(s64) = G_ZEXT %small(s8)
726    %cst:gpr(s64) = G_CONSTANT i64 3
727    %shl:gpr(s64) = G_SHL %zext, %cst(s64)
728    %gep:gpr(p0) = G_PTR_ADD %0, %shl(s64)
729    G_STORE %2(p0), %gep(p0) :: (store (p0))
730    RET_ReallyLR
731...
732---
733name:            store_16b_sext
734alignment:       4
735legalized:       true
736regBankSelected: true
737tracksRegLiveness: true
738liveins:
739  - { reg: '$x0' }
740  - { reg: '$w1' }
741  - { reg: '$x2' }
742body:             |
743  bb.1.entry:
744    liveins: $x0, $x1, $x2
745
746    ; CHECK-LABEL: name: store_16b_sext
747    ; CHECK: liveins: $x0, $x1, $x2
748    ; CHECK-NEXT: {{  $}}
749    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
750    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
751    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
752    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32
753    ; CHECK-NEXT: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 15
754    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
755    ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
756    ; CHECK-NEXT: RET_ReallyLR
757    %0:gpr(p0) = COPY $x0
758    %1:gpr(s32) = COPY $w1
759    %2:gpr(p0) = COPY $x2
760    %small:gpr(s16) = G_TRUNC %1
761    %zext:gpr(s64) = G_SEXT %small(s16)
762    %cst:gpr(s64) = G_CONSTANT i64 3
763    %shl:gpr(s64) = G_SHL %zext, %cst(s64)
764    %gep:gpr(p0) = G_PTR_ADD %0, %shl(s64)
765    G_STORE %2(p0), %gep(p0) :: (store (p0))
766    RET_ReallyLR
767...
768---
769name:            store_8b_sext
770alignment:       4
771legalized:       true
772regBankSelected: true
773tracksRegLiveness: true
774liveins:
775  - { reg: '$x0' }
776  - { reg: '$w1' }
777  - { reg: '$x2' }
778body:             |
779  bb.1.entry:
780    liveins: $x0, $x1, $x2
781
782    ; CHECK-LABEL: name: store_8b_sext
783    ; CHECK: liveins: $x0, $x1, $x2
784    ; CHECK-NEXT: {{  $}}
785    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
786    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
787    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr64all = COPY $x2
788    ; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_32
789    ; CHECK-NEXT: %zext:gpr64 = SBFMXri [[SUBREG_TO_REG]], 0, 7
790    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr64 = COPY [[COPY2]]
791    ; CHECK-NEXT: STRXroX [[COPY3]], [[COPY]], %zext, 0, 1 :: (store (p0))
792    ; CHECK-NEXT: RET_ReallyLR
793    %0:gpr(p0) = COPY $x0
794    %1:gpr(s32) = COPY $w1
795    %2:gpr(p0) = COPY $x2
796    %small:gpr(s8) = G_TRUNC %1
797    %zext:gpr(s64) = G_SEXT %small(s8)
798    %cst:gpr(s64) = G_CONSTANT i64 3
799    %shl:gpr(s64) = G_SHL %zext, %cst(s64)
800    %gep:gpr(p0) = G_PTR_ADD %0, %shl(s64)
801    G_STORE %2(p0), %gep(p0) :: (store (p0))
802    RET_ReallyLR
803...
804