xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/select-abs.mir (revision 6cb7599078121f1e510b27170815f81f169c9554) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64-apple-ios -run-pass=instruction-select %s -o - | FileCheck %s
3
4...
5---
6name:            v4s16
7legalized:       true
8regBankSelected: true
9tracksRegLiveness: true
10body:             |
11  bb.0:
12    liveins: $d0
13
14    ; CHECK-LABEL: name: v4s16
15    ; CHECK: liveins: $d0
16    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
17    ; CHECK: [[ABSv4i16_:%[0-9]+]]:fpr64 = ABSv4i16 [[COPY]]
18    ; CHECK: $d0 = COPY [[ABSv4i16_]]
19    ; CHECK: RET_ReallyLR implicit $d0
20    %0:fpr(<4 x s16>) = COPY $d0
21    %1:fpr(<4 x s16>) = G_ABS %0
22    $d0 = COPY %1(<4 x s16>)
23    RET_ReallyLR implicit $d0
24
25...
26---
27name:            v8s16
28legalized:       true
29regBankSelected: true
30tracksRegLiveness: true
31body:             |
32  bb.0:
33    liveins: $q0
34
35    ; CHECK-LABEL: name: v8s16
36    ; CHECK: liveins: $q0
37    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
38    ; CHECK: [[ABSv8i16_:%[0-9]+]]:fpr128 = ABSv8i16 [[COPY]]
39    ; CHECK: $q0 = COPY [[ABSv8i16_]]
40    ; CHECK: RET_ReallyLR implicit $q0
41    %0:fpr(<8 x s16>) = COPY $q0
42    %1:fpr(<8 x s16>) = G_ABS %0
43    $q0 = COPY %1(<8 x s16>)
44    RET_ReallyLR implicit $q0
45
46...
47---
48name:            v2s32
49legalized:       true
50regBankSelected: true
51tracksRegLiveness: true
52body:             |
53  bb.0:
54    liveins: $d0
55
56    ; CHECK-LABEL: name: v2s32
57    ; CHECK: liveins: $d0
58    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
59    ; CHECK: [[ABSv2i32_:%[0-9]+]]:fpr64 = ABSv2i32 [[COPY]]
60    ; CHECK: $d0 = COPY [[ABSv2i32_]]
61    ; CHECK: RET_ReallyLR implicit $d0
62    %0:fpr(<2 x s32>) = COPY $d0
63    %1:fpr(<2 x s32>) = G_ABS %0
64    $d0 = COPY %1(<2 x s32>)
65    RET_ReallyLR implicit $d0
66
67...
68---
69name:            v4s32
70legalized:       true
71regBankSelected: true
72tracksRegLiveness: true
73body:             |
74  bb.0:
75    liveins: $q0
76
77    ; CHECK-LABEL: name: v4s32
78    ; CHECK: liveins: $q0
79    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
80    ; CHECK: [[ABSv4i32_:%[0-9]+]]:fpr128 = ABSv4i32 [[COPY]]
81    ; CHECK: $q0 = COPY [[ABSv4i32_]]
82    ; CHECK: RET_ReallyLR implicit $q0
83    %0:fpr(<4 x s32>) = COPY $q0
84    %1:fpr(<4 x s32>) = G_ABS %0
85    $q0 = COPY %1(<4 x s32>)
86    RET_ReallyLR implicit $q0
87
88...
89---
90name:            v4s8
91legalized:       true
92regBankSelected: true
93tracksRegLiveness: true
94body:             |
95  bb.0:
96    liveins: $d0
97
98    ; CHECK-LABEL: name: v4s8
99    ; CHECK: liveins: $d0
100    ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
101    ; CHECK: [[ABSv8i8_:%[0-9]+]]:fpr64 = ABSv8i8 [[COPY]]
102    ; CHECK: $d0 = COPY [[ABSv8i8_]]
103    ; CHECK: RET_ReallyLR implicit $d0
104    %0:fpr(<8 x s8>) = COPY $d0
105    %1:fpr(<8 x s8>) = G_ABS %0
106    $d0 = COPY %1(<8 x s8>)
107    RET_ReallyLR implicit $d0
108
109...
110---
111name:            v16s8
112legalized:       true
113regBankSelected: true
114tracksRegLiveness: true
115body:             |
116  bb.0:
117    liveins: $q0
118
119    ; CHECK-LABEL: name: v16s8
120    ; CHECK: liveins: $q0
121    ; CHECK: [[COPY:%[0-9]+]]:fpr128 = COPY $q0
122    ; CHECK: [[ABSv16i8_:%[0-9]+]]:fpr128 = ABSv16i8 [[COPY]]
123    ; CHECK: $q0 = COPY [[ABSv16i8_]]
124    ; CHECK: RET_ReallyLR implicit $q0
125    %0:fpr(<16 x s8>) = COPY $q0
126    %1:fpr(<16 x s8>) = G_ABS %0
127    $q0 = COPY %1(<16 x s8>)
128    RET_ReallyLR implicit $q0
129
130...
131