xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/ret-1x-vec.ll (revision 10b1f58cba4f7e32134a8e50e97b402f81572a5a)
1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2; RUN: llc -mtriple=aarch64-linux-gnu -O0 -global-isel -stop-after=irtranslator -o - %s | FileCheck %s
3
4define <1 x float> @ret_v1f32(<1 x float> %v) {
5  ; CHECK-LABEL: name: ret_v1f32
6  ; CHECK: bb.1 (%ir-block.0):
7  ; CHECK-NEXT:   liveins: $d0
8  ; CHECK-NEXT: {{  $}}
9  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
10  ; CHECK-NEXT:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
11  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
12  ; CHECK-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[DEF]](s32)
13  ; CHECK-NEXT:   $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)
14  ; CHECK-NEXT:   RET_ReallyLR implicit $d0
15  ret <1 x float> %v
16}
17
18define <1 x ptr> @ret_v1p0(<1 x ptr> %v) {
19  ; CHECK-LABEL: name: ret_v1p0
20  ; CHECK: bb.1 (%ir-block.0):
21  ; CHECK-NEXT:   liveins: $d0
22  ; CHECK-NEXT: {{  $}}
23  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $d0
24  ; CHECK-NEXT:   $d0 = COPY [[COPY]](p0)
25  ; CHECK-NEXT:   RET_ReallyLR implicit $d0
26  ret <1 x ptr> %v
27}
28
29define <1 x ptr addrspace(1)> @ret_v1p1(<1 x ptr addrspace(1)> %v) {
30  ; CHECK-LABEL: name: ret_v1p1
31  ; CHECK: bb.1 (%ir-block.0):
32  ; CHECK-NEXT:   liveins: $d0
33  ; CHECK-NEXT: {{  $}}
34  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p1) = COPY $d0
35  ; CHECK-NEXT:   $d0 = COPY [[COPY]](p1)
36  ; CHECK-NEXT:   RET_ReallyLR implicit $d0
37  ret <1 x ptr addrspace(1)> %v
38}
39
40define <1 x i16> @ret_v1i16(<1 x i16> %v) {
41  ; CHECK-LABEL: name: ret_v1i16
42  ; CHECK: bb.1 (%ir-block.0):
43  ; CHECK-NEXT:   liveins: $d0
44  ; CHECK-NEXT: {{  $}}
45  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
46  ; CHECK-NEXT:   [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<4 x s16>)
47  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
48  ; CHECK-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[DEF]](s16), [[DEF]](s16), [[DEF]](s16)
49  ; CHECK-NEXT:   $d0 = COPY [[BUILD_VECTOR]](<4 x s16>)
50  ; CHECK-NEXT:   RET_ReallyLR implicit $d0
51  ret <1 x i16> %v
52}
53
54define <1 x i8> @ret_v1i8(<1 x i8> %v) {
55  ; CHECK-LABEL: name: ret_v1i8
56  ; CHECK: bb.1 (%ir-block.0):
57  ; CHECK-NEXT:   liveins: $d0
58  ; CHECK-NEXT: {{  $}}
59  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
60  ; CHECK-NEXT:   [[UV:%[0-9]+]]:_(s8), [[UV1:%[0-9]+]]:_(s8), [[UV2:%[0-9]+]]:_(s8), [[UV3:%[0-9]+]]:_(s8), [[UV4:%[0-9]+]]:_(s8), [[UV5:%[0-9]+]]:_(s8), [[UV6:%[0-9]+]]:_(s8), [[UV7:%[0-9]+]]:_(s8) = G_UNMERGE_VALUES [[COPY]](<8 x s8>)
61  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
62  ; CHECK-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s8>) = G_BUILD_VECTOR [[UV]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8)
63  ; CHECK-NEXT:   $d0 = COPY [[BUILD_VECTOR]](<8 x s8>)
64  ; CHECK-NEXT:   RET_ReallyLR implicit $d0
65  ret <1 x i8> %v
66}
67
68define <1 x i32> @ret_v1i32(<1 x i32> %v) {
69  ; CHECK-LABEL: name: ret_v1i32
70  ; CHECK: bb.1 (%ir-block.0):
71  ; CHECK-NEXT:   liveins: $d0
72  ; CHECK-NEXT: {{  $}}
73  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
74  ; CHECK-NEXT:   [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
75  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
76  ; CHECK-NEXT:   [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[DEF]](s32)
77  ; CHECK-NEXT:   $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)
78  ; CHECK-NEXT:   RET_ReallyLR implicit $d0
79  ret <1 x i32> %v
80}
81
82define <1 x i64> @ret_v1i64(<1 x i64> %v) {
83  ; CHECK-LABEL: name: ret_v1i64
84  ; CHECK: bb.1 (%ir-block.0):
85  ; CHECK-NEXT:   liveins: $d0
86  ; CHECK-NEXT: {{  $}}
87  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $d0
88  ; CHECK-NEXT:   $d0 = COPY [[COPY]](s64)
89  ; CHECK-NEXT:   RET_ReallyLR implicit $d0
90  ret <1 x i64> %v
91}
92define <1 x i1> @ret_v1i1(<1 x i1> %v) {
93  ; CHECK-LABEL: name: ret_v1i1
94  ; CHECK: bb.1 (%ir-block.0):
95  ; CHECK-NEXT:   liveins: $w0
96  ; CHECK-NEXT: {{  $}}
97  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
98  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[COPY]](s32)
99  ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(s8) = G_ZEXT [[TRUNC]](s1)
100  ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ZEXT]](s8)
101  ; CHECK-NEXT:   $w0 = COPY [[ANYEXT]](s32)
102  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
103  ret <1 x i1> %v
104}
105