1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 2# RUN: llc -mtriple aarch64 -mattr=+fullfp16 -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s 3--- 4name: shl_add_k 5alignment: 4 6tracksRegLiveness: true 7body: | 8 bb.1: 9 liveins: $w1, $x0 10 11 ; CHECK-LABEL: name: shl_add_k 12 ; CHECK: liveins: $w1, $x0 13 ; CHECK-NEXT: {{ $}} 14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 15 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 16 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 17 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) 18 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 19 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[SHL]], [[C1]] 20 ; CHECK-NEXT: G_STORE [[ADD]](s32), [[COPY]](p0) :: (store (s32)) 21 ; CHECK-NEXT: RET_ReallyLR 22 %0:_(p0) = COPY $x0 23 %1:_(s32) = COPY $w1 24 %2:_(s32) = G_CONSTANT i32 1 25 %4:_(s32) = G_CONSTANT i32 2 26 %3:_(s32) = G_ADD %1, %2 27 %5:_(s32) = G_SHL %3, %4(s32) 28 G_STORE %5(s32), %0(p0) :: (store (s32)) 29 RET_ReallyLR 30 31... 32--- 33name: shl_or_k 34alignment: 4 35tracksRegLiveness: true 36body: | 37 bb.1: 38 liveins: $w1, $x0 39 40 ; CHECK-LABEL: name: shl_or_k 41 ; CHECK: liveins: $w1, $x0 42 ; CHECK-NEXT: {{ $}} 43 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 44 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 45 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 46 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[COPY1]], [[C]](s32) 47 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 48 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[SHL]], [[C1]] 49 ; CHECK-NEXT: G_STORE [[OR]](s32), [[COPY]](p0) :: (store (s32)) 50 ; CHECK-NEXT: RET_ReallyLR 51 %0:_(p0) = COPY $x0 52 %1:_(s32) = COPY $w1 53 %2:_(s32) = G_CONSTANT i32 1 54 %4:_(s32) = G_CONSTANT i32 2 55 %3:_(s32) = G_OR %1, %2 56 %5:_(s32) = G_SHL %3, %4(s32) 57 G_STORE %5(s32), %0(p0) :: (store (s32)) 58 RET_ReallyLR 59 60... 61--- 62name: shl_or_k_multiuse 63alignment: 4 64tracksRegLiveness: true 65body: | 66 bb.1: 67 liveins: $w1, $x0 68 69 ; CHECK-LABEL: name: shl_or_k_multiuse 70 ; CHECK: liveins: $w1, $x0 71 ; CHECK-NEXT: {{ $}} 72 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 73 ; CHECK-NEXT: %ptr:_(p0) = COPY $x1 74 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 75 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 76 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 77 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY1]], [[C]] 78 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[OR]], [[C1]](s32) 79 ; CHECK-NEXT: G_STORE [[SHL]](s32), [[COPY]](p0) :: (store (s32)) 80 ; CHECK-NEXT: G_STORE [[OR]](s32), %ptr(p0) :: (store (s32)) 81 ; CHECK-NEXT: RET_ReallyLR 82 %0:_(p0) = COPY $x0 83 %ptr:_(p0) = COPY $x1 84 %1:_(s32) = COPY $w1 85 %2:_(s32) = G_CONSTANT i32 1 86 %4:_(s32) = G_CONSTANT i32 2 87 %3:_(s32) = G_OR %1, %2 88 %5:_(s32) = G_SHL %3, %4(s32) 89 G_STORE %5(s32), %0(p0) :: (store (s32)) 90 G_STORE %3(s32), %ptr(p0) :: (store (s32)) 91 RET_ReallyLR 92 93... 94--- 95name: shl_add_k_vector 96alignment: 4 97tracksRegLiveness: true 98body: | 99 bb.1: 100 liveins: $w1, $x0 101 102 ; CHECK-LABEL: name: shl_add_k_vector 103 ; CHECK: liveins: $w1, $x0 104 ; CHECK-NEXT: {{ $}} 105 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 106 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 107 ; CHECK-NEXT: %xvec:_(<4 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[COPY1]](s32), [[COPY1]](s32), [[COPY1]](s32) 108 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 2 109 ; CHECK-NEXT: %veccst2:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32) 110 ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(<4 x s32>) = G_SHL %xvec, %veccst2(<4 x s32>) 111 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 112 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32) 113 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<4 x s32>) = G_ADD [[SHL]], [[BUILD_VECTOR]] 114 ; CHECK-NEXT: G_STORE [[ADD]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>)) 115 ; CHECK-NEXT: RET_ReallyLR 116 %0:_(p0) = COPY $x0 117 %1:_(s32) = COPY $w1 118 %xvec:_(<4 x s32>) = G_BUILD_VECTOR %1, %1, %1, %1 119 %2:_(s32) = G_CONSTANT i32 1 120 %veccst:_(<4 x s32>) = G_BUILD_VECTOR %2, %2, %2, %2 121 %4:_(s32) = G_CONSTANT i32 2 122 %veccst2:_(<4 x s32>) = G_BUILD_VECTOR %4, %4, %4, %4 123 %3:_(<4 x s32>) = G_ADD %xvec, %veccst2 124 %5:_(<4 x s32>) = G_SHL %3, %veccst2 125 G_STORE %5(<4 x s32>), %0(p0) :: (store (<4 x s32>)) 126 RET_ReallyLR 127 128... 129