xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-mulo-zero.mir (revision 655714a300ff303a1f283718c34d9e27e096b319)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple aarch64 -debugify-and-strip-all-safe -run-pass=aarch64-prelegalizer-combiner --aarch64prelegalizercombiner-only-enable-rule="mulo_by_0" -global-isel -verify-machineinstrs %s -o - | FileCheck %s
3# REQUIRES: asserts
4
5# (G_*MULO x, 0) -> 0 + no carry out
6
7...
8---
9name:            umulo_zero
10tracksRegLiveness: true
11body:             |
12  bb.0:
13    liveins: $w0, $w1
14    ; CHECK-LABEL: name: umulo_zero
15    ; CHECK: liveins: $w0, $w1
16    ; CHECK-NEXT: {{  $}}
17    ; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
18    ; CHECK-NEXT: %mulo:_(s32) = COPY %zero(s32)
19    ; CHECK-NEXT: %carry:_(s1) = G_CONSTANT i1 false
20    ; CHECK-NEXT: %carry_wide:_(s32) = G_ZEXT %carry(s1)
21    ; CHECK-NEXT: $w0 = COPY %mulo(s32)
22    ; CHECK-NEXT: $w1 = COPY %carry_wide(s32)
23    ; CHECK-NEXT: RET_ReallyLR implicit $w0
24    %lhs:_(s32) = COPY $w0
25    %zero:_(s32) = G_CONSTANT i32 0
26    %mulo:_(s32), %carry:_(s1) = G_UMULO %lhs, %zero
27    %carry_wide:_(s32) = G_ZEXT %carry(s1)
28    $w0 = COPY %mulo(s32)
29    $w1 = COPY %carry_wide
30    RET_ReallyLR implicit $w0
31...
32---
33name:            smulo_zero
34tracksRegLiveness: true
35body:             |
36  bb.0:
37    liveins: $w0, $w1
38    ; CHECK-LABEL: name: smulo_zero
39    ; CHECK: liveins: $w0, $w1
40    ; CHECK-NEXT: {{  $}}
41    ; CHECK-NEXT: %zero:_(s32) = G_CONSTANT i32 0
42    ; CHECK-NEXT: %mulo:_(s32) = COPY %zero(s32)
43    ; CHECK-NEXT: %carry:_(s1) = G_CONSTANT i1 false
44    ; CHECK-NEXT: %carry_wide:_(s32) = G_ZEXT %carry(s1)
45    ; CHECK-NEXT: $w0 = COPY %mulo(s32)
46    ; CHECK-NEXT: $w1 = COPY %carry_wide(s32)
47    ; CHECK-NEXT: RET_ReallyLR implicit $w0
48    %lhs:_(s32) = COPY $w0
49    %zero:_(s32) = G_CONSTANT i32 0
50    %mulo:_(s32), %carry:_(s1) = G_SMULO %lhs, %zero
51    %carry_wide:_(s32) = G_ZEXT %carry(s1)
52    $w0 = COPY %mulo(s32)
53    $w1 = COPY %carry_wide
54    RET_ReallyLR implicit $w0
55...
56---
57name:            wrong_cst
58tracksRegLiveness: true
59body:             |
60  bb.0:
61    liveins: $w0, $w1
62    ; CHECK-LABEL: name: wrong_cst
63    ; CHECK: liveins: $w0, $w1
64    ; CHECK-NEXT: {{  $}}
65    ; CHECK-NEXT: %lhs:_(s32) = COPY $w0
66    ; CHECK-NEXT: %not_zero:_(s32) = G_CONSTANT i32 3
67    ; CHECK-NEXT: %mulo:_(s32), %carry:_(s1) = G_UMULO %lhs, %not_zero
68    ; CHECK-NEXT: %carry_wide:_(s32) = G_ZEXT %carry(s1)
69    ; CHECK-NEXT: $w0 = COPY %mulo(s32)
70    ; CHECK-NEXT: $w1 = COPY %carry_wide(s32)
71    ; CHECK-NEXT: RET_ReallyLR implicit $w0
72    %lhs:_(s32) = COPY $w0
73    %not_zero:_(s32) = G_CONSTANT i32 3
74    %mulo:_(s32), %carry:_(s1) = G_UMULO %lhs, %not_zero
75    %carry_wide:_(s32) = G_ZEXT %carry(s1)
76    $w0 = COPY %mulo(s32)
77    $w1 = COPY %carry_wide
78    RET_ReallyLR implicit $w0
79...
80---
81name:            umulo_vec_zero
82tracksRegLiveness: true
83body:             |
84  bb.0:
85    liveins: $q0, $x0
86    ; CHECK-LABEL: name: umulo_vec_zero
87    ; CHECK: liveins: $q0, $x0
88    ; CHECK-NEXT: {{  $}}
89    ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
90    ; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
91    ; CHECK-NEXT: %mulo:_(<2 x s64>) = COPY %zero_vec(<2 x s64>)
92    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
93    ; CHECK-NEXT: %carry:_(<2 x s1>) = G_BUILD_VECTOR [[C]](s1), [[C]](s1)
94    ; CHECK-NEXT: %carry_elt_0:_(s1) = G_EXTRACT_VECTOR_ELT %carry(<2 x s1>), %zero(s64)
95    ; CHECK-NEXT: %carry_wide:_(s64) = G_ZEXT %carry_elt_0(s1)
96    ; CHECK-NEXT: $q0 = COPY %mulo(<2 x s64>)
97    ; CHECK-NEXT: $x0 = COPY %carry_wide(s64)
98    ; CHECK-NEXT: RET_ReallyLR implicit $q0
99    %lhs:_(<2 x s64>) = COPY $q0
100    %zero:_(s64) = G_CONSTANT i64 0
101    %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
102    %mulo:_(<2 x s64>), %carry:_(<2 x s1>) = G_UMULO %lhs, %zero_vec
103    %carry_elt_0:_(s1) = G_EXTRACT_VECTOR_ELT %carry:_(<2 x s1>), %zero:_(s64)
104    %carry_wide:_(s64) = G_ZEXT %carry_elt_0
105    $q0 = COPY %mulo(<2 x s64>)
106    $x0 = COPY %carry_wide
107    RET_ReallyLR implicit $q0
108...
109---
110name:            smulo_vec_zero
111tracksRegLiveness: true
112body:             |
113  bb.0:
114    liveins: $q0, $x0
115    ; CHECK-LABEL: name: smulo_vec_zero
116    ; CHECK: liveins: $q0, $x0
117    ; CHECK-NEXT: {{  $}}
118    ; CHECK-NEXT: %zero:_(s64) = G_CONSTANT i64 0
119    ; CHECK-NEXT: %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero(s64), %zero(s64)
120    ; CHECK-NEXT: %mulo:_(<2 x s64>) = COPY %zero_vec(<2 x s64>)
121    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s1) = G_CONSTANT i1 false
122    ; CHECK-NEXT: %carry:_(<2 x s1>) = G_BUILD_VECTOR [[C]](s1), [[C]](s1)
123    ; CHECK-NEXT: %carry_elt_0:_(s1) = G_EXTRACT_VECTOR_ELT %carry(<2 x s1>), %zero(s64)
124    ; CHECK-NEXT: %carry_wide:_(s64) = G_ZEXT %carry_elt_0(s1)
125    ; CHECK-NEXT: $q0 = COPY %mulo(<2 x s64>)
126    ; CHECK-NEXT: $x0 = COPY %carry_wide(s64)
127    ; CHECK-NEXT: RET_ReallyLR implicit $q0
128    %lhs:_(<2 x s64>) = COPY $q0
129    %zero:_(s64) = G_CONSTANT i64 0
130    %zero_vec:_(<2 x s64>) = G_BUILD_VECTOR %zero, %zero
131    %mulo:_(<2 x s64>), %carry:_(<2 x s1>) = G_SMULO %lhs, %zero_vec
132    %carry_elt_0:_(s1) = G_EXTRACT_VECTOR_ELT %carry:_(<2 x s1>), %zero:_(s64)
133    %carry_wide:_(s64) = G_ZEXT %carry_elt_0
134    $q0 = COPY %mulo(<2 x s64>)
135    $x0 = COPY %carry_wide
136    RET_ReallyLR implicit $q0
137