xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/postlegalizercombiner-extending-loads.mir (revision 1ee315ae7964c8433b772e0b5d667834994ba753)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -run-pass=aarch64-postlegalizer-combiner -global-isel -verify-machineinstrs %s -o - | FileCheck %s
3
4--- |
5  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
6  target triple = "aarch64--"
7  define void @test_zeroext(ptr %addr) {
8  entry:
9    ret void
10  }
11  define void @test_s32_to_s64(ptr %addr) {
12  entry:
13    ret void
14  }
15...
16
17---
18name:            test_zeroext
19legalized:       true
20body: |
21  bb.0.entry:
22    liveins: $x0
23    ; CHECK-LABEL: name: test_zeroext
24    ; CHECK: liveins: $x0
25    ; CHECK-NEXT: {{  $}}
26    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
27    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8) from %ir.addr)
28    ; CHECK-NEXT: $w0 = COPY [[ZEXTLOAD]](s32)
29    %0:_(p0) = COPY $x0
30    %1:_(s8) = G_LOAD %0 :: (load (s8) from %ir.addr)
31    %2:_(s32) = G_ZEXT %1
32    $w0 = COPY %2
33...
34
35---
36name:            test_s32_to_s64
37legalized:       true
38body: |
39  bb.0.entry:
40    liveins: $x0
41    ; CHECK-LABEL: name: test_s32_to_s64
42    ; CHECK: liveins: $x0
43    ; CHECK-NEXT: {{  $}}
44    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
45    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p0) :: (load (s32) from %ir.addr)
46    ; CHECK-NEXT: $x0 = COPY [[LOAD]](s64)
47    %0:_(p0) = COPY $x0
48    %1:_(s32) = G_LOAD %0 :: (load (s32) from %ir.addr)
49    %2:_(s64) = G_ANYEXT %1
50    $x0 = COPY %2
51...
52