xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/opt-fold-compare.mir (revision c3cfbbc4160c3e0284034c98b332b468328458e3) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple aarch64-unknown-unknown -run-pass=instruction-select -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
3#
4# Verify folding operations into G_ICMP.
5#
6# E.g cmn/adds folding:
7#
8# x = G_SUB 0, y
9# G_ICMP intpred(something_safe) z, x
10#
11# Folds to:
12# adds z, y
13#
14# Where "something_safe" is ne or eq.
15#
16# ands/tst folding:
17#
18# z = G_AND x, y
19# G_ICMP z, 0
20#
21# Folds to:
22#
23# tst x, y
24#
25# When we have signed comparisons.
26#
27# Tests whose names start with cmn_ should use ADDS for the G_ICMP. Tests whose
28# names start with no_cmn should use SUBS. Similarly, tests whose names start
29# with TST should use ANDS for the G_ICMP.
30#
31
32...
33---
34name:            cmn_s32_rhs
35alignment:       4
36legalized:       true
37regBankSelected: true
38tracksRegLiveness: true
39body:             |
40  bb.0:
41    liveins: $w0, $w1
42
43    ; CHECK-LABEL: name: cmn_s32_rhs
44    ; CHECK: liveins: $w0, $w1
45    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
46    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
47    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
48    ; CHECK: [[ADDSWrr:%[0-9]+]]:gpr32 = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
49    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
50    ; CHECK: $w0 = COPY [[CSINCWr]]
51    ; CHECK: RET_ReallyLR implicit $w0
52    %0:gpr(s32) = COPY $w0
53    %1:gpr(s32) = COPY $w1
54    %2:gpr(s32) = G_CONSTANT i32 0
55    %6:gpr(s32) = G_CONSTANT i32 1
56    %3:gpr(s32) = G_SUB %2, %1
57    %7:gpr(s32) = G_ICMP intpred(ne), %0(s32), %3
58    %5:gpr(s32) = G_SELECT %7, %6, %2
59    $w0 = COPY %5(s32)
60    RET_ReallyLR implicit $w0
61
62...
63---
64name:            cmn_s32_lhs
65alignment:       4
66legalized:       true
67regBankSelected: true
68tracksRegLiveness: true
69body:             |
70  bb.0:
71    liveins: $w0, $w1
72
73    ; CHECK-LABEL: name: cmn_s32_lhs
74    ; CHECK: liveins: $w0, $w1
75    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
76    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
77    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
78    ; CHECK: [[ADDSWrr:%[0-9]+]]:gpr32 = ADDSWrr [[COPY]], [[COPY1]], implicit-def $nzcv
79    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 0, implicit $nzcv
80    ; CHECK: $w0 = COPY [[CSINCWr]]
81    ; CHECK: RET_ReallyLR implicit $w0
82    %0:gpr(s32) = COPY $w0
83    %1:gpr(s32) = COPY $w1
84    %2:gpr(s32) = G_CONSTANT i32 0
85    %6:gpr(s32) = G_CONSTANT i32 1
86    %3:gpr(s32) = G_SUB %2, %0
87    %7:gpr(s32) = G_ICMP intpred(ne), %3(s32), %1
88    %5:gpr(s32) = G_SELECT %7, %6, %2
89    $w0 = COPY %5(s32)
90    RET_ReallyLR implicit $w0
91
92...
93---
94name:            no_cmn_s32_rhs
95alignment:       4
96legalized:       true
97regBankSelected: true
98tracksRegLiveness: true
99body:             |
100  bb.0:
101    liveins: $w0, $w1
102
103    ; CHECK-LABEL: name: no_cmn_s32_rhs
104    ; CHECK: liveins: $w0, $w1
105    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
106    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
107    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
108    ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY2]], [[COPY1]], implicit-def dead $nzcv
109    ; CHECK: [[SUBSWrr1:%[0-9]+]]:gpr32 = SUBSWrr [[COPY]], [[SUBSWrr]], implicit-def $nzcv
110    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 10, implicit $nzcv
111    ; CHECK: $w0 = COPY [[CSINCWr]]
112    ; CHECK: RET_ReallyLR implicit $w0
113    %0:gpr(s32) = COPY $w0
114    %1:gpr(s32) = COPY $w1
115    %2:gpr(s32) = G_CONSTANT i32 0
116    %6:gpr(s32) = G_CONSTANT i32 1
117    %3:gpr(s32) = G_SUB %2, %1
118    %7:gpr(s32) = G_ICMP intpred(slt), %0(s32), %3
119    %5:gpr(s32) = G_SELECT %7, %6, %2
120    $w0 = COPY %5(s32)
121    RET_ReallyLR implicit $w0
122
123...
124---
125name:            no_cmn_s32_lhs
126alignment:       4
127legalized:       true
128regBankSelected: true
129tracksRegLiveness: true
130body:             |
131  bb.0:
132    liveins: $w0, $w1
133
134    ; CHECK-LABEL: name: no_cmn_s32_lhs
135    ; CHECK: liveins: $w0, $w1
136    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
137    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1
138    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $wzr
139    ; CHECK: [[SUBSWrr:%[0-9]+]]:gpr32 = SUBSWrr [[COPY2]], [[COPY]], implicit-def dead $nzcv
140    ; CHECK: [[SUBSWrr1:%[0-9]+]]:gpr32 = SUBSWrr [[SUBSWrr]], [[COPY1]], implicit-def $nzcv
141    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY2]], $wzr, 10, implicit $nzcv
142    ; CHECK: $w0 = COPY [[CSINCWr]]
143    ; CHECK: RET_ReallyLR implicit $w0
144    %0:gpr(s32) = COPY $w0
145    %1:gpr(s32) = COPY $w1
146    %2:gpr(s32) = G_CONSTANT i32 0
147    %6:gpr(s32) = G_CONSTANT i32 1
148    %3:gpr(s32) = G_SUB %2, %0
149    %7:gpr(s32) = G_ICMP intpred(slt), %3(s32), %1
150    %5:gpr(s32) = G_SELECT %7, %6, %2
151    $w0 = COPY %5(s32)
152    RET_ReallyLR implicit $w0
153
154...
155---
156name:            cmn_s64_rhs
157alignment:       4
158legalized:       true
159regBankSelected: true
160tracksRegLiveness: true
161body:             |
162  bb.0:
163    liveins: $x0, $x1
164
165    ; CHECK-LABEL: name: cmn_s64_rhs
166    ; CHECK: liveins: $x0, $x1
167    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
168    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
169    ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
170    ; CHECK: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
171    ; CHECK: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 0, implicit $nzcv
172    ; CHECK: $x0 = COPY [[CSINCXr]]
173    ; CHECK: RET_ReallyLR implicit $x0
174    %0:gpr(s64) = COPY $x0
175    %1:gpr(s64) = COPY $x1
176    %2:gpr(s64) = G_CONSTANT i64 0
177    %6:gpr(s64) = G_CONSTANT i64 1
178    %3:gpr(s64) = G_SUB %2, %1
179    %7:gpr(s32) = G_ICMP intpred(ne), %0(s64), %3
180    %5:gpr(s64) = G_SELECT %7, %6, %2
181    $x0 = COPY %5(s64)
182    RET_ReallyLR implicit $x0
183
184...
185---
186name:            cmn_s64_lhs
187alignment:       4
188legalized:       true
189regBankSelected: true
190tracksRegLiveness: true
191body:             |
192  bb.0:
193    liveins: $x0, $x1
194
195    ; CHECK-LABEL: name: cmn_s64_lhs
196    ; CHECK: liveins: $x0, $x1
197    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
198    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
199    ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
200    ; CHECK: [[ADDSXrr:%[0-9]+]]:gpr64 = ADDSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
201    ; CHECK: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 0, implicit $nzcv
202    ; CHECK: $x0 = COPY [[CSINCXr]]
203    ; CHECK: RET_ReallyLR implicit $x0
204    %0:gpr(s64) = COPY $x0
205    %1:gpr(s64) = COPY $x1
206    %2:gpr(s64) = G_CONSTANT i64 0
207    %6:gpr(s64) = G_CONSTANT i64 1
208    %3:gpr(s64) = G_SUB %2, %0
209    %7:gpr(s32) = G_ICMP intpred(ne), %3(s64), %1
210    %5:gpr(s64) = G_SELECT %7, %6, %2
211    $x0 = COPY %5(s64)
212    RET_ReallyLR implicit $x0
213
214...
215---
216name:            no_cmn_s64_rhs
217alignment:       4
218legalized:       true
219regBankSelected: true
220tracksRegLiveness: true
221body:             |
222  bb.0:
223    liveins: $x0, $x1
224
225    ; CHECK-LABEL: name: no_cmn_s64_rhs
226    ; CHECK: liveins: $x0, $x1
227    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
228    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
229    ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
230    ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY1]], implicit-def dead $nzcv
231    ; CHECK: [[SUBSXrr1:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[SUBSXrr]], implicit-def $nzcv
232    ; CHECK: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 10, implicit $nzcv
233    ; CHECK: $x0 = COPY [[CSINCXr]]
234    ; CHECK: RET_ReallyLR implicit $x0
235    %0:gpr(s64) = COPY $x0
236    %1:gpr(s64) = COPY $x1
237    %2:gpr(s64) = G_CONSTANT i64 0
238    %6:gpr(s64) = G_CONSTANT i64 1
239    %3:gpr(s64) = G_SUB %2, %1
240    %7:gpr(s32) = G_ICMP intpred(slt), %0(s64), %3
241    %5:gpr(s64) = G_SELECT %7, %6, %2
242    $x0 = COPY %5(s64)
243    RET_ReallyLR implicit $x0
244
245...
246---
247name:            no_cmn_s64_lhs
248alignment:       4
249legalized:       true
250regBankSelected: true
251tracksRegLiveness: true
252body:             |
253  bb.0:
254    liveins: $x0, $x1
255
256    ; CHECK-LABEL: name: no_cmn_s64_lhs
257    ; CHECK: liveins: $x0, $x1
258    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
259    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
260    ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY $xzr
261    ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY2]], [[COPY]], implicit-def dead $nzcv
262    ; CHECK: [[SUBSXrr1:%[0-9]+]]:gpr64 = SUBSXrr [[SUBSXrr]], [[COPY1]], implicit-def $nzcv
263    ; CHECK: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY2]], $xzr, 10, implicit $nzcv
264    ; CHECK: $x0 = COPY [[CSINCXr]]
265    ; CHECK: RET_ReallyLR implicit $x0
266    %0:gpr(s64) = COPY $x0
267    %1:gpr(s64) = COPY $x1
268    %2:gpr(s64) = G_CONSTANT i64 0
269    %6:gpr(s64) = G_CONSTANT i64 1
270    %3:gpr(s64) = G_SUB %2, %0
271    %7:gpr(s32) = G_ICMP intpred(slt), %3(s64), %1
272    %5:gpr(s64) = G_SELECT %7, %6, %2
273    $x0 = COPY %5(s64)
274    RET_ReallyLR implicit $x0
275
276...
277---
278name:            tst_s32
279alignment:       4
280legalized:       true
281regBankSelected: true
282tracksRegLiveness: true
283body:             |
284  bb.0:
285    liveins: $w0, $w1
286    ; CHECK-LABEL: name: tst_s32
287    ; CHECK: liveins: $w0, $w1
288    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
289    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
290    ; CHECK: [[ANDSWrr:%[0-9]+]]:gpr32 = ANDSWrr [[COPY1]], [[COPY]], implicit-def $nzcv
291    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY1]], $wzr, 1, implicit $nzcv
292    ; CHECK: $w0 = COPY [[CSINCWr]]
293    ; CHECK: RET_ReallyLR implicit $w0
294    %0:gpr(s32) = COPY $w0
295    %1:gpr(s32) = COPY $w1
296    %2:gpr(s32) = G_CONSTANT i32 0
297    %6:gpr(s32) = G_CONSTANT i32 1
298    %3:gpr(s32) = G_AND %2, %1
299    %8:gpr(s32) = G_CONSTANT i32 0
300    %7:gpr(s32) = G_ICMP intpred(eq), %3(s32), %8
301    %5:gpr(s32) = G_SELECT %7, %6, %2
302    $w0 = COPY %5(s32)
303    RET_ReallyLR implicit $w0
304
305...
306---
307name:            tst_s64
308alignment:       4
309legalized:       true
310regBankSelected: true
311tracksRegLiveness: true
312body:             |
313  bb.0:
314    liveins: $x0, $x1
315    ; CHECK-LABEL: name: tst_s64
316    ; CHECK: liveins: $x0, $x1
317    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x1
318    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $xzr
319    ; CHECK: [[ANDSXrr:%[0-9]+]]:gpr64 = ANDSXrr [[COPY1]], [[COPY]], implicit-def $nzcv
320    ; CHECK: [[CSINCXr:%[0-9]+]]:gpr64 = CSINCXr [[COPY1]], $xzr, 1, implicit $nzcv
321    ; CHECK: $x0 = COPY [[CSINCXr]]
322    ; CHECK: RET_ReallyLR implicit $x0
323    %0:gpr(s64) = COPY $x0
324    %1:gpr(s64) = COPY $x1
325    %2:gpr(s64) = G_CONSTANT i64 0
326    %6:gpr(s64) = G_CONSTANT i64 1
327    %3:gpr(s64) = G_AND %2, %1
328    %8:gpr(s64) = G_CONSTANT i64 0
329    %7:gpr(s32) = G_ICMP intpred(eq), %3(s64), %8
330    %5:gpr(s64) = G_SELECT %7, %6, %2
331    $x0 = COPY %5(s64)
332    RET_ReallyLR implicit $x0
333
334...
335---
336name:            no_tst_unsigned_compare
337alignment:       4
338legalized:       true
339regBankSelected: true
340tracksRegLiveness: true
341body:             |
342  bb.0:
343    liveins: $w0, $w1
344    ; CHECK-LABEL: name: no_tst_unsigned_compare
345    ; CHECK: liveins: $w0, $w1
346    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
347    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
348    ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[COPY1]], [[COPY]]
349    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ANDWrr]], 0, 0, implicit-def $nzcv
350    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY1]], $wzr, 9, implicit $nzcv
351    ; CHECK: $w0 = COPY [[CSINCWr]]
352    ; CHECK: RET_ReallyLR implicit $w0
353    %0:gpr(s32) = COPY $w0
354    %1:gpr(s32) = COPY $w1
355    %2:gpr(s32) = G_CONSTANT i32 0
356    %6:gpr(s32) = G_CONSTANT i32 1
357    %3:gpr(s32) = G_AND %2, %1
358    %8:gpr(s32) = G_CONSTANT i32 0
359    %7:gpr(s32) = G_ICMP intpred(ugt), %3(s32), %8
360    %5:gpr(s32) = G_SELECT %7, %6, %2
361    $w0 = COPY %5(s32)
362    RET_ReallyLR implicit $w0
363
364...
365---
366name:            no_tst_nonzero
367alignment:       4
368legalized:       true
369regBankSelected: true
370tracksRegLiveness: true
371body:             |
372  bb.0:
373    liveins: $w0, $w1
374    ; CHECK-LABEL: name: no_tst_nonzero
375    ; CHECK: liveins: $w0, $w1
376    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
377    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $wzr
378    ; CHECK: [[ANDWrr:%[0-9]+]]:gpr32common = ANDWrr [[COPY1]], [[COPY]]
379    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[ANDWrr]], 42, 0, implicit-def $nzcv
380    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr [[COPY1]], $wzr, 9, implicit $nzcv
381    ; CHECK: $w0 = COPY [[CSINCWr]]
382    ; CHECK: RET_ReallyLR implicit $w0
383    %0:gpr(s32) = COPY $w0
384    %1:gpr(s32) = COPY $w1
385    %2:gpr(s32) = G_CONSTANT i32 0
386    %6:gpr(s32) = G_CONSTANT i32 1
387    %3:gpr(s32) = G_AND %2, %1
388    %8:gpr(s32) = G_CONSTANT i32 42
389    %7:gpr(s32) = G_ICMP intpred(ugt), %3(s32), %8
390    %5:gpr(s32) = G_SELECT %7, %6, %2
391    $w0 = COPY %5(s32)
392    RET_ReallyLR implicit $w0
393
394...
395---
396name:            imm_tst
397alignment:       4
398legalized:       true
399regBankSelected: true
400tracksRegLiveness: true
401body:             |
402  bb.0:
403    liveins: $w0, $w1
404    ; CHECK-LABEL: name: imm_tst
405    ; CHECK: liveins: $w0, $w1
406    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
407    ; CHECK: [[ANDSWri:%[0-9]+]]:gpr32 = ANDSWri [[COPY]], 1, implicit-def $nzcv
408    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
409    ; CHECK: $w0 = COPY [[CSINCWr]]
410    ; CHECK: RET_ReallyLR implicit $w0
411    %0:gpr(s32) = COPY $w0
412    %1:gpr(s32) = COPY $w1
413    %2:gpr(s32) = G_CONSTANT i32 0
414    %3:gpr(s32) = G_CONSTANT i32 1
415
416    ; This can be represented as a logical immediate, so we can pull it into
417    ; the ANDS. We should get ANDSWri.
418    %4:gpr(s32) = G_CONSTANT i32 3
419
420    %5:gpr(s32) = G_AND %1, %4
421    %6:gpr(s32) = G_ICMP intpred(eq), %5(s32), %2
422    $w0 = COPY %6(s32)
423    RET_ReallyLR implicit $w0
424
425
426...
427---
428name:            no_imm_tst_not_logical_imm
429alignment:       4
430legalized:       true
431regBankSelected: true
432tracksRegLiveness: true
433body:             |
434  bb.0:
435    liveins: $w0, $w1
436    ; CHECK-LABEL: name: no_imm_tst_not_logical_imm
437    ; CHECK: liveins: $w0, $w1
438    ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w1
439    ; CHECK: [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm -1
440    ; CHECK: [[ANDSWrr:%[0-9]+]]:gpr32 = ANDSWrr [[COPY]], [[MOVi32imm]], implicit-def $nzcv
441    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
442    ; CHECK: $w0 = COPY [[CSINCWr]]
443    ; CHECK: RET_ReallyLR implicit $w0
444    %0:gpr(s32) = COPY $w0
445    %1:gpr(s32) = COPY $w1
446    %2:gpr(s32) = G_CONSTANT i32 0
447    %3:gpr(s32) = G_CONSTANT i32 1
448
449    ; This immediate can't be represented as a logical immediate. We shouldn't
450    ; select ANDSWri.
451    %4:gpr(s32) = G_CONSTANT i32 -1
452
453    %5:gpr(s32) = G_AND %1, %4
454    %6:gpr(s32) = G_ICMP intpred(eq), %5(s32), %2
455    $w0 = COPY %6(s32)
456    RET_ReallyLR implicit $w0
457
458...
459---
460name:            test_physreg_copy
461alignment:       4
462legalized:       true
463regBankSelected: true
464tracksRegLiveness: true
465body:             |
466  bb.0:
467    liveins: $x0, $x1
468    ; CHECK-LABEL: name: test_physreg_copy
469    ; CHECK: liveins: $x0, $x1
470    ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
471    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1
472    ; CHECK: [[SUBSXrr:%[0-9]+]]:gpr64 = SUBSXrr [[COPY]], [[COPY1]], implicit-def $nzcv
473    ; CHECK: [[CSINCWr:%[0-9]+]]:gpr32 = CSINCWr $wzr, $wzr, 1, implicit $nzcv
474    ; CHECK: $w0 = COPY [[CSINCWr]]
475    ; CHECK: RET_ReallyLR implicit $x0
476    %0:gpr(s64) = COPY $x0
477    %1:gpr(s64) = COPY $x1
478    ; When we find the defs of the LHS and RHS of the compare, we walk over
479    ; copies. Make sure that we don't crash when we hit a copy from a physical
480    ; register.
481    %7:gpr(s32) = G_ICMP intpred(eq), %0, %1
482    $w0 = COPY %7(s32)
483    RET_ReallyLR implicit $x0
484
485...
486---
487name:            tst_fold_shift_s64
488alignment:       4
489legalized:       true
490regBankSelected: true
491tracksRegLiveness: true
492body:             |
493  bb.0:
494    liveins: $x0, $x1
495    ; We should fold the G_SHL into the ANDS to get ANDSXrs.
496    ;
497    ; CHECK-LABEL: name: tst_fold_shift_s64
498    ; CHECK: liveins: $x0, $x1
499    ; CHECK: %copy:gpr64 = COPY $x1
500    ; CHECK: %zero:gpr64 = COPY $xzr
501    ; CHECK: [[ANDSXrs:%[0-9]+]]:gpr64 = ANDSXrs %zero, %copy, 16, implicit-def $nzcv
502    ; CHECK: %select:gpr64 = CSINCXr %zero, $xzr, 1, implicit $nzcv
503    ; CHECK: $x0 = COPY %select
504    ; CHECK: RET_ReallyLR implicit $x0
505    %copy:gpr(s64) = COPY $x1
506    %zero:gpr(s64) = G_CONSTANT i64 0
507    %one:gpr(s64) = G_CONSTANT i64 1
508    %cst:gpr(s64) = G_CONSTANT i64 16
509    %shift:gpr(s64) = G_SHL %copy(s64), %cst(s64)
510    %and:gpr(s64) = G_AND %zero, %shift
511    %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s64), %zero
512    %select:gpr(s64) = G_SELECT %cmp, %one, %zero
513    $x0 = COPY %select(s64)
514    RET_ReallyLR implicit $x0
515
516...
517---
518name:            tst_fold_shift_s32
519alignment:       4
520legalized:       true
521regBankSelected: true
522tracksRegLiveness: true
523body:             |
524  bb.0:
525    liveins: $w0, $w1
526    ; We should fold the G_SHL into the ANDS to get ANDSWrs.
527    ;
528    ; CHECK-LABEL: name: tst_fold_shift_s32
529    ; CHECK: liveins: $w0, $w1
530    ; CHECK: %copy:gpr32 = COPY $w1
531    ; CHECK: %zero:gpr32 = COPY $wzr
532    ; CHECK: [[ANDSWrs:%[0-9]+]]:gpr32 = ANDSWrs %zero, %copy, 16, implicit-def $nzcv
533    ; CHECK: %select:gpr32 = CSINCWr %zero, $wzr, 1, implicit $nzcv
534    ; CHECK: $w0 = COPY %select
535    ; CHECK: RET_ReallyLR implicit $w0
536    %copy:gpr(s32) = COPY $w1
537    %zero:gpr(s32) = G_CONSTANT i32 0
538    %one:gpr(s32) = G_CONSTANT i32 1
539    %cst:gpr(s32) = G_CONSTANT i32 16
540    %shift:gpr(s32) = G_SHL %copy(s32), %cst(s32)
541    %and:gpr(s32) = G_AND %zero, %shift
542    %cmp:gpr(s32) = G_ICMP intpred(eq), %and(s32), %zero
543    %select:gpr(s32) = G_SELECT %cmp, %one, %zero
544    $w0 = COPY %select(s32)
545    RET_ReallyLR implicit $w0
546
547...
548---
549name:            cmn_s32_neg_imm
550alignment:       4
551legalized:       true
552regBankSelected: true
553tracksRegLiveness: true
554body:             |
555  bb.0:
556    liveins: $w0, $w1
557
558    ; CHECK-LABEL: name: cmn_s32_neg_imm
559    ; CHECK: liveins: $w0, $w1
560    ; CHECK: %reg0:gpr32sp = COPY $w0
561    ; CHECK: [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri %reg0, 1, 0, implicit-def $nzcv
562    ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
563    ; CHECK: $w0 = COPY %cmp
564    ; CHECK: RET_ReallyLR implicit $w0
565    %reg0:gpr(s32) = COPY $w0
566    %negative_one:gpr(s32) = G_CONSTANT i32 -1
567    %zero:gpr(s32) = G_CONSTANT i32 0
568    %sub:gpr(s32) = G_SUB %zero, %negative_one
569    %cmp:gpr(s32) = G_ICMP intpred(ne), %reg0(s32), %sub
570    $w0 = COPY %cmp(s32)
571    RET_ReallyLR implicit $w0
572
573...
574---
575name:            cmn_arith_extended_shl
576alignment:       4
577legalized:       true
578regBankSelected: true
579tracksRegLiveness: true
580body:             |
581  bb.0:
582    liveins: $w0, $x0, $x1
583    ; We should be able to fold away the extend + shift and select ADDSXrx.
584
585    ; CHECK-LABEL: name: cmn_arith_extended_shl
586    ; CHECK: liveins: $w0, $x0, $x1
587    ; CHECK: %reg0:gpr64sp = COPY $x0
588    ; CHECK: %reg1:gpr32 = COPY $w0
589    ; CHECK: [[ADDSXrx:%[0-9]+]]:gpr64 = ADDSXrx %reg0, %reg1, 50, implicit-def $nzcv
590    ; CHECK: %cmp:gpr32 = CSINCWr $wzr, $wzr, 0, implicit $nzcv
591    ; CHECK: $w0 = COPY %cmp
592    ; CHECK: RET_ReallyLR implicit $w0
593    %reg0:gpr(s64) = COPY $x0
594    %zero:gpr(s64) = G_CONSTANT i64 0
595    %sub:gpr(s64) = G_SUB %zero, %reg0
596
597    %reg1:gpr(s32) = COPY $w0
598    %ext:gpr(s64) = G_SEXT %reg1(s32)
599    %cst:gpr(s64) = G_CONSTANT i64 2
600    %shift:gpr(s64) = G_SHL %ext, %cst(s64)
601
602    %cmp:gpr(s32) = G_ICMP intpred(ne), %sub(s64), %shift
603    $w0 = COPY %cmp(s32)
604    RET_ReallyLR implicit $w0
605