1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64 -run-pass=legalizer %s -o - -verify-machineinstrs | FileCheck %s 3--- 4name: test_v2i64_eq 5alignment: 4 6tracksRegLiveness: true 7registers: 8 - { id: 0, class: _ } 9 - { id: 1, class: _ } 10 - { id: 2, class: _ } 11 - { id: 3, class: _ } 12machineFunctionInfo: {} 13body: | 14 bb.1: 15 liveins: $q0, $q1 16 17 ; CHECK-LABEL: name: test_v2i64_eq 18 ; CHECK: liveins: $q0, $q1 19 ; CHECK-NEXT: {{ $}} 20 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 21 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 22 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(eq), [[COPY]](<2 x s64>), [[COPY1]] 23 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 24 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>) 25 ; CHECK-NEXT: RET_ReallyLR implicit $d0 26 %0:_(<2 x s64>) = COPY $q0 27 %1:_(<2 x s64>) = COPY $q1 28 %2:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s64>), %1 29 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 30 $d0 = COPY %3(<2 x s32>) 31 RET_ReallyLR implicit $d0 32 33... 34--- 35name: test_v4i32_eq 36alignment: 4 37tracksRegLiveness: true 38registers: 39 - { id: 0, class: _ } 40 - { id: 1, class: _ } 41 - { id: 2, class: _ } 42 - { id: 3, class: _ } 43machineFunctionInfo: {} 44body: | 45 bb.1: 46 liveins: $q0, $q1 47 48 ; CHECK-LABEL: name: test_v4i32_eq 49 ; CHECK: liveins: $q0, $q1 50 ; CHECK-NEXT: {{ $}} 51 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 52 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 53 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY]](<4 x s32>), [[COPY1]] 54 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 55 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>) 56 ; CHECK-NEXT: RET_ReallyLR implicit $d0 57 %0:_(<4 x s32>) = COPY $q0 58 %1:_(<4 x s32>) = COPY $q1 59 %2:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s32>), %1 60 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 61 $d0 = COPY %3(<4 x s16>) 62 RET_ReallyLR implicit $d0 63 64... 65--- 66name: test_v2i32_eq 67alignment: 4 68tracksRegLiveness: true 69registers: 70 - { id: 0, class: _ } 71 - { id: 1, class: _ } 72 - { id: 2, class: _ } 73 - { id: 3, class: _ } 74machineFunctionInfo: {} 75body: | 76 bb.1: 77 liveins: $d0, $d1 78 79 ; CHECK-LABEL: name: test_v2i32_eq 80 ; CHECK: liveins: $d0, $d1 81 ; CHECK-NEXT: {{ $}} 82 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 83 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 84 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY]](<2 x s32>), [[COPY1]] 85 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<2 x s32>) 86 ; CHECK-NEXT: RET_ReallyLR implicit $d0 87 %0:_(<2 x s32>) = COPY $d0 88 %1:_(<2 x s32>) = COPY $d1 89 %2:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s32>), %1 90 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 91 $d0 = COPY %3(<2 x s32>) 92 RET_ReallyLR implicit $d0 93 94... 95--- 96name: test_v8i16_eq 97alignment: 4 98tracksRegLiveness: true 99registers: 100 - { id: 0, class: _ } 101 - { id: 1, class: _ } 102 - { id: 2, class: _ } 103 - { id: 3, class: _ } 104machineFunctionInfo: {} 105body: | 106 bb.1: 107 liveins: $q0, $q1 108 109 ; CHECK-LABEL: name: test_v8i16_eq 110 ; CHECK: liveins: $q0, $q1 111 ; CHECK-NEXT: {{ $}} 112 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 113 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1 114 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(eq), [[COPY]](<8 x s16>), [[COPY1]] 115 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>) 116 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<8 x s8>) 117 ; CHECK-NEXT: RET_ReallyLR implicit $d0 118 %0:_(<8 x s16>) = COPY $q0 119 %1:_(<8 x s16>) = COPY $q1 120 %2:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s16>), %1 121 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 122 $d0 = COPY %3(<8 x s8>) 123 RET_ReallyLR implicit $d0 124 125... 126--- 127name: test_v4i16_eq 128alignment: 4 129tracksRegLiveness: true 130registers: 131 - { id: 0, class: _ } 132 - { id: 1, class: _ } 133 - { id: 2, class: _ } 134 - { id: 3, class: _ } 135machineFunctionInfo: {} 136body: | 137 bb.1: 138 liveins: $d0, $d1 139 140 ; CHECK-LABEL: name: test_v4i16_eq 141 ; CHECK: liveins: $d0, $d1 142 ; CHECK-NEXT: {{ $}} 143 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 144 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1 145 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY]](<4 x s16>), [[COPY1]] 146 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<4 x s16>) 147 ; CHECK-NEXT: RET_ReallyLR implicit $d0 148 %0:_(<4 x s16>) = COPY $d0 149 %1:_(<4 x s16>) = COPY $d1 150 %2:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s16>), %1 151 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 152 $d0 = COPY %3(<4 x s16>) 153 RET_ReallyLR implicit $d0 154 155... 156--- 157name: test_v16i8_eq 158alignment: 4 159tracksRegLiveness: true 160registers: 161 - { id: 0, class: _ } 162 - { id: 1, class: _ } 163 - { id: 2, class: _ } 164 - { id: 3, class: _ } 165machineFunctionInfo: {} 166body: | 167 bb.1: 168 liveins: $q0, $q1 169 170 ; CHECK-LABEL: name: test_v16i8_eq 171 ; CHECK: liveins: $q0, $q1 172 ; CHECK-NEXT: {{ $}} 173 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 174 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 175 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]] 176 ; CHECK-NEXT: $q0 = COPY [[ICMP]](<16 x s8>) 177 ; CHECK-NEXT: RET_ReallyLR implicit $q0 178 %0:_(<16 x s8>) = COPY $q0 179 %1:_(<16 x s8>) = COPY $q1 180 %2:_(<16 x s1>) = G_ICMP intpred(eq), %0(<16 x s8>), %1 181 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>) 182 $q0 = COPY %3(<16 x s8>) 183 RET_ReallyLR implicit $q0 184 185... 186--- 187name: test_v8i8_eq 188alignment: 4 189tracksRegLiveness: true 190registers: 191 - { id: 0, class: _ } 192 - { id: 1, class: _ } 193 - { id: 2, class: _ } 194 - { id: 3, class: _ } 195machineFunctionInfo: {} 196body: | 197 bb.1: 198 liveins: $d0, $d1 199 200 ; CHECK-LABEL: name: test_v8i8_eq 201 ; CHECK: liveins: $d0, $d1 202 ; CHECK-NEXT: {{ $}} 203 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 204 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 205 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY]](<8 x s8>), [[COPY1]] 206 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<8 x s8>) 207 ; CHECK-NEXT: RET_ReallyLR implicit $d0 208 %0:_(<8 x s8>) = COPY $d0 209 %1:_(<8 x s8>) = COPY $d1 210 %2:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s8>), %1 211 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 212 $d0 = COPY %3(<8 x s8>) 213 RET_ReallyLR implicit $d0 214 215... 216--- 217name: test_v2i64_ugt 218alignment: 4 219tracksRegLiveness: true 220registers: 221 - { id: 0, class: _ } 222 - { id: 1, class: _ } 223 - { id: 2, class: _ } 224 - { id: 3, class: _ } 225machineFunctionInfo: {} 226body: | 227 bb.1: 228 liveins: $q0, $q1 229 230 ; CHECK-LABEL: name: test_v2i64_ugt 231 ; CHECK: liveins: $q0, $q1 232 ; CHECK-NEXT: {{ $}} 233 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 234 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 235 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[COPY]](<2 x s64>), [[COPY1]] 236 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 237 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>) 238 ; CHECK-NEXT: RET_ReallyLR implicit $d0 239 %0:_(<2 x s64>) = COPY $q0 240 %1:_(<2 x s64>) = COPY $q1 241 %2:_(<2 x s1>) = G_ICMP intpred(ugt), %0(<2 x s64>), %1 242 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 243 $d0 = COPY %3(<2 x s32>) 244 RET_ReallyLR implicit $d0 245 246... 247--- 248name: test_v4i32_ugt 249alignment: 4 250tracksRegLiveness: true 251registers: 252 - { id: 0, class: _ } 253 - { id: 1, class: _ } 254 - { id: 2, class: _ } 255 - { id: 3, class: _ } 256machineFunctionInfo: {} 257body: | 258 bb.1: 259 liveins: $q0, $q1 260 261 ; CHECK-LABEL: name: test_v4i32_ugt 262 ; CHECK: liveins: $q0, $q1 263 ; CHECK-NEXT: {{ $}} 264 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 265 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 266 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(ugt), [[COPY]](<4 x s32>), [[COPY1]] 267 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 268 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>) 269 ; CHECK-NEXT: RET_ReallyLR implicit $d0 270 %0:_(<4 x s32>) = COPY $q0 271 %1:_(<4 x s32>) = COPY $q1 272 %2:_(<4 x s1>) = G_ICMP intpred(ugt), %0(<4 x s32>), %1 273 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 274 $d0 = COPY %3(<4 x s16>) 275 RET_ReallyLR implicit $d0 276 277... 278--- 279name: test_v2i32_ugt 280alignment: 4 281tracksRegLiveness: true 282registers: 283 - { id: 0, class: _ } 284 - { id: 1, class: _ } 285 - { id: 2, class: _ } 286 - { id: 3, class: _ } 287machineFunctionInfo: {} 288body: | 289 bb.1: 290 liveins: $d0, $d1 291 292 ; CHECK-LABEL: name: test_v2i32_ugt 293 ; CHECK: liveins: $d0, $d1 294 ; CHECK-NEXT: {{ $}} 295 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 296 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 297 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(ugt), [[COPY]](<2 x s32>), [[COPY1]] 298 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<2 x s32>) 299 ; CHECK-NEXT: RET_ReallyLR implicit $d0 300 %0:_(<2 x s32>) = COPY $d0 301 %1:_(<2 x s32>) = COPY $d1 302 %2:_(<2 x s1>) = G_ICMP intpred(ugt), %0(<2 x s32>), %1 303 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 304 $d0 = COPY %3(<2 x s32>) 305 RET_ReallyLR implicit $d0 306 307... 308--- 309name: test_v8i16_ugt 310alignment: 4 311tracksRegLiveness: true 312registers: 313 - { id: 0, class: _ } 314 - { id: 1, class: _ } 315 - { id: 2, class: _ } 316 - { id: 3, class: _ } 317machineFunctionInfo: {} 318body: | 319 bb.1: 320 liveins: $q0, $q1 321 322 ; CHECK-LABEL: name: test_v8i16_ugt 323 ; CHECK: liveins: $q0, $q1 324 ; CHECK-NEXT: {{ $}} 325 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 326 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1 327 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(ugt), [[COPY]](<8 x s16>), [[COPY1]] 328 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>) 329 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<8 x s8>) 330 ; CHECK-NEXT: RET_ReallyLR implicit $d0 331 %0:_(<8 x s16>) = COPY $q0 332 %1:_(<8 x s16>) = COPY $q1 333 %2:_(<8 x s1>) = G_ICMP intpred(ugt), %0(<8 x s16>), %1 334 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 335 $d0 = COPY %3(<8 x s8>) 336 RET_ReallyLR implicit $d0 337 338... 339--- 340name: test_v4i16_ugt 341alignment: 4 342tracksRegLiveness: true 343registers: 344 - { id: 0, class: _ } 345 - { id: 1, class: _ } 346 - { id: 2, class: _ } 347 - { id: 3, class: _ } 348machineFunctionInfo: {} 349body: | 350 bb.1: 351 liveins: $d0, $d1 352 353 ; CHECK-LABEL: name: test_v4i16_ugt 354 ; CHECK: liveins: $d0, $d1 355 ; CHECK-NEXT: {{ $}} 356 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 357 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1 358 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(ugt), [[COPY]](<4 x s16>), [[COPY1]] 359 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<4 x s16>) 360 ; CHECK-NEXT: RET_ReallyLR implicit $d0 361 %0:_(<4 x s16>) = COPY $d0 362 %1:_(<4 x s16>) = COPY $d1 363 %2:_(<4 x s1>) = G_ICMP intpred(ugt), %0(<4 x s16>), %1 364 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 365 $d0 = COPY %3(<4 x s16>) 366 RET_ReallyLR implicit $d0 367 368... 369--- 370name: test_v16i8_ugt 371alignment: 4 372tracksRegLiveness: true 373registers: 374 - { id: 0, class: _ } 375 - { id: 1, class: _ } 376 - { id: 2, class: _ } 377 - { id: 3, class: _ } 378machineFunctionInfo: {} 379body: | 380 bb.1: 381 liveins: $q0, $q1 382 383 ; CHECK-LABEL: name: test_v16i8_ugt 384 ; CHECK: liveins: $q0, $q1 385 ; CHECK-NEXT: {{ $}} 386 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 387 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 388 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(ugt), [[COPY]](<16 x s8>), [[COPY1]] 389 ; CHECK-NEXT: $q0 = COPY [[ICMP]](<16 x s8>) 390 ; CHECK-NEXT: RET_ReallyLR implicit $q0 391 %0:_(<16 x s8>) = COPY $q0 392 %1:_(<16 x s8>) = COPY $q1 393 %2:_(<16 x s1>) = G_ICMP intpred(ugt), %0(<16 x s8>), %1 394 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>) 395 $q0 = COPY %3(<16 x s8>) 396 RET_ReallyLR implicit $q0 397 398... 399--- 400name: test_v8i8_ugt 401alignment: 4 402tracksRegLiveness: true 403registers: 404 - { id: 0, class: _ } 405 - { id: 1, class: _ } 406 - { id: 2, class: _ } 407 - { id: 3, class: _ } 408machineFunctionInfo: {} 409body: | 410 bb.1: 411 liveins: $d0, $d1 412 413 ; CHECK-LABEL: name: test_v8i8_ugt 414 ; CHECK: liveins: $d0, $d1 415 ; CHECK-NEXT: {{ $}} 416 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 417 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 418 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(ugt), [[COPY]](<8 x s8>), [[COPY1]] 419 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<8 x s8>) 420 ; CHECK-NEXT: RET_ReallyLR implicit $d0 421 %0:_(<8 x s8>) = COPY $d0 422 %1:_(<8 x s8>) = COPY $d1 423 %2:_(<8 x s1>) = G_ICMP intpred(ugt), %0(<8 x s8>), %1 424 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 425 $d0 = COPY %3(<8 x s8>) 426 RET_ReallyLR implicit $d0 427 428... 429--- 430name: test_v2i64_uge 431alignment: 4 432tracksRegLiveness: true 433registers: 434 - { id: 0, class: _ } 435 - { id: 1, class: _ } 436 - { id: 2, class: _ } 437 - { id: 3, class: _ } 438machineFunctionInfo: {} 439body: | 440 bb.1: 441 liveins: $q0, $q1 442 443 ; CHECK-LABEL: name: test_v2i64_uge 444 ; CHECK: liveins: $q0, $q1 445 ; CHECK-NEXT: {{ $}} 446 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 447 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 448 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(uge), [[COPY]](<2 x s64>), [[COPY1]] 449 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 450 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>) 451 ; CHECK-NEXT: RET_ReallyLR implicit $d0 452 %0:_(<2 x s64>) = COPY $q0 453 %1:_(<2 x s64>) = COPY $q1 454 %2:_(<2 x s1>) = G_ICMP intpred(uge), %0(<2 x s64>), %1 455 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 456 $d0 = COPY %3(<2 x s32>) 457 RET_ReallyLR implicit $d0 458 459... 460--- 461name: test_v4i32_uge 462alignment: 4 463tracksRegLiveness: true 464registers: 465 - { id: 0, class: _ } 466 - { id: 1, class: _ } 467 - { id: 2, class: _ } 468 - { id: 3, class: _ } 469machineFunctionInfo: {} 470body: | 471 bb.1: 472 liveins: $q0, $q1 473 474 ; CHECK-LABEL: name: test_v4i32_uge 475 ; CHECK: liveins: $q0, $q1 476 ; CHECK-NEXT: {{ $}} 477 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 478 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 479 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(uge), [[COPY]](<4 x s32>), [[COPY1]] 480 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 481 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>) 482 ; CHECK-NEXT: RET_ReallyLR implicit $d0 483 %0:_(<4 x s32>) = COPY $q0 484 %1:_(<4 x s32>) = COPY $q1 485 %2:_(<4 x s1>) = G_ICMP intpred(uge), %0(<4 x s32>), %1 486 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 487 $d0 = COPY %3(<4 x s16>) 488 RET_ReallyLR implicit $d0 489 490... 491--- 492name: test_v2i32_uge 493alignment: 4 494tracksRegLiveness: true 495registers: 496 - { id: 0, class: _ } 497 - { id: 1, class: _ } 498 - { id: 2, class: _ } 499 - { id: 3, class: _ } 500machineFunctionInfo: {} 501body: | 502 bb.1: 503 liveins: $d0, $d1 504 505 ; CHECK-LABEL: name: test_v2i32_uge 506 ; CHECK: liveins: $d0, $d1 507 ; CHECK-NEXT: {{ $}} 508 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 509 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 510 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(uge), [[COPY]](<2 x s32>), [[COPY1]] 511 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<2 x s32>) 512 ; CHECK-NEXT: RET_ReallyLR implicit $d0 513 %0:_(<2 x s32>) = COPY $d0 514 %1:_(<2 x s32>) = COPY $d1 515 %2:_(<2 x s1>) = G_ICMP intpred(uge), %0(<2 x s32>), %1 516 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 517 $d0 = COPY %3(<2 x s32>) 518 RET_ReallyLR implicit $d0 519 520... 521--- 522name: test_v8i16_uge 523alignment: 4 524tracksRegLiveness: true 525registers: 526 - { id: 0, class: _ } 527 - { id: 1, class: _ } 528 - { id: 2, class: _ } 529 - { id: 3, class: _ } 530machineFunctionInfo: {} 531body: | 532 bb.1: 533 liveins: $q0, $q1 534 535 ; CHECK-LABEL: name: test_v8i16_uge 536 ; CHECK: liveins: $q0, $q1 537 ; CHECK-NEXT: {{ $}} 538 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 539 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1 540 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(uge), [[COPY]](<8 x s16>), [[COPY1]] 541 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>) 542 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<8 x s8>) 543 ; CHECK-NEXT: RET_ReallyLR implicit $d0 544 %0:_(<8 x s16>) = COPY $q0 545 %1:_(<8 x s16>) = COPY $q1 546 %2:_(<8 x s1>) = G_ICMP intpred(uge), %0(<8 x s16>), %1 547 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 548 $d0 = COPY %3(<8 x s8>) 549 RET_ReallyLR implicit $d0 550 551... 552--- 553name: test_v4i16_uge 554alignment: 4 555tracksRegLiveness: true 556registers: 557 - { id: 0, class: _ } 558 - { id: 1, class: _ } 559 - { id: 2, class: _ } 560 - { id: 3, class: _ } 561machineFunctionInfo: {} 562body: | 563 bb.1: 564 liveins: $d0, $d1 565 566 ; CHECK-LABEL: name: test_v4i16_uge 567 ; CHECK: liveins: $d0, $d1 568 ; CHECK-NEXT: {{ $}} 569 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 570 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1 571 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(uge), [[COPY]](<4 x s16>), [[COPY1]] 572 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<4 x s16>) 573 ; CHECK-NEXT: RET_ReallyLR implicit $d0 574 %0:_(<4 x s16>) = COPY $d0 575 %1:_(<4 x s16>) = COPY $d1 576 %2:_(<4 x s1>) = G_ICMP intpred(uge), %0(<4 x s16>), %1 577 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 578 $d0 = COPY %3(<4 x s16>) 579 RET_ReallyLR implicit $d0 580 581... 582--- 583name: test_v16i8_uge 584alignment: 4 585tracksRegLiveness: true 586registers: 587 - { id: 0, class: _ } 588 - { id: 1, class: _ } 589 - { id: 2, class: _ } 590 - { id: 3, class: _ } 591machineFunctionInfo: {} 592body: | 593 bb.1: 594 liveins: $q0, $q1 595 596 ; CHECK-LABEL: name: test_v16i8_uge 597 ; CHECK: liveins: $q0, $q1 598 ; CHECK-NEXT: {{ $}} 599 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 600 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 601 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(uge), [[COPY]](<16 x s8>), [[COPY1]] 602 ; CHECK-NEXT: $q0 = COPY [[ICMP]](<16 x s8>) 603 ; CHECK-NEXT: RET_ReallyLR implicit $q0 604 %0:_(<16 x s8>) = COPY $q0 605 %1:_(<16 x s8>) = COPY $q1 606 %2:_(<16 x s1>) = G_ICMP intpred(uge), %0(<16 x s8>), %1 607 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>) 608 $q0 = COPY %3(<16 x s8>) 609 RET_ReallyLR implicit $q0 610 611... 612--- 613name: test_v8i8_uge 614alignment: 4 615tracksRegLiveness: true 616registers: 617 - { id: 0, class: _ } 618 - { id: 1, class: _ } 619 - { id: 2, class: _ } 620 - { id: 3, class: _ } 621machineFunctionInfo: {} 622body: | 623 bb.1: 624 liveins: $d0, $d1 625 626 ; CHECK-LABEL: name: test_v8i8_uge 627 ; CHECK: liveins: $d0, $d1 628 ; CHECK-NEXT: {{ $}} 629 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 630 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 631 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(uge), [[COPY]](<8 x s8>), [[COPY1]] 632 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<8 x s8>) 633 ; CHECK-NEXT: RET_ReallyLR implicit $d0 634 %0:_(<8 x s8>) = COPY $d0 635 %1:_(<8 x s8>) = COPY $d1 636 %2:_(<8 x s1>) = G_ICMP intpred(uge), %0(<8 x s8>), %1 637 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 638 $d0 = COPY %3(<8 x s8>) 639 RET_ReallyLR implicit $d0 640 641... 642--- 643name: test_v2i64_ult 644alignment: 4 645tracksRegLiveness: true 646registers: 647 - { id: 0, class: _ } 648 - { id: 1, class: _ } 649 - { id: 2, class: _ } 650 - { id: 3, class: _ } 651machineFunctionInfo: {} 652body: | 653 bb.1: 654 liveins: $q0, $q1 655 656 ; CHECK-LABEL: name: test_v2i64_ult 657 ; CHECK: liveins: $q0, $q1 658 ; CHECK-NEXT: {{ $}} 659 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 660 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 661 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[COPY]](<2 x s64>), [[COPY1]] 662 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 663 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>) 664 ; CHECK-NEXT: RET_ReallyLR implicit $d0 665 %0:_(<2 x s64>) = COPY $q0 666 %1:_(<2 x s64>) = COPY $q1 667 %2:_(<2 x s1>) = G_ICMP intpred(ult), %0(<2 x s64>), %1 668 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 669 $d0 = COPY %3(<2 x s32>) 670 RET_ReallyLR implicit $d0 671 672... 673--- 674name: test_v4i32_ult 675alignment: 4 676tracksRegLiveness: true 677registers: 678 - { id: 0, class: _ } 679 - { id: 1, class: _ } 680 - { id: 2, class: _ } 681 - { id: 3, class: _ } 682machineFunctionInfo: {} 683body: | 684 bb.1: 685 liveins: $q0, $q1 686 687 ; CHECK-LABEL: name: test_v4i32_ult 688 ; CHECK: liveins: $q0, $q1 689 ; CHECK-NEXT: {{ $}} 690 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 691 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 692 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(ult), [[COPY]](<4 x s32>), [[COPY1]] 693 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 694 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>) 695 ; CHECK-NEXT: RET_ReallyLR implicit $d0 696 %0:_(<4 x s32>) = COPY $q0 697 %1:_(<4 x s32>) = COPY $q1 698 %2:_(<4 x s1>) = G_ICMP intpred(ult), %0(<4 x s32>), %1 699 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 700 $d0 = COPY %3(<4 x s16>) 701 RET_ReallyLR implicit $d0 702 703... 704--- 705name: test_v2i32_ult 706alignment: 4 707tracksRegLiveness: true 708registers: 709 - { id: 0, class: _ } 710 - { id: 1, class: _ } 711 - { id: 2, class: _ } 712 - { id: 3, class: _ } 713machineFunctionInfo: {} 714body: | 715 bb.1: 716 liveins: $d0, $d1 717 718 ; CHECK-LABEL: name: test_v2i32_ult 719 ; CHECK: liveins: $d0, $d1 720 ; CHECK-NEXT: {{ $}} 721 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 722 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 723 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(ult), [[COPY]](<2 x s32>), [[COPY1]] 724 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<2 x s32>) 725 ; CHECK-NEXT: RET_ReallyLR implicit $d0 726 %0:_(<2 x s32>) = COPY $d0 727 %1:_(<2 x s32>) = COPY $d1 728 %2:_(<2 x s1>) = G_ICMP intpred(ult), %0(<2 x s32>), %1 729 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 730 $d0 = COPY %3(<2 x s32>) 731 RET_ReallyLR implicit $d0 732 733... 734--- 735name: test_v8i16_ult 736alignment: 4 737tracksRegLiveness: true 738registers: 739 - { id: 0, class: _ } 740 - { id: 1, class: _ } 741 - { id: 2, class: _ } 742 - { id: 3, class: _ } 743machineFunctionInfo: {} 744body: | 745 bb.1: 746 liveins: $q0, $q1 747 748 ; CHECK-LABEL: name: test_v8i16_ult 749 ; CHECK: liveins: $q0, $q1 750 ; CHECK-NEXT: {{ $}} 751 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 752 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1 753 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(ult), [[COPY]](<8 x s16>), [[COPY1]] 754 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>) 755 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<8 x s8>) 756 ; CHECK-NEXT: RET_ReallyLR implicit $d0 757 %0:_(<8 x s16>) = COPY $q0 758 %1:_(<8 x s16>) = COPY $q1 759 %2:_(<8 x s1>) = G_ICMP intpred(ult), %0(<8 x s16>), %1 760 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 761 $d0 = COPY %3(<8 x s8>) 762 RET_ReallyLR implicit $d0 763 764... 765--- 766name: test_v4i16_ult 767alignment: 4 768tracksRegLiveness: true 769registers: 770 - { id: 0, class: _ } 771 - { id: 1, class: _ } 772 - { id: 2, class: _ } 773 - { id: 3, class: _ } 774machineFunctionInfo: {} 775body: | 776 bb.1: 777 liveins: $d0, $d1 778 779 ; CHECK-LABEL: name: test_v4i16_ult 780 ; CHECK: liveins: $d0, $d1 781 ; CHECK-NEXT: {{ $}} 782 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 783 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1 784 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(ult), [[COPY]](<4 x s16>), [[COPY1]] 785 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<4 x s16>) 786 ; CHECK-NEXT: RET_ReallyLR implicit $d0 787 %0:_(<4 x s16>) = COPY $d0 788 %1:_(<4 x s16>) = COPY $d1 789 %2:_(<4 x s1>) = G_ICMP intpred(ult), %0(<4 x s16>), %1 790 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 791 $d0 = COPY %3(<4 x s16>) 792 RET_ReallyLR implicit $d0 793 794... 795--- 796name: test_v16i8_ult 797alignment: 4 798tracksRegLiveness: true 799registers: 800 - { id: 0, class: _ } 801 - { id: 1, class: _ } 802 - { id: 2, class: _ } 803 - { id: 3, class: _ } 804machineFunctionInfo: {} 805body: | 806 bb.1: 807 liveins: $q0, $q1 808 809 ; CHECK-LABEL: name: test_v16i8_ult 810 ; CHECK: liveins: $q0, $q1 811 ; CHECK-NEXT: {{ $}} 812 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 813 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 814 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(ult), [[COPY]](<16 x s8>), [[COPY1]] 815 ; CHECK-NEXT: $q0 = COPY [[ICMP]](<16 x s8>) 816 ; CHECK-NEXT: RET_ReallyLR implicit $q0 817 %0:_(<16 x s8>) = COPY $q0 818 %1:_(<16 x s8>) = COPY $q1 819 %2:_(<16 x s1>) = G_ICMP intpred(ult), %0(<16 x s8>), %1 820 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>) 821 $q0 = COPY %3(<16 x s8>) 822 RET_ReallyLR implicit $q0 823 824... 825--- 826name: test_v8i8_ult 827alignment: 4 828tracksRegLiveness: true 829registers: 830 - { id: 0, class: _ } 831 - { id: 1, class: _ } 832 - { id: 2, class: _ } 833 - { id: 3, class: _ } 834machineFunctionInfo: {} 835body: | 836 bb.1: 837 liveins: $d0, $d1 838 839 ; CHECK-LABEL: name: test_v8i8_ult 840 ; CHECK: liveins: $d0, $d1 841 ; CHECK-NEXT: {{ $}} 842 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 843 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 844 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(ult), [[COPY]](<8 x s8>), [[COPY1]] 845 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<8 x s8>) 846 ; CHECK-NEXT: RET_ReallyLR implicit $d0 847 %0:_(<8 x s8>) = COPY $d0 848 %1:_(<8 x s8>) = COPY $d1 849 %2:_(<8 x s1>) = G_ICMP intpred(ult), %0(<8 x s8>), %1 850 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 851 $d0 = COPY %3(<8 x s8>) 852 RET_ReallyLR implicit $d0 853 854... 855--- 856name: test_v2i64_ule 857alignment: 4 858tracksRegLiveness: true 859registers: 860 - { id: 0, class: _ } 861 - { id: 1, class: _ } 862 - { id: 2, class: _ } 863 - { id: 3, class: _ } 864machineFunctionInfo: {} 865body: | 866 bb.1: 867 liveins: $q0, $q1 868 869 ; CHECK-LABEL: name: test_v2i64_ule 870 ; CHECK: liveins: $q0, $q1 871 ; CHECK-NEXT: {{ $}} 872 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 873 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 874 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ule), [[COPY]](<2 x s64>), [[COPY1]] 875 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 876 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>) 877 ; CHECK-NEXT: RET_ReallyLR implicit $d0 878 %0:_(<2 x s64>) = COPY $q0 879 %1:_(<2 x s64>) = COPY $q1 880 %2:_(<2 x s1>) = G_ICMP intpred(ule), %0(<2 x s64>), %1 881 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 882 $d0 = COPY %3(<2 x s32>) 883 RET_ReallyLR implicit $d0 884 885... 886--- 887name: test_v4i32_ule 888alignment: 4 889tracksRegLiveness: true 890registers: 891 - { id: 0, class: _ } 892 - { id: 1, class: _ } 893 - { id: 2, class: _ } 894 - { id: 3, class: _ } 895machineFunctionInfo: {} 896body: | 897 bb.1: 898 liveins: $q0, $q1 899 900 ; CHECK-LABEL: name: test_v4i32_ule 901 ; CHECK: liveins: $q0, $q1 902 ; CHECK-NEXT: {{ $}} 903 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 904 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 905 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(ule), [[COPY]](<4 x s32>), [[COPY1]] 906 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 907 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>) 908 ; CHECK-NEXT: RET_ReallyLR implicit $d0 909 %0:_(<4 x s32>) = COPY $q0 910 %1:_(<4 x s32>) = COPY $q1 911 %2:_(<4 x s1>) = G_ICMP intpred(ule), %0(<4 x s32>), %1 912 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 913 $d0 = COPY %3(<4 x s16>) 914 RET_ReallyLR implicit $d0 915 916... 917--- 918name: test_v2i32_ule 919alignment: 4 920tracksRegLiveness: true 921registers: 922 - { id: 0, class: _ } 923 - { id: 1, class: _ } 924 - { id: 2, class: _ } 925 - { id: 3, class: _ } 926machineFunctionInfo: {} 927body: | 928 bb.1: 929 liveins: $d0, $d1 930 931 ; CHECK-LABEL: name: test_v2i32_ule 932 ; CHECK: liveins: $d0, $d1 933 ; CHECK-NEXT: {{ $}} 934 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 935 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 936 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(ule), [[COPY]](<2 x s32>), [[COPY1]] 937 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<2 x s32>) 938 ; CHECK-NEXT: RET_ReallyLR implicit $d0 939 %0:_(<2 x s32>) = COPY $d0 940 %1:_(<2 x s32>) = COPY $d1 941 %2:_(<2 x s1>) = G_ICMP intpred(ule), %0(<2 x s32>), %1 942 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 943 $d0 = COPY %3(<2 x s32>) 944 RET_ReallyLR implicit $d0 945 946... 947--- 948name: test_v8i16_ule 949alignment: 4 950tracksRegLiveness: true 951registers: 952 - { id: 0, class: _ } 953 - { id: 1, class: _ } 954 - { id: 2, class: _ } 955 - { id: 3, class: _ } 956machineFunctionInfo: {} 957body: | 958 bb.1: 959 liveins: $q0, $q1 960 961 ; CHECK-LABEL: name: test_v8i16_ule 962 ; CHECK: liveins: $q0, $q1 963 ; CHECK-NEXT: {{ $}} 964 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 965 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1 966 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(ule), [[COPY]](<8 x s16>), [[COPY1]] 967 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>) 968 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<8 x s8>) 969 ; CHECK-NEXT: RET_ReallyLR implicit $d0 970 %0:_(<8 x s16>) = COPY $q0 971 %1:_(<8 x s16>) = COPY $q1 972 %2:_(<8 x s1>) = G_ICMP intpred(ule), %0(<8 x s16>), %1 973 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 974 $d0 = COPY %3(<8 x s8>) 975 RET_ReallyLR implicit $d0 976 977... 978--- 979name: test_v4i16_ule 980alignment: 4 981tracksRegLiveness: true 982registers: 983 - { id: 0, class: _ } 984 - { id: 1, class: _ } 985 - { id: 2, class: _ } 986 - { id: 3, class: _ } 987machineFunctionInfo: {} 988body: | 989 bb.1: 990 liveins: $d0, $d1 991 992 ; CHECK-LABEL: name: test_v4i16_ule 993 ; CHECK: liveins: $d0, $d1 994 ; CHECK-NEXT: {{ $}} 995 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 996 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1 997 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(ule), [[COPY]](<4 x s16>), [[COPY1]] 998 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<4 x s16>) 999 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1000 %0:_(<4 x s16>) = COPY $d0 1001 %1:_(<4 x s16>) = COPY $d1 1002 %2:_(<4 x s1>) = G_ICMP intpred(ule), %0(<4 x s16>), %1 1003 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 1004 $d0 = COPY %3(<4 x s16>) 1005 RET_ReallyLR implicit $d0 1006 1007... 1008--- 1009name: test_v16i8_ule 1010alignment: 4 1011tracksRegLiveness: true 1012registers: 1013 - { id: 0, class: _ } 1014 - { id: 1, class: _ } 1015 - { id: 2, class: _ } 1016 - { id: 3, class: _ } 1017machineFunctionInfo: {} 1018body: | 1019 bb.1: 1020 liveins: $q0, $q1 1021 1022 ; CHECK-LABEL: name: test_v16i8_ule 1023 ; CHECK: liveins: $q0, $q1 1024 ; CHECK-NEXT: {{ $}} 1025 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 1026 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 1027 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(ule), [[COPY]](<16 x s8>), [[COPY1]] 1028 ; CHECK-NEXT: $q0 = COPY [[ICMP]](<16 x s8>) 1029 ; CHECK-NEXT: RET_ReallyLR implicit $q0 1030 %0:_(<16 x s8>) = COPY $q0 1031 %1:_(<16 x s8>) = COPY $q1 1032 %2:_(<16 x s1>) = G_ICMP intpred(ule), %0(<16 x s8>), %1 1033 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>) 1034 $q0 = COPY %3(<16 x s8>) 1035 RET_ReallyLR implicit $q0 1036 1037... 1038--- 1039name: test_v8i8_ule 1040alignment: 4 1041tracksRegLiveness: true 1042registers: 1043 - { id: 0, class: _ } 1044 - { id: 1, class: _ } 1045 - { id: 2, class: _ } 1046 - { id: 3, class: _ } 1047machineFunctionInfo: {} 1048body: | 1049 bb.1: 1050 liveins: $d0, $d1 1051 1052 ; CHECK-LABEL: name: test_v8i8_ule 1053 ; CHECK: liveins: $d0, $d1 1054 ; CHECK-NEXT: {{ $}} 1055 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 1056 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 1057 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(ule), [[COPY]](<8 x s8>), [[COPY1]] 1058 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<8 x s8>) 1059 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1060 %0:_(<8 x s8>) = COPY $d0 1061 %1:_(<8 x s8>) = COPY $d1 1062 %2:_(<8 x s1>) = G_ICMP intpred(ule), %0(<8 x s8>), %1 1063 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 1064 $d0 = COPY %3(<8 x s8>) 1065 RET_ReallyLR implicit $d0 1066 1067... 1068--- 1069name: test_v2i64_sgt 1070alignment: 4 1071tracksRegLiveness: true 1072registers: 1073 - { id: 0, class: _ } 1074 - { id: 1, class: _ } 1075 - { id: 2, class: _ } 1076 - { id: 3, class: _ } 1077machineFunctionInfo: {} 1078body: | 1079 bb.1: 1080 liveins: $q0, $q1 1081 1082 ; CHECK-LABEL: name: test_v2i64_sgt 1083 ; CHECK: liveins: $q0, $q1 1084 ; CHECK-NEXT: {{ $}} 1085 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 1086 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 1087 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[COPY]](<2 x s64>), [[COPY1]] 1088 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 1089 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>) 1090 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1091 %0:_(<2 x s64>) = COPY $q0 1092 %1:_(<2 x s64>) = COPY $q1 1093 %2:_(<2 x s1>) = G_ICMP intpred(sgt), %0(<2 x s64>), %1 1094 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 1095 $d0 = COPY %3(<2 x s32>) 1096 RET_ReallyLR implicit $d0 1097 1098... 1099--- 1100name: test_v4i32_sgt 1101alignment: 4 1102tracksRegLiveness: true 1103registers: 1104 - { id: 0, class: _ } 1105 - { id: 1, class: _ } 1106 - { id: 2, class: _ } 1107 - { id: 3, class: _ } 1108machineFunctionInfo: {} 1109body: | 1110 bb.1: 1111 liveins: $q0, $q1 1112 1113 ; CHECK-LABEL: name: test_v4i32_sgt 1114 ; CHECK: liveins: $q0, $q1 1115 ; CHECK-NEXT: {{ $}} 1116 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 1117 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 1118 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(sgt), [[COPY]](<4 x s32>), [[COPY1]] 1119 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 1120 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>) 1121 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1122 %0:_(<4 x s32>) = COPY $q0 1123 %1:_(<4 x s32>) = COPY $q1 1124 %2:_(<4 x s1>) = G_ICMP intpred(sgt), %0(<4 x s32>), %1 1125 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 1126 $d0 = COPY %3(<4 x s16>) 1127 RET_ReallyLR implicit $d0 1128 1129... 1130--- 1131name: test_v2i32_sgt 1132alignment: 4 1133tracksRegLiveness: true 1134registers: 1135 - { id: 0, class: _ } 1136 - { id: 1, class: _ } 1137 - { id: 2, class: _ } 1138 - { id: 3, class: _ } 1139machineFunctionInfo: {} 1140body: | 1141 bb.1: 1142 liveins: $d0, $d1 1143 1144 ; CHECK-LABEL: name: test_v2i32_sgt 1145 ; CHECK: liveins: $d0, $d1 1146 ; CHECK-NEXT: {{ $}} 1147 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 1148 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 1149 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sgt), [[COPY]](<2 x s32>), [[COPY1]] 1150 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<2 x s32>) 1151 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1152 %0:_(<2 x s32>) = COPY $d0 1153 %1:_(<2 x s32>) = COPY $d1 1154 %2:_(<2 x s1>) = G_ICMP intpred(sgt), %0(<2 x s32>), %1 1155 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 1156 $d0 = COPY %3(<2 x s32>) 1157 RET_ReallyLR implicit $d0 1158 1159... 1160--- 1161name: test_v8i16_sgt 1162alignment: 4 1163tracksRegLiveness: true 1164registers: 1165 - { id: 0, class: _ } 1166 - { id: 1, class: _ } 1167 - { id: 2, class: _ } 1168 - { id: 3, class: _ } 1169machineFunctionInfo: {} 1170body: | 1171 bb.1: 1172 liveins: $q0, $q1 1173 1174 ; CHECK-LABEL: name: test_v8i16_sgt 1175 ; CHECK: liveins: $q0, $q1 1176 ; CHECK-NEXT: {{ $}} 1177 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 1178 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1 1179 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(sgt), [[COPY]](<8 x s16>), [[COPY1]] 1180 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>) 1181 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<8 x s8>) 1182 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1183 %0:_(<8 x s16>) = COPY $q0 1184 %1:_(<8 x s16>) = COPY $q1 1185 %2:_(<8 x s1>) = G_ICMP intpred(sgt), %0(<8 x s16>), %1 1186 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 1187 $d0 = COPY %3(<8 x s8>) 1188 RET_ReallyLR implicit $d0 1189 1190... 1191--- 1192name: test_v4i16_sgt 1193alignment: 4 1194tracksRegLiveness: true 1195registers: 1196 - { id: 0, class: _ } 1197 - { id: 1, class: _ } 1198 - { id: 2, class: _ } 1199 - { id: 3, class: _ } 1200machineFunctionInfo: {} 1201body: | 1202 bb.1: 1203 liveins: $d0, $d1 1204 1205 ; CHECK-LABEL: name: test_v4i16_sgt 1206 ; CHECK: liveins: $d0, $d1 1207 ; CHECK-NEXT: {{ $}} 1208 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 1209 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1 1210 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(sgt), [[COPY]](<4 x s16>), [[COPY1]] 1211 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<4 x s16>) 1212 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1213 %0:_(<4 x s16>) = COPY $d0 1214 %1:_(<4 x s16>) = COPY $d1 1215 %2:_(<4 x s1>) = G_ICMP intpred(sgt), %0(<4 x s16>), %1 1216 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 1217 $d0 = COPY %3(<4 x s16>) 1218 RET_ReallyLR implicit $d0 1219 1220... 1221--- 1222name: test_v16i8_sgt 1223alignment: 4 1224tracksRegLiveness: true 1225registers: 1226 - { id: 0, class: _ } 1227 - { id: 1, class: _ } 1228 - { id: 2, class: _ } 1229 - { id: 3, class: _ } 1230machineFunctionInfo: {} 1231body: | 1232 bb.1: 1233 liveins: $q0, $q1 1234 1235 ; CHECK-LABEL: name: test_v16i8_sgt 1236 ; CHECK: liveins: $q0, $q1 1237 ; CHECK-NEXT: {{ $}} 1238 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 1239 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 1240 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sgt), [[COPY]](<16 x s8>), [[COPY1]] 1241 ; CHECK-NEXT: $q0 = COPY [[ICMP]](<16 x s8>) 1242 ; CHECK-NEXT: RET_ReallyLR implicit $q0 1243 %0:_(<16 x s8>) = COPY $q0 1244 %1:_(<16 x s8>) = COPY $q1 1245 %2:_(<16 x s1>) = G_ICMP intpred(sgt), %0(<16 x s8>), %1 1246 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>) 1247 $q0 = COPY %3(<16 x s8>) 1248 RET_ReallyLR implicit $q0 1249 1250... 1251--- 1252name: test_v8i8_sgt 1253alignment: 4 1254tracksRegLiveness: true 1255registers: 1256 - { id: 0, class: _ } 1257 - { id: 1, class: _ } 1258 - { id: 2, class: _ } 1259 - { id: 3, class: _ } 1260machineFunctionInfo: {} 1261body: | 1262 bb.1: 1263 liveins: $d0, $d1 1264 1265 ; CHECK-LABEL: name: test_v8i8_sgt 1266 ; CHECK: liveins: $d0, $d1 1267 ; CHECK-NEXT: {{ $}} 1268 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 1269 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 1270 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(sgt), [[COPY]](<8 x s8>), [[COPY1]] 1271 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<8 x s8>) 1272 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1273 %0:_(<8 x s8>) = COPY $d0 1274 %1:_(<8 x s8>) = COPY $d1 1275 %2:_(<8 x s1>) = G_ICMP intpred(sgt), %0(<8 x s8>), %1 1276 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 1277 $d0 = COPY %3(<8 x s8>) 1278 RET_ReallyLR implicit $d0 1279 1280... 1281--- 1282name: test_v2i64_sge 1283alignment: 4 1284tracksRegLiveness: true 1285registers: 1286 - { id: 0, class: _ } 1287 - { id: 1, class: _ } 1288 - { id: 2, class: _ } 1289 - { id: 3, class: _ } 1290machineFunctionInfo: {} 1291body: | 1292 bb.1: 1293 liveins: $q0, $q1 1294 1295 ; CHECK-LABEL: name: test_v2i64_sge 1296 ; CHECK: liveins: $q0, $q1 1297 ; CHECK-NEXT: {{ $}} 1298 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 1299 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 1300 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sge), [[COPY]](<2 x s64>), [[COPY1]] 1301 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 1302 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>) 1303 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1304 %0:_(<2 x s64>) = COPY $q0 1305 %1:_(<2 x s64>) = COPY $q1 1306 %2:_(<2 x s1>) = G_ICMP intpred(sge), %0(<2 x s64>), %1 1307 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 1308 $d0 = COPY %3(<2 x s32>) 1309 RET_ReallyLR implicit $d0 1310 1311... 1312--- 1313name: test_v4i32_sge 1314alignment: 4 1315tracksRegLiveness: true 1316registers: 1317 - { id: 0, class: _ } 1318 - { id: 1, class: _ } 1319 - { id: 2, class: _ } 1320 - { id: 3, class: _ } 1321machineFunctionInfo: {} 1322body: | 1323 bb.1: 1324 liveins: $q0, $q1 1325 1326 ; CHECK-LABEL: name: test_v4i32_sge 1327 ; CHECK: liveins: $q0, $q1 1328 ; CHECK-NEXT: {{ $}} 1329 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 1330 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 1331 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(sge), [[COPY]](<4 x s32>), [[COPY1]] 1332 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 1333 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>) 1334 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1335 %0:_(<4 x s32>) = COPY $q0 1336 %1:_(<4 x s32>) = COPY $q1 1337 %2:_(<4 x s1>) = G_ICMP intpred(sge), %0(<4 x s32>), %1 1338 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 1339 $d0 = COPY %3(<4 x s16>) 1340 RET_ReallyLR implicit $d0 1341 1342... 1343--- 1344name: test_v2i32_sge 1345alignment: 4 1346tracksRegLiveness: true 1347registers: 1348 - { id: 0, class: _ } 1349 - { id: 1, class: _ } 1350 - { id: 2, class: _ } 1351 - { id: 3, class: _ } 1352machineFunctionInfo: {} 1353body: | 1354 bb.1: 1355 liveins: $d0, $d1 1356 1357 ; CHECK-LABEL: name: test_v2i32_sge 1358 ; CHECK: liveins: $d0, $d1 1359 ; CHECK-NEXT: {{ $}} 1360 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 1361 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 1362 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sge), [[COPY]](<2 x s32>), [[COPY1]] 1363 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<2 x s32>) 1364 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1365 %0:_(<2 x s32>) = COPY $d0 1366 %1:_(<2 x s32>) = COPY $d1 1367 %2:_(<2 x s1>) = G_ICMP intpred(sge), %0(<2 x s32>), %1 1368 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 1369 $d0 = COPY %3(<2 x s32>) 1370 RET_ReallyLR implicit $d0 1371 1372... 1373--- 1374name: test_v8i16_sge 1375alignment: 4 1376tracksRegLiveness: true 1377registers: 1378 - { id: 0, class: _ } 1379 - { id: 1, class: _ } 1380 - { id: 2, class: _ } 1381 - { id: 3, class: _ } 1382machineFunctionInfo: {} 1383body: | 1384 bb.1: 1385 liveins: $q0, $q1 1386 1387 ; CHECK-LABEL: name: test_v8i16_sge 1388 ; CHECK: liveins: $q0, $q1 1389 ; CHECK-NEXT: {{ $}} 1390 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 1391 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1 1392 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(sge), [[COPY]](<8 x s16>), [[COPY1]] 1393 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>) 1394 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<8 x s8>) 1395 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1396 %0:_(<8 x s16>) = COPY $q0 1397 %1:_(<8 x s16>) = COPY $q1 1398 %2:_(<8 x s1>) = G_ICMP intpred(sge), %0(<8 x s16>), %1 1399 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 1400 $d0 = COPY %3(<8 x s8>) 1401 RET_ReallyLR implicit $d0 1402 1403... 1404--- 1405name: test_v4i16_sge 1406alignment: 4 1407tracksRegLiveness: true 1408registers: 1409 - { id: 0, class: _ } 1410 - { id: 1, class: _ } 1411 - { id: 2, class: _ } 1412 - { id: 3, class: _ } 1413machineFunctionInfo: {} 1414body: | 1415 bb.1: 1416 liveins: $d0, $d1 1417 1418 ; CHECK-LABEL: name: test_v4i16_sge 1419 ; CHECK: liveins: $d0, $d1 1420 ; CHECK-NEXT: {{ $}} 1421 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 1422 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1 1423 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(sge), [[COPY]](<4 x s16>), [[COPY1]] 1424 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<4 x s16>) 1425 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1426 %0:_(<4 x s16>) = COPY $d0 1427 %1:_(<4 x s16>) = COPY $d1 1428 %2:_(<4 x s1>) = G_ICMP intpred(sge), %0(<4 x s16>), %1 1429 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 1430 $d0 = COPY %3(<4 x s16>) 1431 RET_ReallyLR implicit $d0 1432 1433... 1434--- 1435name: test_v16i8_sge 1436alignment: 4 1437tracksRegLiveness: true 1438registers: 1439 - { id: 0, class: _ } 1440 - { id: 1, class: _ } 1441 - { id: 2, class: _ } 1442 - { id: 3, class: _ } 1443machineFunctionInfo: {} 1444body: | 1445 bb.1: 1446 liveins: $q0, $q1 1447 1448 ; CHECK-LABEL: name: test_v16i8_sge 1449 ; CHECK: liveins: $q0, $q1 1450 ; CHECK-NEXT: {{ $}} 1451 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 1452 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 1453 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sge), [[COPY]](<16 x s8>), [[COPY1]] 1454 ; CHECK-NEXT: $q0 = COPY [[ICMP]](<16 x s8>) 1455 ; CHECK-NEXT: RET_ReallyLR implicit $q0 1456 %0:_(<16 x s8>) = COPY $q0 1457 %1:_(<16 x s8>) = COPY $q1 1458 %2:_(<16 x s1>) = G_ICMP intpred(sge), %0(<16 x s8>), %1 1459 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>) 1460 $q0 = COPY %3(<16 x s8>) 1461 RET_ReallyLR implicit $q0 1462 1463... 1464--- 1465name: test_v8i8_sge 1466alignment: 4 1467tracksRegLiveness: true 1468registers: 1469 - { id: 0, class: _ } 1470 - { id: 1, class: _ } 1471 - { id: 2, class: _ } 1472 - { id: 3, class: _ } 1473machineFunctionInfo: {} 1474body: | 1475 bb.1: 1476 liveins: $d0, $d1 1477 1478 ; CHECK-LABEL: name: test_v8i8_sge 1479 ; CHECK: liveins: $d0, $d1 1480 ; CHECK-NEXT: {{ $}} 1481 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 1482 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 1483 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(sge), [[COPY]](<8 x s8>), [[COPY1]] 1484 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<8 x s8>) 1485 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1486 %0:_(<8 x s8>) = COPY $d0 1487 %1:_(<8 x s8>) = COPY $d1 1488 %2:_(<8 x s1>) = G_ICMP intpred(sge), %0(<8 x s8>), %1 1489 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 1490 $d0 = COPY %3(<8 x s8>) 1491 RET_ReallyLR implicit $d0 1492 1493... 1494--- 1495name: test_v2i64_slt 1496alignment: 4 1497tracksRegLiveness: true 1498registers: 1499 - { id: 0, class: _ } 1500 - { id: 1, class: _ } 1501 - { id: 2, class: _ } 1502 - { id: 3, class: _ } 1503machineFunctionInfo: {} 1504body: | 1505 bb.1: 1506 liveins: $q0, $q1 1507 1508 ; CHECK-LABEL: name: test_v2i64_slt 1509 ; CHECK: liveins: $q0, $q1 1510 ; CHECK-NEXT: {{ $}} 1511 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 1512 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 1513 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[COPY]](<2 x s64>), [[COPY1]] 1514 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 1515 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>) 1516 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1517 %0:_(<2 x s64>) = COPY $q0 1518 %1:_(<2 x s64>) = COPY $q1 1519 %2:_(<2 x s1>) = G_ICMP intpred(slt), %0(<2 x s64>), %1 1520 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 1521 $d0 = COPY %3(<2 x s32>) 1522 RET_ReallyLR implicit $d0 1523 1524... 1525--- 1526name: test_v4i32_slt 1527alignment: 4 1528tracksRegLiveness: true 1529registers: 1530 - { id: 0, class: _ } 1531 - { id: 1, class: _ } 1532 - { id: 2, class: _ } 1533 - { id: 3, class: _ } 1534machineFunctionInfo: {} 1535body: | 1536 bb.1: 1537 liveins: $q0, $q1 1538 1539 ; CHECK-LABEL: name: test_v4i32_slt 1540 ; CHECK: liveins: $q0, $q1 1541 ; CHECK-NEXT: {{ $}} 1542 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 1543 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 1544 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(slt), [[COPY]](<4 x s32>), [[COPY1]] 1545 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 1546 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>) 1547 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1548 %0:_(<4 x s32>) = COPY $q0 1549 %1:_(<4 x s32>) = COPY $q1 1550 %2:_(<4 x s1>) = G_ICMP intpred(slt), %0(<4 x s32>), %1 1551 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 1552 $d0 = COPY %3(<4 x s16>) 1553 RET_ReallyLR implicit $d0 1554 1555... 1556--- 1557name: test_v2i32_slt 1558alignment: 4 1559tracksRegLiveness: true 1560registers: 1561 - { id: 0, class: _ } 1562 - { id: 1, class: _ } 1563 - { id: 2, class: _ } 1564 - { id: 3, class: _ } 1565machineFunctionInfo: {} 1566body: | 1567 bb.1: 1568 liveins: $d0, $d1 1569 1570 ; CHECK-LABEL: name: test_v2i32_slt 1571 ; CHECK: liveins: $d0, $d1 1572 ; CHECK-NEXT: {{ $}} 1573 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 1574 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 1575 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(slt), [[COPY]](<2 x s32>), [[COPY1]] 1576 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<2 x s32>) 1577 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1578 %0:_(<2 x s32>) = COPY $d0 1579 %1:_(<2 x s32>) = COPY $d1 1580 %2:_(<2 x s1>) = G_ICMP intpred(slt), %0(<2 x s32>), %1 1581 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 1582 $d0 = COPY %3(<2 x s32>) 1583 RET_ReallyLR implicit $d0 1584 1585... 1586--- 1587name: test_v8i16_slt 1588alignment: 4 1589tracksRegLiveness: true 1590registers: 1591 - { id: 0, class: _ } 1592 - { id: 1, class: _ } 1593 - { id: 2, class: _ } 1594 - { id: 3, class: _ } 1595machineFunctionInfo: {} 1596body: | 1597 bb.1: 1598 liveins: $q0, $q1 1599 1600 ; CHECK-LABEL: name: test_v8i16_slt 1601 ; CHECK: liveins: $q0, $q1 1602 ; CHECK-NEXT: {{ $}} 1603 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 1604 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1 1605 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(slt), [[COPY]](<8 x s16>), [[COPY1]] 1606 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>) 1607 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<8 x s8>) 1608 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1609 %0:_(<8 x s16>) = COPY $q0 1610 %1:_(<8 x s16>) = COPY $q1 1611 %2:_(<8 x s1>) = G_ICMP intpred(slt), %0(<8 x s16>), %1 1612 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 1613 $d0 = COPY %3(<8 x s8>) 1614 RET_ReallyLR implicit $d0 1615 1616... 1617--- 1618name: test_v4i16_slt 1619alignment: 4 1620tracksRegLiveness: true 1621registers: 1622 - { id: 0, class: _ } 1623 - { id: 1, class: _ } 1624 - { id: 2, class: _ } 1625 - { id: 3, class: _ } 1626machineFunctionInfo: {} 1627body: | 1628 bb.1: 1629 liveins: $d0, $d1 1630 1631 ; CHECK-LABEL: name: test_v4i16_slt 1632 ; CHECK: liveins: $d0, $d1 1633 ; CHECK-NEXT: {{ $}} 1634 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 1635 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1 1636 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(slt), [[COPY]](<4 x s16>), [[COPY1]] 1637 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<4 x s16>) 1638 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1639 %0:_(<4 x s16>) = COPY $d0 1640 %1:_(<4 x s16>) = COPY $d1 1641 %2:_(<4 x s1>) = G_ICMP intpred(slt), %0(<4 x s16>), %1 1642 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 1643 $d0 = COPY %3(<4 x s16>) 1644 RET_ReallyLR implicit $d0 1645 1646... 1647--- 1648name: test_v16i8_slt 1649alignment: 4 1650tracksRegLiveness: true 1651registers: 1652 - { id: 0, class: _ } 1653 - { id: 1, class: _ } 1654 - { id: 2, class: _ } 1655 - { id: 3, class: _ } 1656machineFunctionInfo: {} 1657body: | 1658 bb.1: 1659 liveins: $q0, $q1 1660 1661 ; CHECK-LABEL: name: test_v16i8_slt 1662 ; CHECK: liveins: $q0, $q1 1663 ; CHECK-NEXT: {{ $}} 1664 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 1665 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 1666 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(slt), [[COPY]](<16 x s8>), [[COPY1]] 1667 ; CHECK-NEXT: $q0 = COPY [[ICMP]](<16 x s8>) 1668 ; CHECK-NEXT: RET_ReallyLR implicit $q0 1669 %0:_(<16 x s8>) = COPY $q0 1670 %1:_(<16 x s8>) = COPY $q1 1671 %2:_(<16 x s1>) = G_ICMP intpred(slt), %0(<16 x s8>), %1 1672 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>) 1673 $q0 = COPY %3(<16 x s8>) 1674 RET_ReallyLR implicit $q0 1675 1676... 1677--- 1678name: test_v8i8_slt 1679alignment: 4 1680tracksRegLiveness: true 1681registers: 1682 - { id: 0, class: _ } 1683 - { id: 1, class: _ } 1684 - { id: 2, class: _ } 1685 - { id: 3, class: _ } 1686machineFunctionInfo: {} 1687body: | 1688 bb.1: 1689 liveins: $d0, $d1 1690 1691 ; CHECK-LABEL: name: test_v8i8_slt 1692 ; CHECK: liveins: $d0, $d1 1693 ; CHECK-NEXT: {{ $}} 1694 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 1695 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 1696 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(slt), [[COPY]](<8 x s8>), [[COPY1]] 1697 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<8 x s8>) 1698 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1699 %0:_(<8 x s8>) = COPY $d0 1700 %1:_(<8 x s8>) = COPY $d1 1701 %2:_(<8 x s1>) = G_ICMP intpred(slt), %0(<8 x s8>), %1 1702 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 1703 $d0 = COPY %3(<8 x s8>) 1704 RET_ReallyLR implicit $d0 1705 1706... 1707--- 1708name: test_v2i64_sle 1709alignment: 4 1710tracksRegLiveness: true 1711registers: 1712 - { id: 0, class: _ } 1713 - { id: 1, class: _ } 1714 - { id: 2, class: _ } 1715 - { id: 3, class: _ } 1716machineFunctionInfo: {} 1717body: | 1718 bb.1: 1719 liveins: $q0, $q1 1720 1721 ; CHECK-LABEL: name: test_v2i64_sle 1722 ; CHECK: liveins: $q0, $q1 1723 ; CHECK-NEXT: {{ $}} 1724 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 1725 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 1726 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sle), [[COPY]](<2 x s64>), [[COPY1]] 1727 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 1728 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>) 1729 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1730 %0:_(<2 x s64>) = COPY $q0 1731 %1:_(<2 x s64>) = COPY $q1 1732 %2:_(<2 x s1>) = G_ICMP intpred(sle), %0(<2 x s64>), %1 1733 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 1734 $d0 = COPY %3(<2 x s32>) 1735 RET_ReallyLR implicit $d0 1736 1737... 1738--- 1739name: test_v4i32_sle 1740alignment: 4 1741tracksRegLiveness: true 1742registers: 1743 - { id: 0, class: _ } 1744 - { id: 1, class: _ } 1745 - { id: 2, class: _ } 1746 - { id: 3, class: _ } 1747machineFunctionInfo: {} 1748body: | 1749 bb.1: 1750 liveins: $q0, $q1 1751 1752 ; CHECK-LABEL: name: test_v4i32_sle 1753 ; CHECK: liveins: $q0, $q1 1754 ; CHECK-NEXT: {{ $}} 1755 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 1756 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 1757 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(sle), [[COPY]](<4 x s32>), [[COPY1]] 1758 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 1759 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>) 1760 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1761 %0:_(<4 x s32>) = COPY $q0 1762 %1:_(<4 x s32>) = COPY $q1 1763 %2:_(<4 x s1>) = G_ICMP intpred(sle), %0(<4 x s32>), %1 1764 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 1765 $d0 = COPY %3(<4 x s16>) 1766 RET_ReallyLR implicit $d0 1767 1768... 1769--- 1770name: test_v2i32_sle 1771alignment: 4 1772tracksRegLiveness: true 1773registers: 1774 - { id: 0, class: _ } 1775 - { id: 1, class: _ } 1776 - { id: 2, class: _ } 1777 - { id: 3, class: _ } 1778machineFunctionInfo: {} 1779body: | 1780 bb.1: 1781 liveins: $d0, $d1 1782 1783 ; CHECK-LABEL: name: test_v2i32_sle 1784 ; CHECK: liveins: $d0, $d1 1785 ; CHECK-NEXT: {{ $}} 1786 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 1787 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 1788 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(sle), [[COPY]](<2 x s32>), [[COPY1]] 1789 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<2 x s32>) 1790 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1791 %0:_(<2 x s32>) = COPY $d0 1792 %1:_(<2 x s32>) = COPY $d1 1793 %2:_(<2 x s1>) = G_ICMP intpred(sle), %0(<2 x s32>), %1 1794 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 1795 $d0 = COPY %3(<2 x s32>) 1796 RET_ReallyLR implicit $d0 1797 1798... 1799--- 1800name: test_v8i16_sle 1801alignment: 4 1802tracksRegLiveness: true 1803registers: 1804 - { id: 0, class: _ } 1805 - { id: 1, class: _ } 1806 - { id: 2, class: _ } 1807 - { id: 3, class: _ } 1808machineFunctionInfo: {} 1809body: | 1810 bb.1: 1811 liveins: $q0, $q1 1812 1813 ; CHECK-LABEL: name: test_v8i16_sle 1814 ; CHECK: liveins: $q0, $q1 1815 ; CHECK-NEXT: {{ $}} 1816 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0 1817 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1 1818 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s16>) = G_ICMP intpred(sle), [[COPY]](<8 x s16>), [[COPY1]] 1819 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[ICMP]](<8 x s16>) 1820 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<8 x s8>) 1821 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1822 %0:_(<8 x s16>) = COPY $q0 1823 %1:_(<8 x s16>) = COPY $q1 1824 %2:_(<8 x s1>) = G_ICMP intpred(sle), %0(<8 x s16>), %1 1825 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 1826 $d0 = COPY %3(<8 x s8>) 1827 RET_ReallyLR implicit $d0 1828 1829... 1830--- 1831name: test_v4i16_sle 1832alignment: 4 1833tracksRegLiveness: true 1834registers: 1835 - { id: 0, class: _ } 1836 - { id: 1, class: _ } 1837 - { id: 2, class: _ } 1838 - { id: 3, class: _ } 1839machineFunctionInfo: {} 1840body: | 1841 bb.1: 1842 liveins: $d0, $d1 1843 1844 ; CHECK-LABEL: name: test_v4i16_sle 1845 ; CHECK: liveins: $d0, $d1 1846 ; CHECK-NEXT: {{ $}} 1847 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0 1848 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1 1849 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(sle), [[COPY]](<4 x s16>), [[COPY1]] 1850 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<4 x s16>) 1851 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1852 %0:_(<4 x s16>) = COPY $d0 1853 %1:_(<4 x s16>) = COPY $d1 1854 %2:_(<4 x s1>) = G_ICMP intpred(sle), %0(<4 x s16>), %1 1855 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 1856 $d0 = COPY %3(<4 x s16>) 1857 RET_ReallyLR implicit $d0 1858 1859... 1860--- 1861name: test_v16i8_sle 1862alignment: 4 1863tracksRegLiveness: true 1864registers: 1865 - { id: 0, class: _ } 1866 - { id: 1, class: _ } 1867 - { id: 2, class: _ } 1868 - { id: 3, class: _ } 1869machineFunctionInfo: {} 1870body: | 1871 bb.1: 1872 liveins: $q0, $q1 1873 1874 ; CHECK-LABEL: name: test_v16i8_sle 1875 ; CHECK: liveins: $q0, $q1 1876 ; CHECK-NEXT: {{ $}} 1877 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0 1878 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1 1879 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(sle), [[COPY]](<16 x s8>), [[COPY1]] 1880 ; CHECK-NEXT: $q0 = COPY [[ICMP]](<16 x s8>) 1881 ; CHECK-NEXT: RET_ReallyLR implicit $q0 1882 %0:_(<16 x s8>) = COPY $q0 1883 %1:_(<16 x s8>) = COPY $q1 1884 %2:_(<16 x s1>) = G_ICMP intpred(sle), %0(<16 x s8>), %1 1885 %3:_(<16 x s8>) = G_ANYEXT %2(<16 x s1>) 1886 $q0 = COPY %3(<16 x s8>) 1887 RET_ReallyLR implicit $q0 1888 1889... 1890--- 1891name: test_v8i8_sle 1892alignment: 4 1893tracksRegLiveness: true 1894registers: 1895 - { id: 0, class: _ } 1896 - { id: 1, class: _ } 1897 - { id: 2, class: _ } 1898 - { id: 3, class: _ } 1899machineFunctionInfo: {} 1900body: | 1901 bb.1: 1902 liveins: $d0, $d1 1903 1904 ; CHECK-LABEL: name: test_v8i8_sle 1905 ; CHECK: liveins: $d0, $d1 1906 ; CHECK-NEXT: {{ $}} 1907 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0 1908 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1 1909 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(sle), [[COPY]](<8 x s8>), [[COPY1]] 1910 ; CHECK-NEXT: $d0 = COPY [[ICMP]](<8 x s8>) 1911 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1912 %0:_(<8 x s8>) = COPY $d0 1913 %1:_(<8 x s8>) = COPY $d1 1914 %2:_(<8 x s1>) = G_ICMP intpred(sle), %0(<8 x s8>), %1 1915 %3:_(<8 x s8>) = G_ANYEXT %2(<8 x s1>) 1916 $d0 = COPY %3(<8 x s8>) 1917 RET_ReallyLR implicit $d0 1918 1919... 1920--- 1921name: test_v2p0_eq 1922alignment: 4 1923tracksRegLiveness: true 1924registers: 1925 - { id: 0, class: _ } 1926 - { id: 1, class: _ } 1927 - { id: 2, class: _ } 1928 - { id: 3, class: _ } 1929machineFunctionInfo: {} 1930body: | 1931 bb.1: 1932 liveins: $q0, $q1 1933 1934 ; CHECK-LABEL: name: test_v2p0_eq 1935 ; CHECK: liveins: $q0, $q1 1936 ; CHECK-NEXT: {{ $}} 1937 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x p0>) = COPY $q0 1938 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x p0>) = COPY $q1 1939 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(eq), [[COPY]](<2 x p0>), [[COPY1]] 1940 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[ICMP]](<2 x s64>) 1941 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<2 x s32>) 1942 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1943 %0:_(<2 x p0>) = COPY $q0 1944 %1:_(<2 x p0>) = COPY $q1 1945 %2:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x p0>), %1 1946 %3:_(<2 x s32>) = G_ANYEXT %2(<2 x s1>) 1947 $d0 = COPY %3(<2 x s32>) 1948 RET_ReallyLR implicit $d0 1949 1950... 1951--- 1952name: icmp_8xs1 1953alignment: 4 1954tracksRegLiveness: true 1955liveins: 1956 - { reg: '$q0' } 1957 - { reg: '$q1' } 1958 - { reg: '$q2' } 1959 - { reg: '$q3' } 1960body: | 1961 bb.1: 1962 liveins: $q0, $q1, $q2, $q3 1963 1964 ; CHECK-LABEL: name: icmp_8xs1 1965 ; CHECK: liveins: $q0, $q1, $q2, $q3 1966 ; CHECK-NEXT: {{ $}} 1967 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 1968 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 1969 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2 1970 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q3 1971 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY]](<4 x s32>), [[COPY2]] 1972 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY1]](<4 x s32>), [[COPY3]] 1973 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 1974 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP1]](<4 x s32>) 1975 ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>) 1976 ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>) 1977 ; CHECK-NEXT: $d0 = COPY [[TRUNC2]](<8 x s8>) 1978 ; CHECK-NEXT: RET_ReallyLR implicit $d0 1979 %2:_(<4 x s32>) = COPY $q0 1980 %3:_(<4 x s32>) = COPY $q1 1981 %0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>) 1982 %4:_(<4 x s32>) = COPY $q2 1983 %5:_(<4 x s32>) = COPY $q3 1984 %1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>) 1985 %6:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s32>), %1 1986 %7:_(<8 x s8>) = G_ANYEXT %6(<8 x s1>) 1987 $d0 = COPY %7(<8 x s8>) 1988 RET_ReallyLR implicit $d0 1989... 1990--- 1991name: icmp_8xs32 1992alignment: 4 1993tracksRegLiveness: true 1994liveins: 1995 - { reg: '$q0' } 1996 - { reg: '$q1' } 1997 - { reg: '$q2' } 1998 - { reg: '$q3' } 1999body: | 2000 bb.1: 2001 liveins: $q0, $q1, $q2, $q3 2002 2003 ; CHECK-LABEL: name: icmp_8xs32 2004 ; CHECK: liveins: $q0, $q1, $q2, $q3 2005 ; CHECK-NEXT: {{ $}} 2006 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 2007 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 2008 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2 2009 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q3 2010 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY]](<4 x s32>), [[COPY2]] 2011 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s32>) = G_ICMP intpred(eq), [[COPY1]](<4 x s32>), [[COPY3]] 2012 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP]](<4 x s32>) 2013 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[ICMP1]](<4 x s32>) 2014 ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>) 2015 ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>) 2016 ; CHECK-NEXT: $d0 = COPY [[TRUNC2]](<8 x s8>) 2017 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2018 %2:_(<4 x s32>) = COPY $q0 2019 %3:_(<4 x s32>) = COPY $q1 2020 %0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>) 2021 %4:_(<4 x s32>) = COPY $q2 2022 %5:_(<4 x s32>) = COPY $q3 2023 %1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>) 2024 %6:_(<8 x s32>) = G_ICMP intpred(eq), %0(<8 x s32>), %1 2025 %7:_(<8 x s8>) = G_TRUNC %6(<8 x s32>) 2026 $d0 = COPY %7(<8 x s8>) 2027 RET_ReallyLR implicit $d0 2028... 2029--- 2030name: fcmp_8xs1 2031alignment: 4 2032tracksRegLiveness: true 2033liveins: 2034 - { reg: '$q0' } 2035 - { reg: '$q1' } 2036 - { reg: '$q2' } 2037 - { reg: '$q3' } 2038body: | 2039 bb.1: 2040 liveins: $q0, $q1, $q2, $q3 2041 2042 ; CHECK-LABEL: name: fcmp_8xs1 2043 ; CHECK: liveins: $q0, $q1, $q2, $q3 2044 ; CHECK-NEXT: {{ $}} 2045 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 2046 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 2047 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2 2048 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q3 2049 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(one), [[COPY]](<4 x s32>), [[COPY2]] 2050 ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(one), [[COPY1]](<4 x s32>), [[COPY3]] 2051 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP]](<4 x s32>) 2052 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP1]](<4 x s32>) 2053 ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>) 2054 ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>) 2055 ; CHECK-NEXT: $d0 = COPY [[TRUNC2]](<8 x s8>) 2056 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2057 %2:_(<4 x s32>) = COPY $q0 2058 %3:_(<4 x s32>) = COPY $q1 2059 %0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>) 2060 %4:_(<4 x s32>) = COPY $q2 2061 %5:_(<4 x s32>) = COPY $q3 2062 %1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>) 2063 %6:_(<8 x s1>) = G_FCMP floatpred(one), %0(<8 x s32>), %1 2064 %7:_(<8 x s8>) = G_ANYEXT %6(<8 x s1>) 2065 $d0 = COPY %7(<8 x s8>) 2066 RET_ReallyLR implicit $d0 2067... 2068--- 2069name: fcmp_8xs32 2070alignment: 4 2071tracksRegLiveness: true 2072liveins: 2073 - { reg: '$q0' } 2074 - { reg: '$q1' } 2075 - { reg: '$q2' } 2076 - { reg: '$q3' } 2077body: | 2078 bb.1: 2079 liveins: $q0, $q1, $q2, $q3 2080 2081 ; CHECK-LABEL: name: fcmp_8xs32 2082 ; CHECK: liveins: $q0, $q1, $q2, $q3 2083 ; CHECK-NEXT: {{ $}} 2084 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 2085 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 2086 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s32>) = COPY $q2 2087 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s32>) = COPY $q3 2088 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(oeq), [[COPY]](<4 x s32>), [[COPY2]] 2089 ; CHECK-NEXT: [[FCMP1:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(oeq), [[COPY1]](<4 x s32>), [[COPY3]] 2090 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP]](<4 x s32>) 2091 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP1]](<4 x s32>) 2092 ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s16>) = G_CONCAT_VECTORS [[TRUNC]](<4 x s16>), [[TRUNC1]](<4 x s16>) 2093 ; CHECK-NEXT: [[TRUNC2:%[0-9]+]]:_(<8 x s8>) = G_TRUNC [[CONCAT_VECTORS]](<8 x s16>) 2094 ; CHECK-NEXT: $d0 = COPY [[TRUNC2]](<8 x s8>) 2095 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2096 %2:_(<4 x s32>) = COPY $q0 2097 %3:_(<4 x s32>) = COPY $q1 2098 %0:_(<8 x s32>) = G_CONCAT_VECTORS %2(<4 x s32>), %3(<4 x s32>) 2099 %4:_(<4 x s32>) = COPY $q2 2100 %5:_(<4 x s32>) = COPY $q3 2101 %1:_(<8 x s32>) = G_CONCAT_VECTORS %4(<4 x s32>), %5(<4 x s32>) 2102 %6:_(<8 x s32>) = G_FCMP floatpred(oeq), %0(<8 x s32>), %1 2103 %7:_(<8 x s8>) = G_TRUNC %6(<8 x s32>) 2104 $d0 = COPY %7(<8 x s8>) 2105 RET_ReallyLR implicit $d0 2106... 2107--- 2108name: fcmp_v4s32 2109alignment: 4 2110tracksRegLiveness: true 2111registers: 2112 - { id: 0, class: _ } 2113 - { id: 1, class: _ } 2114 - { id: 2, class: _ } 2115 - { id: 3, class: _ } 2116machineFunctionInfo: {} 2117body: | 2118 bb.1: 2119 liveins: $q0, $q1 2120 2121 ; CHECK-LABEL: name: fcmp_v4s32 2122 ; CHECK: liveins: $q0, $q1 2123 ; CHECK-NEXT: {{ $}} 2124 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 2125 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s32>) = COPY $q1 2126 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:_(<4 x s32>) = G_FCMP floatpred(olt), [[COPY]](<4 x s32>), [[COPY1]] 2127 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<4 x s16>) = G_TRUNC [[FCMP]](<4 x s32>) 2128 ; CHECK-NEXT: $d0 = COPY [[TRUNC]](<4 x s16>) 2129 ; CHECK-NEXT: RET_ReallyLR implicit $d0 2130 %0:_(<4 x s32>) = COPY $q0 2131 %1:_(<4 x s32>) = COPY $q1 2132 %2:_(<4 x s1>) = G_FCMP floatpred(olt), %0(<4 x s32>), %1 2133 %3:_(<4 x s16>) = G_ANYEXT %2(<4 x s1>) 2134 $d0 = COPY %3(<4 x s16>) 2135 RET_ReallyLR implicit $d0 2136 2137... 2138