xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/legalize-phi-insertpt-decrement.mir (revision 1ee315ae7964c8433b772e0b5d667834994ba753)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -debugify-and-strip-all-safe -O0 -mtriple=aarch64-unknown-unknown -verify-machineinstrs -run-pass=legalizer %s -o - | FileCheck %s
3--- |
4  target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
5
6  define void @snork() {
7  bb:
8    br label %bb1
9
10  bb1:                                              ; preds = %bb3, %bb
11    %lsr.iv = phi ptr [ %scevgep, %bb3 ], [ undef, %bb ]
12    %tmp = phi i1 [ %tmp9, %bb3 ], [ undef, %bb ]
13    br i1 %tmp, label %bb10, label %bb3
14
15  bb3:                                              ; preds = %bb1
16    %tmp5 = getelementptr i16, ptr null, i64 2
17    %tmp6 = load i16, ptr %lsr.iv, align 2, !tbaa !0
18    %tmp7 = icmp eq i16 %tmp6, -1
19    %tmp8 = load i16, ptr %tmp5, align 2, !tbaa !0
20    %tmp9 = icmp eq i16 %tmp8, -1
21    %scevgep = getelementptr i16, ptr %lsr.iv, i64 2
22    br i1 %tmp7, label %bb10, label %bb1
23
24  bb10:                                             ; preds = %bb3, %bb1
25    ret void
26  }
27
28  !0 = !{!1, !1, i64 0}
29  !1 = !{!"short", !2, i64 0}
30  !2 = !{!"omnipotent char", !3, i64 0}
31  !3 = !{!"Simple C/C++ TBAA"}
32
33...
34---
35name:            snork
36alignment:       16
37tracksRegLiveness: true
38frameInfo:
39  maxAlignment:    1
40body:             |
41  ; CHECK-LABEL: name: snork
42  ; CHECK: bb.0.bb:
43  ; CHECK-NEXT:   successors: %bb.1(0x80000000)
44  ; CHECK-NEXT: {{  $}}
45  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
46  ; CHECK-NEXT:   [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[C]](s64)
47  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
48  ; CHECK-NEXT:   [[DEF1:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
49  ; CHECK-NEXT: {{  $}}
50  ; CHECK-NEXT: bb.1.bb1:
51  ; CHECK-NEXT:   successors: %bb.3(0x40000000), %bb.2(0x40000000)
52  ; CHECK-NEXT: {{  $}}
53  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:_(p0) = G_PHI %6(p0), %bb.2, [[DEF]](p0), %bb.0
54  ; CHECK-NEXT:   [[PHI1:%[0-9]+]]:_(s16) = G_PHI %22(s16), %bb.2, [[DEF1]](s16), %bb.0
55  ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[PHI1]](s16)
56  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
57  ; CHECK-NEXT:   [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C1]]
58  ; CHECK-NEXT:   G_BRCOND [[AND]](s32), %bb.3
59  ; CHECK-NEXT: {{  $}}
60  ; CHECK-NEXT: bb.2.bb3:
61  ; CHECK-NEXT:   successors: %bb.3(0x40000000), %bb.1(0x40000000)
62  ; CHECK-NEXT: {{  $}}
63  ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4
64  ; CHECK-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[INTTOPTR]], [[C2]](s64)
65  ; CHECK-NEXT:   [[LOAD:%[0-9]+]]:_(s16) = G_LOAD [[PHI]](p0) :: (load (s16) from %ir.lsr.iv)
66  ; CHECK-NEXT:   [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD]](s16)
67  ; CHECK-NEXT:   [[C3:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
68  ; CHECK-NEXT:   [[ICMP:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ZEXT]](s32), [[C3]]
69  ; CHECK-NEXT:   [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from %ir.tmp5)
70  ; CHECK-NEXT:   [[ZEXT1:%[0-9]+]]:_(s32) = G_ZEXT [[LOAD1]](s16)
71  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY [[C3]](s32)
72  ; CHECK-NEXT:   [[ICMP1:%[0-9]+]]:_(s32) = G_ICMP intpred(eq), [[ZEXT1]](s32), [[COPY]]
73  ; CHECK-NEXT:   [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PHI]], [[C2]](s64)
74  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[ICMP1]](s32)
75  ; CHECK-NEXT:   G_BRCOND [[ICMP]](s32), %bb.3
76  ; CHECK-NEXT:   G_BR %bb.1
77  ; CHECK-NEXT: {{  $}}
78  ; CHECK-NEXT: bb.3.bb10:
79  ; CHECK-NEXT:   RET_ReallyLR
80  bb.1.bb:
81    %3:_(s64) = G_CONSTANT i64 0
82    %2:_(p0) = G_INTTOPTR %3(s64)
83    %7:_(s16) = G_CONSTANT i16 -1
84    %12:_(p0) = G_IMPLICIT_DEF
85    %13:_(s1) = G_IMPLICIT_DEF
86
87  bb.2.bb1:
88    %0:_(p0) = G_PHI %11(p0), %bb.3, %12(p0), %bb.1
89    %1:_(s1) = G_PHI %10(s1), %bb.3, %13(s1), %bb.1
90    G_BRCOND %1(s1), %bb.4
91
92  bb.3.bb3:
93    %4:_(s64) = G_CONSTANT i64 4
94    %5:_(p0) = G_PTR_ADD %2, %4(s64)
95    %6:_(s16) = G_LOAD %0(p0) :: (load (s16) from %ir.lsr.iv)
96    %8:_(s1) = G_ICMP intpred(eq), %6(s16), %7
97    %9:_(s16) = G_LOAD %5(p0) :: (load (s16) from %ir.tmp5)
98    %10:_(s1) = G_ICMP intpred(eq), %9(s16), %7
99    %11:_(p0) = G_PTR_ADD %0, %4(s64)
100    G_BRCOND %8(s1), %bb.4
101    G_BR %bb.2
102
103  bb.4.bb10:
104    RET_ReallyLR
105
106...
107