1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -mtriple=aarch64-- -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s 3 4--- 5name: v8s8_smin 6tracksRegLiveness: true 7body: | 8 bb.0: 9 liveins: $x0 10 11 ; CHECK-LABEL: name: v8s8_smin 12 ; CHECK: liveins: $x0 13 ; CHECK-NEXT: {{ $}} 14 ; CHECK-NEXT: %vec:_(<8 x s8>) = G_IMPLICIT_DEF 15 ; CHECK-NEXT: %vec1:_(<8 x s8>) = G_IMPLICIT_DEF 16 ; CHECK-NEXT: %smin:_(<8 x s8>) = G_SMIN %vec, %vec1 17 ; CHECK-NEXT: $x0 = COPY %smin(<8 x s8>) 18 ; CHECK-NEXT: RET_ReallyLR implicit $x0 19 %vec:_(<8 x s8>) = G_IMPLICIT_DEF 20 %vec1:_(<8 x s8>) = G_IMPLICIT_DEF 21 %smin:_(<8 x s8>) = G_SMIN %vec, %vec1 22 $x0 = COPY %smin 23 RET_ReallyLR implicit $x0 24 25... 26--- 27name: v16s8_smin 28tracksRegLiveness: true 29body: | 30 bb.0: 31 liveins: $q0 32 33 ; CHECK-LABEL: name: v16s8_smin 34 ; CHECK: liveins: $q0 35 ; CHECK-NEXT: {{ $}} 36 ; CHECK-NEXT: %vec:_(<16 x s8>) = G_IMPLICIT_DEF 37 ; CHECK-NEXT: %vec1:_(<16 x s8>) = G_IMPLICIT_DEF 38 ; CHECK-NEXT: %smin:_(<16 x s8>) = G_SMIN %vec, %vec1 39 ; CHECK-NEXT: $q0 = COPY %smin(<16 x s8>) 40 ; CHECK-NEXT: RET_ReallyLR implicit $q0 41 %vec:_(<16 x s8>) = G_IMPLICIT_DEF 42 %vec1:_(<16 x s8>) = G_IMPLICIT_DEF 43 %smin:_(<16 x s8>) = G_SMIN %vec, %vec1 44 $q0 = COPY %smin 45 RET_ReallyLR implicit $q0 46 47... 48--- 49name: v32s8_smin 50tracksRegLiveness: true 51body: | 52 bb.0: 53 liveins: $x0, $q0, $q1 54 55 ; CHECK-LABEL: name: v32s8_smin 56 ; CHECK: liveins: $x0, $q0, $q1 57 ; CHECK-NEXT: {{ $}} 58 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = G_IMPLICIT_DEF 59 ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(<16 x s8>) = G_SMIN [[DEF]], [[DEF]] 60 ; CHECK-NEXT: [[SMIN1:%[0-9]+]]:_(<16 x s8>) = G_SMIN [[DEF]], [[DEF]] 61 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 62 ; CHECK-NEXT: G_STORE [[SMIN]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32) 63 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 64 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) 65 ; CHECK-NEXT: G_STORE [[SMIN1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16) 66 %vec:_(<32 x s8>) = G_IMPLICIT_DEF 67 %vec1:_(<32 x s8>) = G_IMPLICIT_DEF 68 %smin:_(<32 x s8>) = G_SMIN %vec, %vec1 69 %1:_(p0) = COPY $x0 70 G_STORE %smin(<32 x s8>), %1(p0) :: (store (<32 x s8>)) 71 72... 73--- 74name: v4s16_smin 75tracksRegLiveness: true 76body: | 77 bb.0: 78 liveins: $x0 79 80 ; CHECK-LABEL: name: v4s16_smin 81 ; CHECK: liveins: $x0 82 ; CHECK-NEXT: {{ $}} 83 ; CHECK-NEXT: %vec:_(<4 x s16>) = G_IMPLICIT_DEF 84 ; CHECK-NEXT: %vec1:_(<4 x s16>) = G_IMPLICIT_DEF 85 ; CHECK-NEXT: %smin:_(<4 x s16>) = G_SMIN %vec, %vec1 86 ; CHECK-NEXT: $x0 = COPY %smin(<4 x s16>) 87 ; CHECK-NEXT: RET_ReallyLR implicit $x0 88 %vec:_(<4 x s16>) = G_IMPLICIT_DEF 89 %vec1:_(<4 x s16>) = G_IMPLICIT_DEF 90 %smin:_(<4 x s16>) = G_SMIN %vec, %vec1 91 $x0 = COPY %smin 92 RET_ReallyLR implicit $x0 93 94... 95--- 96name: v8s16_smin 97tracksRegLiveness: true 98body: | 99 bb.0: 100 liveins: $q0 101 102 ; CHECK-LABEL: name: v8s16_smin 103 ; CHECK: liveins: $q0 104 ; CHECK-NEXT: {{ $}} 105 ; CHECK-NEXT: %vec:_(<8 x s16>) = G_IMPLICIT_DEF 106 ; CHECK-NEXT: %vec1:_(<8 x s16>) = G_IMPLICIT_DEF 107 ; CHECK-NEXT: %smin:_(<8 x s16>) = G_SMIN %vec, %vec1 108 ; CHECK-NEXT: $q0 = COPY %smin(<8 x s16>) 109 ; CHECK-NEXT: RET_ReallyLR implicit $q0 110 %vec:_(<8 x s16>) = G_IMPLICIT_DEF 111 %vec1:_(<8 x s16>) = G_IMPLICIT_DEF 112 %smin:_(<8 x s16>) = G_SMIN %vec, %vec1 113 $q0 = COPY %smin 114 RET_ReallyLR implicit $q0 115 116... 117--- 118name: v16s16_smin 119tracksRegLiveness: true 120body: | 121 bb.0: 122 liveins: $x0, $q0, $q1 123 124 ; CHECK-LABEL: name: v16s16_smin 125 ; CHECK: liveins: $x0, $q0, $q1 126 ; CHECK-NEXT: {{ $}} 127 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = G_IMPLICIT_DEF 128 ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(<8 x s16>) = G_SMIN [[DEF]], [[DEF]] 129 ; CHECK-NEXT: [[SMIN1:%[0-9]+]]:_(<8 x s16>) = G_SMIN [[DEF]], [[DEF]] 130 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 131 ; CHECK-NEXT: G_STORE [[SMIN]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32) 132 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 133 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) 134 ; CHECK-NEXT: G_STORE [[SMIN1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16) 135 %vec:_(<16 x s16>) = G_IMPLICIT_DEF 136 %vec1:_(<16 x s16>) = G_IMPLICIT_DEF 137 %smin:_(<16 x s16>) = G_SMIN %vec, %vec1 138 %1:_(p0) = COPY $x0 139 G_STORE %smin(<16 x s16>), %1(p0) :: (store (<16 x s16>)) 140 141... 142--- 143name: v2s32_smin 144tracksRegLiveness: true 145body: | 146 bb.0: 147 liveins: $x0 148 149 ; CHECK-LABEL: name: v2s32_smin 150 ; CHECK: liveins: $x0 151 ; CHECK-NEXT: {{ $}} 152 ; CHECK-NEXT: %vec:_(<2 x s32>) = G_IMPLICIT_DEF 153 ; CHECK-NEXT: %vec1:_(<2 x s32>) = G_IMPLICIT_DEF 154 ; CHECK-NEXT: %smin:_(<2 x s32>) = G_SMIN %vec, %vec1 155 ; CHECK-NEXT: $x0 = COPY %smin(<2 x s32>) 156 ; CHECK-NEXT: RET_ReallyLR implicit $x0 157 %vec:_(<2 x s32>) = G_IMPLICIT_DEF 158 %vec1:_(<2 x s32>) = G_IMPLICIT_DEF 159 %smin:_(<2 x s32>) = G_SMIN %vec, %vec1 160 $x0 = COPY %smin 161 RET_ReallyLR implicit $x0 162 163... 164--- 165name: v4s32_smin 166tracksRegLiveness: true 167body: | 168 bb.0: 169 liveins: $q0 170 171 ; CHECK-LABEL: name: v4s32_smin 172 ; CHECK: liveins: $q0 173 ; CHECK-NEXT: {{ $}} 174 ; CHECK-NEXT: %vec:_(<4 x s32>) = G_IMPLICIT_DEF 175 ; CHECK-NEXT: %vec1:_(<4 x s32>) = G_IMPLICIT_DEF 176 ; CHECK-NEXT: %smin:_(<4 x s32>) = G_SMIN %vec, %vec1 177 ; CHECK-NEXT: $q0 = COPY %smin(<4 x s32>) 178 ; CHECK-NEXT: RET_ReallyLR implicit $q0 179 %vec:_(<4 x s32>) = G_IMPLICIT_DEF 180 %vec1:_(<4 x s32>) = G_IMPLICIT_DEF 181 %smin:_(<4 x s32>) = G_SMIN %vec, %vec1 182 $q0 = COPY %smin 183 RET_ReallyLR implicit $q0 184 185... 186--- 187name: v8s32_smin 188tracksRegLiveness: true 189body: | 190 bb.0: 191 liveins: $x0, $q0, $q1 192 193 ; CHECK-LABEL: name: v8s32_smin 194 ; CHECK: liveins: $x0, $q0, $q1 195 ; CHECK-NEXT: {{ $}} 196 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF 197 ; CHECK-NEXT: [[SMIN:%[0-9]+]]:_(<4 x s32>) = G_SMIN [[DEF]], [[DEF]] 198 ; CHECK-NEXT: [[SMIN1:%[0-9]+]]:_(<4 x s32>) = G_SMIN [[DEF]], [[DEF]] 199 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 200 ; CHECK-NEXT: G_STORE [[SMIN]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32) 201 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 202 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) 203 ; CHECK-NEXT: G_STORE [[SMIN1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16) 204 %vec:_(<8 x s32>) = G_IMPLICIT_DEF 205 %vec1:_(<8 x s32>) = G_IMPLICIT_DEF 206 %smin:_(<8 x s32>) = G_SMIN %vec, %vec1 207 %1:_(p0) = COPY $x0 208 G_STORE %smin(<8 x s32>), %1(p0) :: (store (<8 x s32>)) 209 210... 211--- 212name: v2s64_smin 213tracksRegLiveness: true 214body: | 215 bb.0: 216 liveins: $q0 217 218 ; CHECK-LABEL: name: v2s64_smin 219 ; CHECK: liveins: $q0 220 ; CHECK-NEXT: {{ $}} 221 ; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF 222 ; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF 223 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), %vec(<2 x s64>), %vec1 224 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 225 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64) 226 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]] 227 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ICMP]] 228 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]] 229 ; CHECK-NEXT: %smin:_(<2 x s64>) = G_OR [[AND]], [[AND1]] 230 ; CHECK-NEXT: $q0 = COPY %smin(<2 x s64>) 231 ; CHECK-NEXT: RET_ReallyLR implicit $q0 232 %vec:_(<2 x s64>) = G_IMPLICIT_DEF 233 %vec1:_(<2 x s64>) = G_IMPLICIT_DEF 234 %smin:_(<2 x s64>) = G_SMIN %vec, %vec1 235 $q0 = COPY %smin 236 RET_ReallyLR implicit $q0 237 238... 239--- 240name: v4s64_smin 241tracksRegLiveness: true 242body: | 243 bb.0: 244 liveins: $x0, $q0, $q1 245 246 ; CHECK-LABEL: name: v4s64_smin 247 ; CHECK: liveins: $x0, $q0, $q1 248 ; CHECK-NEXT: {{ $}} 249 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF 250 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]] 251 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 252 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64) 253 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]] 254 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]] 255 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]] 256 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]] 257 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(slt), [[DEF]](<2 x s64>), [[DEF]] 258 ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]] 259 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]] 260 ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]] 261 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]] 262 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 263 ; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32) 264 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 265 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64) 266 ; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16) 267 %vec:_(<4 x s64>) = G_IMPLICIT_DEF 268 %vec1:_(<4 x s64>) = G_IMPLICIT_DEF 269 %smin:_(<4 x s64>) = G_SMIN %vec, %vec1 270 %1:_(p0) = COPY $x0 271 G_STORE %smin(<4 x s64>), %1(p0) :: (store (<4 x s64>)) 272 273... 274--- 275name: v8s8_umin 276tracksRegLiveness: true 277body: | 278 bb.0: 279 liveins: $x0 280 281 ; CHECK-LABEL: name: v8s8_umin 282 ; CHECK: liveins: $x0 283 ; CHECK-NEXT: {{ $}} 284 ; CHECK-NEXT: %vec:_(<8 x s8>) = G_IMPLICIT_DEF 285 ; CHECK-NEXT: %vec1:_(<8 x s8>) = G_IMPLICIT_DEF 286 ; CHECK-NEXT: %umin:_(<8 x s8>) = G_UMIN %vec, %vec1 287 ; CHECK-NEXT: $x0 = COPY %umin(<8 x s8>) 288 ; CHECK-NEXT: RET_ReallyLR implicit $x0 289 %vec:_(<8 x s8>) = G_IMPLICIT_DEF 290 %vec1:_(<8 x s8>) = G_IMPLICIT_DEF 291 %umin:_(<8 x s8>) = G_UMIN %vec, %vec1 292 $x0 = COPY %umin 293 RET_ReallyLR implicit $x0 294 295... 296--- 297name: v16s8_umin 298tracksRegLiveness: true 299body: | 300 bb.0: 301 liveins: $q0 302 303 ; CHECK-LABEL: name: v16s8_umin 304 ; CHECK: liveins: $q0 305 ; CHECK-NEXT: {{ $}} 306 ; CHECK-NEXT: %vec:_(<16 x s8>) = G_IMPLICIT_DEF 307 ; CHECK-NEXT: %vec1:_(<16 x s8>) = G_IMPLICIT_DEF 308 ; CHECK-NEXT: %umin:_(<16 x s8>) = G_UMIN %vec, %vec1 309 ; CHECK-NEXT: $q0 = COPY %umin(<16 x s8>) 310 ; CHECK-NEXT: RET_ReallyLR implicit $q0 311 %vec:_(<16 x s8>) = G_IMPLICIT_DEF 312 %vec1:_(<16 x s8>) = G_IMPLICIT_DEF 313 %umin:_(<16 x s8>) = G_UMIN %vec, %vec1 314 $q0 = COPY %umin 315 RET_ReallyLR implicit $q0 316 317... 318--- 319name: v32s8_umin 320tracksRegLiveness: true 321body: | 322 bb.0: 323 liveins: $x0, $q0, $q1 324 325 ; CHECK-LABEL: name: v32s8_umin 326 ; CHECK: liveins: $x0, $q0, $q1 327 ; CHECK-NEXT: {{ $}} 328 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = G_IMPLICIT_DEF 329 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(<16 x s8>) = G_UMIN [[DEF]], [[DEF]] 330 ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(<16 x s8>) = G_UMIN [[DEF]], [[DEF]] 331 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 332 ; CHECK-NEXT: G_STORE [[UMIN]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32) 333 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 334 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) 335 ; CHECK-NEXT: G_STORE [[UMIN1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16) 336 %vec:_(<32 x s8>) = G_IMPLICIT_DEF 337 %vec1:_(<32 x s8>) = G_IMPLICIT_DEF 338 %umin:_(<32 x s8>) = G_UMIN %vec, %vec1 339 %1:_(p0) = COPY $x0 340 G_STORE %umin(<32 x s8>), %1(p0) :: (store (<32 x s8>)) 341 342... 343--- 344name: v4s16_umin 345tracksRegLiveness: true 346body: | 347 bb.0: 348 liveins: $x0 349 350 ; CHECK-LABEL: name: v4s16_umin 351 ; CHECK: liveins: $x0 352 ; CHECK-NEXT: {{ $}} 353 ; CHECK-NEXT: %vec:_(<4 x s16>) = G_IMPLICIT_DEF 354 ; CHECK-NEXT: %vec1:_(<4 x s16>) = G_IMPLICIT_DEF 355 ; CHECK-NEXT: %umin:_(<4 x s16>) = G_UMIN %vec, %vec1 356 ; CHECK-NEXT: $x0 = COPY %umin(<4 x s16>) 357 ; CHECK-NEXT: RET_ReallyLR implicit $x0 358 %vec:_(<4 x s16>) = G_IMPLICIT_DEF 359 %vec1:_(<4 x s16>) = G_IMPLICIT_DEF 360 %umin:_(<4 x s16>) = G_UMIN %vec, %vec1 361 $x0 = COPY %umin 362 RET_ReallyLR implicit $x0 363 364... 365--- 366name: v8s16_umin 367tracksRegLiveness: true 368body: | 369 bb.0: 370 liveins: $q0 371 372 ; CHECK-LABEL: name: v8s16_umin 373 ; CHECK: liveins: $q0 374 ; CHECK-NEXT: {{ $}} 375 ; CHECK-NEXT: %vec:_(<8 x s16>) = G_IMPLICIT_DEF 376 ; CHECK-NEXT: %vec1:_(<8 x s16>) = G_IMPLICIT_DEF 377 ; CHECK-NEXT: %umin:_(<8 x s16>) = G_UMIN %vec, %vec1 378 ; CHECK-NEXT: $q0 = COPY %umin(<8 x s16>) 379 ; CHECK-NEXT: RET_ReallyLR implicit $q0 380 %vec:_(<8 x s16>) = G_IMPLICIT_DEF 381 %vec1:_(<8 x s16>) = G_IMPLICIT_DEF 382 %umin:_(<8 x s16>) = G_UMIN %vec, %vec1 383 $q0 = COPY %umin 384 RET_ReallyLR implicit $q0 385 386... 387--- 388name: v16s16_umin 389tracksRegLiveness: true 390body: | 391 bb.0: 392 liveins: $x0, $q0, $q1 393 394 ; CHECK-LABEL: name: v16s16_umin 395 ; CHECK: liveins: $x0, $q0, $q1 396 ; CHECK-NEXT: {{ $}} 397 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = G_IMPLICIT_DEF 398 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(<8 x s16>) = G_UMIN [[DEF]], [[DEF]] 399 ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(<8 x s16>) = G_UMIN [[DEF]], [[DEF]] 400 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 401 ; CHECK-NEXT: G_STORE [[UMIN]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32) 402 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 403 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) 404 ; CHECK-NEXT: G_STORE [[UMIN1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16) 405 %vec:_(<16 x s16>) = G_IMPLICIT_DEF 406 %vec1:_(<16 x s16>) = G_IMPLICIT_DEF 407 %umin:_(<16 x s16>) = G_UMIN %vec, %vec1 408 %1:_(p0) = COPY $x0 409 G_STORE %umin(<16 x s16>), %1(p0) :: (store (<16 x s16>)) 410 411... 412--- 413name: v2s32_umin 414tracksRegLiveness: true 415body: | 416 bb.0: 417 liveins: $x0 418 419 ; CHECK-LABEL: name: v2s32_umin 420 ; CHECK: liveins: $x0 421 ; CHECK-NEXT: {{ $}} 422 ; CHECK-NEXT: %vec:_(<2 x s32>) = G_IMPLICIT_DEF 423 ; CHECK-NEXT: %vec1:_(<2 x s32>) = G_IMPLICIT_DEF 424 ; CHECK-NEXT: %umin:_(<2 x s32>) = G_UMIN %vec, %vec1 425 ; CHECK-NEXT: $x0 = COPY %umin(<2 x s32>) 426 ; CHECK-NEXT: RET_ReallyLR implicit $x0 427 %vec:_(<2 x s32>) = G_IMPLICIT_DEF 428 %vec1:_(<2 x s32>) = G_IMPLICIT_DEF 429 %umin:_(<2 x s32>) = G_UMIN %vec, %vec1 430 $x0 = COPY %umin 431 RET_ReallyLR implicit $x0 432 433... 434--- 435name: v4s32_umin 436tracksRegLiveness: true 437body: | 438 bb.0: 439 liveins: $q0 440 441 ; CHECK-LABEL: name: v4s32_umin 442 ; CHECK: liveins: $q0 443 ; CHECK-NEXT: {{ $}} 444 ; CHECK-NEXT: %vec:_(<4 x s32>) = G_IMPLICIT_DEF 445 ; CHECK-NEXT: %vec1:_(<4 x s32>) = G_IMPLICIT_DEF 446 ; CHECK-NEXT: %umin:_(<4 x s32>) = G_UMIN %vec, %vec1 447 ; CHECK-NEXT: $q0 = COPY %umin(<4 x s32>) 448 ; CHECK-NEXT: RET_ReallyLR implicit $q0 449 %vec:_(<4 x s32>) = G_IMPLICIT_DEF 450 %vec1:_(<4 x s32>) = G_IMPLICIT_DEF 451 %umin:_(<4 x s32>) = G_UMIN %vec, %vec1 452 $q0 = COPY %umin 453 RET_ReallyLR implicit $q0 454 455... 456--- 457name: v8s32_umin 458tracksRegLiveness: true 459body: | 460 bb.0: 461 liveins: $x0, $q0, $q1 462 463 ; CHECK-LABEL: name: v8s32_umin 464 ; CHECK: liveins: $x0, $q0, $q1 465 ; CHECK-NEXT: {{ $}} 466 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF 467 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:_(<4 x s32>) = G_UMIN [[DEF]], [[DEF]] 468 ; CHECK-NEXT: [[UMIN1:%[0-9]+]]:_(<4 x s32>) = G_UMIN [[DEF]], [[DEF]] 469 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 470 ; CHECK-NEXT: G_STORE [[UMIN]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32) 471 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 472 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) 473 ; CHECK-NEXT: G_STORE [[UMIN1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16) 474 %vec:_(<8 x s32>) = G_IMPLICIT_DEF 475 %vec1:_(<8 x s32>) = G_IMPLICIT_DEF 476 %umin:_(<8 x s32>) = G_UMIN %vec, %vec1 477 %1:_(p0) = COPY $x0 478 G_STORE %umin(<8 x s32>), %1(p0) :: (store (<8 x s32>)) 479 480... 481--- 482name: v2s64_umin 483tracksRegLiveness: true 484body: | 485 bb.0: 486 liveins: $q0 487 488 ; CHECK-LABEL: name: v2s64_umin 489 ; CHECK: liveins: $q0 490 ; CHECK-NEXT: {{ $}} 491 ; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF 492 ; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF 493 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), %vec(<2 x s64>), %vec1 494 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 495 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64) 496 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]] 497 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ICMP]] 498 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]] 499 ; CHECK-NEXT: %umin:_(<2 x s64>) = G_OR [[AND]], [[AND1]] 500 ; CHECK-NEXT: $q0 = COPY %umin(<2 x s64>) 501 ; CHECK-NEXT: RET_ReallyLR implicit $q0 502 %vec:_(<2 x s64>) = G_IMPLICIT_DEF 503 %vec1:_(<2 x s64>) = G_IMPLICIT_DEF 504 %umin:_(<2 x s64>) = G_UMIN %vec, %vec1 505 $q0 = COPY %umin 506 RET_ReallyLR implicit $q0 507 508... 509--- 510name: v4s64_umin 511tracksRegLiveness: true 512body: | 513 bb.0: 514 liveins: $x0, $q0, $q1 515 516 ; CHECK-LABEL: name: v4s64_umin 517 ; CHECK: liveins: $x0, $q0, $q1 518 ; CHECK-NEXT: {{ $}} 519 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF 520 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]] 521 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 522 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64) 523 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]] 524 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]] 525 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]] 526 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]] 527 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ult), [[DEF]](<2 x s64>), [[DEF]] 528 ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]] 529 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]] 530 ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]] 531 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]] 532 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 533 ; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32) 534 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 535 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64) 536 ; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16) 537 %vec:_(<4 x s64>) = G_IMPLICIT_DEF 538 %vec1:_(<4 x s64>) = G_IMPLICIT_DEF 539 %umin:_(<4 x s64>) = G_UMIN %vec, %vec1 540 %1:_(p0) = COPY $x0 541 G_STORE %umin(<4 x s64>), %1(p0) :: (store (<4 x s64>)) 542 543... 544--- 545name: v8s8_smax 546tracksRegLiveness: true 547body: | 548 bb.0: 549 liveins: $x0 550 551 ; CHECK-LABEL: name: v8s8_smax 552 ; CHECK: liveins: $x0 553 ; CHECK-NEXT: {{ $}} 554 ; CHECK-NEXT: %vec:_(<8 x s8>) = G_IMPLICIT_DEF 555 ; CHECK-NEXT: %vec1:_(<8 x s8>) = G_IMPLICIT_DEF 556 ; CHECK-NEXT: %smax:_(<8 x s8>) = G_SMAX %vec, %vec1 557 ; CHECK-NEXT: $x0 = COPY %smax(<8 x s8>) 558 ; CHECK-NEXT: RET_ReallyLR implicit $x0 559 %vec:_(<8 x s8>) = G_IMPLICIT_DEF 560 %vec1:_(<8 x s8>) = G_IMPLICIT_DEF 561 %smax:_(<8 x s8>) = G_SMAX %vec, %vec1 562 $x0 = COPY %smax 563 RET_ReallyLR implicit $x0 564 565... 566--- 567name: v16s8_smax 568tracksRegLiveness: true 569body: | 570 bb.0: 571 liveins: $q0 572 573 ; CHECK-LABEL: name: v16s8_smax 574 ; CHECK: liveins: $q0 575 ; CHECK-NEXT: {{ $}} 576 ; CHECK-NEXT: %vec:_(<16 x s8>) = G_IMPLICIT_DEF 577 ; CHECK-NEXT: %vec1:_(<16 x s8>) = G_IMPLICIT_DEF 578 ; CHECK-NEXT: %smax:_(<16 x s8>) = G_SMAX %vec, %vec1 579 ; CHECK-NEXT: $q0 = COPY %smax(<16 x s8>) 580 ; CHECK-NEXT: RET_ReallyLR implicit $q0 581 %vec:_(<16 x s8>) = G_IMPLICIT_DEF 582 %vec1:_(<16 x s8>) = G_IMPLICIT_DEF 583 %smax:_(<16 x s8>) = G_SMAX %vec, %vec1 584 $q0 = COPY %smax 585 RET_ReallyLR implicit $q0 586 587... 588--- 589name: v4s16_smax 590tracksRegLiveness: true 591body: | 592 bb.0: 593 liveins: $x0 594 595 ; CHECK-LABEL: name: v4s16_smax 596 ; CHECK: liveins: $x0 597 ; CHECK-NEXT: {{ $}} 598 ; CHECK-NEXT: %vec:_(<4 x s16>) = G_IMPLICIT_DEF 599 ; CHECK-NEXT: %vec1:_(<4 x s16>) = G_IMPLICIT_DEF 600 ; CHECK-NEXT: %smax:_(<4 x s16>) = G_SMAX %vec, %vec1 601 ; CHECK-NEXT: $x0 = COPY %smax(<4 x s16>) 602 ; CHECK-NEXT: RET_ReallyLR implicit $x0 603 %vec:_(<4 x s16>) = G_IMPLICIT_DEF 604 %vec1:_(<4 x s16>) = G_IMPLICIT_DEF 605 %smax:_(<4 x s16>) = G_SMAX %vec, %vec1 606 $x0 = COPY %smax 607 RET_ReallyLR implicit $x0 608 609... 610--- 611name: v32s8_smax 612tracksRegLiveness: true 613body: | 614 bb.0: 615 liveins: $x0, $q0, $q1 616 617 ; CHECK-LABEL: name: v32s8_smax 618 ; CHECK: liveins: $x0, $q0, $q1 619 ; CHECK-NEXT: {{ $}} 620 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = G_IMPLICIT_DEF 621 ; CHECK-NEXT: [[SMAX:%[0-9]+]]:_(<16 x s8>) = G_SMAX [[DEF]], [[DEF]] 622 ; CHECK-NEXT: [[SMAX1:%[0-9]+]]:_(<16 x s8>) = G_SMAX [[DEF]], [[DEF]] 623 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 624 ; CHECK-NEXT: G_STORE [[SMAX]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32) 625 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 626 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) 627 ; CHECK-NEXT: G_STORE [[SMAX1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16) 628 %vec:_(<32 x s8>) = G_IMPLICIT_DEF 629 %vec1:_(<32 x s8>) = G_IMPLICIT_DEF 630 %smax:_(<32 x s8>) = G_SMAX %vec, %vec1 631 %1:_(p0) = COPY $x0 632 G_STORE %smax(<32 x s8>), %1(p0) :: (store (<32 x s8>)) 633 634... 635--- 636name: v8s16_smax 637tracksRegLiveness: true 638body: | 639 bb.0: 640 liveins: $q0 641 642 ; CHECK-LABEL: name: v8s16_smax 643 ; CHECK: liveins: $q0 644 ; CHECK-NEXT: {{ $}} 645 ; CHECK-NEXT: %vec:_(<8 x s16>) = G_IMPLICIT_DEF 646 ; CHECK-NEXT: %vec1:_(<8 x s16>) = G_IMPLICIT_DEF 647 ; CHECK-NEXT: %smax:_(<8 x s16>) = G_SMAX %vec, %vec1 648 ; CHECK-NEXT: $q0 = COPY %smax(<8 x s16>) 649 ; CHECK-NEXT: RET_ReallyLR implicit $q0 650 %vec:_(<8 x s16>) = G_IMPLICIT_DEF 651 %vec1:_(<8 x s16>) = G_IMPLICIT_DEF 652 %smax:_(<8 x s16>) = G_SMAX %vec, %vec1 653 $q0 = COPY %smax 654 RET_ReallyLR implicit $q0 655 656... 657--- 658name: v16s16_smax 659tracksRegLiveness: true 660body: | 661 bb.0: 662 liveins: $x0, $q0, $q1 663 664 ; CHECK-LABEL: name: v16s16_smax 665 ; CHECK: liveins: $x0, $q0, $q1 666 ; CHECK-NEXT: {{ $}} 667 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = G_IMPLICIT_DEF 668 ; CHECK-NEXT: [[SMAX:%[0-9]+]]:_(<8 x s16>) = G_SMAX [[DEF]], [[DEF]] 669 ; CHECK-NEXT: [[SMAX1:%[0-9]+]]:_(<8 x s16>) = G_SMAX [[DEF]], [[DEF]] 670 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 671 ; CHECK-NEXT: G_STORE [[SMAX]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32) 672 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 673 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) 674 ; CHECK-NEXT: G_STORE [[SMAX1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16) 675 %vec:_(<16 x s16>) = G_IMPLICIT_DEF 676 %vec1:_(<16 x s16>) = G_IMPLICIT_DEF 677 %smax:_(<16 x s16>) = G_SMAX %vec, %vec1 678 %1:_(p0) = COPY $x0 679 G_STORE %smax(<16 x s16>), %1(p0) :: (store (<16 x s16>)) 680 681... 682--- 683name: v2s32_smax 684tracksRegLiveness: true 685body: | 686 bb.0: 687 liveins: $x0 688 689 ; CHECK-LABEL: name: v2s32_smax 690 ; CHECK: liveins: $x0 691 ; CHECK-NEXT: {{ $}} 692 ; CHECK-NEXT: %vec:_(<2 x s32>) = G_IMPLICIT_DEF 693 ; CHECK-NEXT: %vec1:_(<2 x s32>) = G_IMPLICIT_DEF 694 ; CHECK-NEXT: %smax:_(<2 x s32>) = G_SMAX %vec, %vec1 695 ; CHECK-NEXT: $x0 = COPY %smax(<2 x s32>) 696 ; CHECK-NEXT: RET_ReallyLR implicit $x0 697 %vec:_(<2 x s32>) = G_IMPLICIT_DEF 698 %vec1:_(<2 x s32>) = G_IMPLICIT_DEF 699 %smax:_(<2 x s32>) = G_SMAX %vec, %vec1 700 $x0 = COPY %smax 701 RET_ReallyLR implicit $x0 702 703... 704--- 705name: v4s32_smax 706tracksRegLiveness: true 707body: | 708 bb.0: 709 liveins: $q0 710 711 ; CHECK-LABEL: name: v4s32_smax 712 ; CHECK: liveins: $q0 713 ; CHECK-NEXT: {{ $}} 714 ; CHECK-NEXT: %vec:_(<4 x s32>) = G_IMPLICIT_DEF 715 ; CHECK-NEXT: %vec1:_(<4 x s32>) = G_IMPLICIT_DEF 716 ; CHECK-NEXT: %smax:_(<4 x s32>) = G_SMAX %vec, %vec1 717 ; CHECK-NEXT: $q0 = COPY %smax(<4 x s32>) 718 ; CHECK-NEXT: RET_ReallyLR implicit $q0 719 %vec:_(<4 x s32>) = G_IMPLICIT_DEF 720 %vec1:_(<4 x s32>) = G_IMPLICIT_DEF 721 %smax:_(<4 x s32>) = G_SMAX %vec, %vec1 722 $q0 = COPY %smax 723 RET_ReallyLR implicit $q0 724 725... 726--- 727name: v8s32_smax 728tracksRegLiveness: true 729body: | 730 bb.0: 731 liveins: $x0, $q0, $q1 732 733 ; CHECK-LABEL: name: v8s32_smax 734 ; CHECK: liveins: $x0, $q0, $q1 735 ; CHECK-NEXT: {{ $}} 736 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF 737 ; CHECK-NEXT: [[SMAX:%[0-9]+]]:_(<4 x s32>) = G_SMAX [[DEF]], [[DEF]] 738 ; CHECK-NEXT: [[SMAX1:%[0-9]+]]:_(<4 x s32>) = G_SMAX [[DEF]], [[DEF]] 739 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 740 ; CHECK-NEXT: G_STORE [[SMAX]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32) 741 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 742 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) 743 ; CHECK-NEXT: G_STORE [[SMAX1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16) 744 %vec:_(<8 x s32>) = G_IMPLICIT_DEF 745 %vec1:_(<8 x s32>) = G_IMPLICIT_DEF 746 %smax:_(<8 x s32>) = G_SMAX %vec, %vec1 747 %1:_(p0) = COPY $x0 748 G_STORE %smax(<8 x s32>), %1(p0) :: (store (<8 x s32>)) 749 750... 751--- 752name: v2s64_smax 753tracksRegLiveness: true 754body: | 755 bb.0: 756 liveins: $q0 757 758 ; CHECK-LABEL: name: v2s64_smax 759 ; CHECK: liveins: $q0 760 ; CHECK-NEXT: {{ $}} 761 ; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF 762 ; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF 763 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), %vec(<2 x s64>), %vec1 764 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 765 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64) 766 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]] 767 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ICMP]] 768 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]] 769 ; CHECK-NEXT: %smax:_(<2 x s64>) = G_OR [[AND]], [[AND1]] 770 ; CHECK-NEXT: $q0 = COPY %smax(<2 x s64>) 771 ; CHECK-NEXT: RET_ReallyLR implicit $q0 772 %vec:_(<2 x s64>) = G_IMPLICIT_DEF 773 %vec1:_(<2 x s64>) = G_IMPLICIT_DEF 774 %smax:_(<2 x s64>) = G_SMAX %vec, %vec1 775 $q0 = COPY %smax 776 RET_ReallyLR implicit $q0 777 778... 779--- 780name: v4s64_smax 781tracksRegLiveness: true 782body: | 783 bb.0: 784 liveins: $x0, $q0, $q1 785 786 ; CHECK-LABEL: name: v4s64_smax 787 ; CHECK: liveins: $x0, $q0, $q1 788 ; CHECK-NEXT: {{ $}} 789 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF 790 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]] 791 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 792 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64) 793 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]] 794 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]] 795 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]] 796 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]] 797 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(sgt), [[DEF]](<2 x s64>), [[DEF]] 798 ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]] 799 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]] 800 ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]] 801 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]] 802 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 803 ; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32) 804 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 805 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64) 806 ; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16) 807 %vec:_(<4 x s64>) = G_IMPLICIT_DEF 808 %vec1:_(<4 x s64>) = G_IMPLICIT_DEF 809 %smax:_(<4 x s64>) = G_SMAX %vec, %vec1 810 %1:_(p0) = COPY $x0 811 G_STORE %smax(<4 x s64>), %1(p0) :: (store (<4 x s64>)) 812 813... 814--- 815name: v8s8_umax 816tracksRegLiveness: true 817body: | 818 bb.0: 819 liveins: $x0 820 821 ; CHECK-LABEL: name: v8s8_umax 822 ; CHECK: liveins: $x0 823 ; CHECK-NEXT: {{ $}} 824 ; CHECK-NEXT: %vec:_(<8 x s8>) = G_IMPLICIT_DEF 825 ; CHECK-NEXT: %vec1:_(<8 x s8>) = G_IMPLICIT_DEF 826 ; CHECK-NEXT: %umax:_(<8 x s8>) = G_UMAX %vec, %vec1 827 ; CHECK-NEXT: $x0 = COPY %umax(<8 x s8>) 828 ; CHECK-NEXT: RET_ReallyLR implicit $x0 829 %vec:_(<8 x s8>) = G_IMPLICIT_DEF 830 %vec1:_(<8 x s8>) = G_IMPLICIT_DEF 831 %umax:_(<8 x s8>) = G_UMAX %vec, %vec1 832 $x0 = COPY %umax 833 RET_ReallyLR implicit $x0 834 835... 836--- 837name: v16s8_umax 838tracksRegLiveness: true 839body: | 840 bb.0: 841 liveins: $q0 842 843 ; CHECK-LABEL: name: v16s8_umax 844 ; CHECK: liveins: $q0 845 ; CHECK-NEXT: {{ $}} 846 ; CHECK-NEXT: %vec:_(<16 x s8>) = G_IMPLICIT_DEF 847 ; CHECK-NEXT: %vec1:_(<16 x s8>) = G_IMPLICIT_DEF 848 ; CHECK-NEXT: %umax:_(<16 x s8>) = G_UMAX %vec, %vec1 849 ; CHECK-NEXT: $q0 = COPY %umax(<16 x s8>) 850 ; CHECK-NEXT: RET_ReallyLR implicit $q0 851 %vec:_(<16 x s8>) = G_IMPLICIT_DEF 852 %vec1:_(<16 x s8>) = G_IMPLICIT_DEF 853 %umax:_(<16 x s8>) = G_UMAX %vec, %vec1 854 $q0 = COPY %umax 855 RET_ReallyLR implicit $q0 856 857... 858--- 859name: v32s8_umax 860tracksRegLiveness: true 861body: | 862 bb.0: 863 liveins: $x0, $q0, $q1 864 865 ; CHECK-LABEL: name: v32s8_umax 866 ; CHECK: liveins: $x0, $q0, $q1 867 ; CHECK-NEXT: {{ $}} 868 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = G_IMPLICIT_DEF 869 ; CHECK-NEXT: [[UMAX:%[0-9]+]]:_(<16 x s8>) = G_UMAX [[DEF]], [[DEF]] 870 ; CHECK-NEXT: [[UMAX1:%[0-9]+]]:_(<16 x s8>) = G_UMAX [[DEF]], [[DEF]] 871 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 872 ; CHECK-NEXT: G_STORE [[UMAX]](<16 x s8>), [[COPY]](p0) :: (store (<16 x s8>), align 32) 873 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 874 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) 875 ; CHECK-NEXT: G_STORE [[UMAX1]](<16 x s8>), [[PTR_ADD]](p0) :: (store (<16 x s8>) into unknown-address + 16) 876 %vec:_(<32 x s8>) = G_IMPLICIT_DEF 877 %vec1:_(<32 x s8>) = G_IMPLICIT_DEF 878 %umax:_(<32 x s8>) = G_UMAX %vec, %vec1 879 %1:_(p0) = COPY $x0 880 G_STORE %umax(<32 x s8>), %1(p0) :: (store (<32 x s8>)) 881 882... 883--- 884name: v4s16_umax 885tracksRegLiveness: true 886body: | 887 bb.0: 888 liveins: $x0 889 890 ; CHECK-LABEL: name: v4s16_umax 891 ; CHECK: liveins: $x0 892 ; CHECK-NEXT: {{ $}} 893 ; CHECK-NEXT: %vec:_(<4 x s16>) = G_IMPLICIT_DEF 894 ; CHECK-NEXT: %vec1:_(<4 x s16>) = G_IMPLICIT_DEF 895 ; CHECK-NEXT: %umax:_(<4 x s16>) = G_UMAX %vec, %vec1 896 ; CHECK-NEXT: $x0 = COPY %umax(<4 x s16>) 897 ; CHECK-NEXT: RET_ReallyLR implicit $x0 898 %vec:_(<4 x s16>) = G_IMPLICIT_DEF 899 %vec1:_(<4 x s16>) = G_IMPLICIT_DEF 900 %umax:_(<4 x s16>) = G_UMAX %vec, %vec1 901 $x0 = COPY %umax 902 RET_ReallyLR implicit $x0 903 904... 905--- 906name: v8s16_umax 907tracksRegLiveness: true 908body: | 909 bb.0: 910 liveins: $q0 911 912 ; CHECK-LABEL: name: v8s16_umax 913 ; CHECK: liveins: $q0 914 ; CHECK-NEXT: {{ $}} 915 ; CHECK-NEXT: %vec:_(<8 x s16>) = G_IMPLICIT_DEF 916 ; CHECK-NEXT: %vec1:_(<8 x s16>) = G_IMPLICIT_DEF 917 ; CHECK-NEXT: %umax:_(<8 x s16>) = G_UMAX %vec, %vec1 918 ; CHECK-NEXT: $q0 = COPY %umax(<8 x s16>) 919 ; CHECK-NEXT: RET_ReallyLR implicit $q0 920 %vec:_(<8 x s16>) = G_IMPLICIT_DEF 921 %vec1:_(<8 x s16>) = G_IMPLICIT_DEF 922 %umax:_(<8 x s16>) = G_UMAX %vec, %vec1 923 $q0 = COPY %umax 924 RET_ReallyLR implicit $q0 925 926... 927--- 928name: v16s16_umax 929tracksRegLiveness: true 930body: | 931 bb.0: 932 liveins: $x0, $q0, $q1 933 934 ; CHECK-LABEL: name: v16s16_umax 935 ; CHECK: liveins: $x0, $q0, $q1 936 ; CHECK-NEXT: {{ $}} 937 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = G_IMPLICIT_DEF 938 ; CHECK-NEXT: [[UMAX:%[0-9]+]]:_(<8 x s16>) = G_UMAX [[DEF]], [[DEF]] 939 ; CHECK-NEXT: [[UMAX1:%[0-9]+]]:_(<8 x s16>) = G_UMAX [[DEF]], [[DEF]] 940 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 941 ; CHECK-NEXT: G_STORE [[UMAX]](<8 x s16>), [[COPY]](p0) :: (store (<8 x s16>), align 32) 942 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 943 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) 944 ; CHECK-NEXT: G_STORE [[UMAX1]](<8 x s16>), [[PTR_ADD]](p0) :: (store (<8 x s16>) into unknown-address + 16) 945 %vec:_(<16 x s16>) = G_IMPLICIT_DEF 946 %vec1:_(<16 x s16>) = G_IMPLICIT_DEF 947 %umax:_(<16 x s16>) = G_UMAX %vec, %vec1 948 %1:_(p0) = COPY $x0 949 G_STORE %umax(<16 x s16>), %1(p0) :: (store (<16 x s16>)) 950 951... 952--- 953name: v2s32_umax 954tracksRegLiveness: true 955body: | 956 bb.0: 957 liveins: $x0 958 959 ; CHECK-LABEL: name: v2s32_umax 960 ; CHECK: liveins: $x0 961 ; CHECK-NEXT: {{ $}} 962 ; CHECK-NEXT: %vec:_(<2 x s32>) = G_IMPLICIT_DEF 963 ; CHECK-NEXT: %vec1:_(<2 x s32>) = G_IMPLICIT_DEF 964 ; CHECK-NEXT: %umax:_(<2 x s32>) = G_UMAX %vec, %vec1 965 ; CHECK-NEXT: $x0 = COPY %umax(<2 x s32>) 966 ; CHECK-NEXT: RET_ReallyLR implicit $x0 967 %vec:_(<2 x s32>) = G_IMPLICIT_DEF 968 %vec1:_(<2 x s32>) = G_IMPLICIT_DEF 969 %umax:_(<2 x s32>) = G_UMAX %vec, %vec1 970 $x0 = COPY %umax 971 RET_ReallyLR implicit $x0 972 973... 974--- 975name: v4s32_umax 976tracksRegLiveness: true 977body: | 978 bb.0: 979 liveins: $q0 980 981 ; CHECK-LABEL: name: v4s32_umax 982 ; CHECK: liveins: $q0 983 ; CHECK-NEXT: {{ $}} 984 ; CHECK-NEXT: %vec:_(<4 x s32>) = G_IMPLICIT_DEF 985 ; CHECK-NEXT: %vec1:_(<4 x s32>) = G_IMPLICIT_DEF 986 ; CHECK-NEXT: %umax:_(<4 x s32>) = G_UMAX %vec, %vec1 987 ; CHECK-NEXT: $q0 = COPY %umax(<4 x s32>) 988 ; CHECK-NEXT: RET_ReallyLR implicit $q0 989 %vec:_(<4 x s32>) = G_IMPLICIT_DEF 990 %vec1:_(<4 x s32>) = G_IMPLICIT_DEF 991 %umax:_(<4 x s32>) = G_UMAX %vec, %vec1 992 $q0 = COPY %umax 993 RET_ReallyLR implicit $q0 994 995... 996--- 997name: v8s32_umax 998tracksRegLiveness: true 999body: | 1000 bb.0: 1001 liveins: $x0, $q0, $q1 1002 1003 ; CHECK-LABEL: name: v8s32_umax 1004 ; CHECK: liveins: $x0, $q0, $q1 1005 ; CHECK-NEXT: {{ $}} 1006 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF 1007 ; CHECK-NEXT: [[UMAX:%[0-9]+]]:_(<4 x s32>) = G_UMAX [[DEF]], [[DEF]] 1008 ; CHECK-NEXT: [[UMAX1:%[0-9]+]]:_(<4 x s32>) = G_UMAX [[DEF]], [[DEF]] 1009 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 1010 ; CHECK-NEXT: G_STORE [[UMAX]](<4 x s32>), [[COPY]](p0) :: (store (<4 x s32>), align 32) 1011 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 1012 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64) 1013 ; CHECK-NEXT: G_STORE [[UMAX1]](<4 x s32>), [[PTR_ADD]](p0) :: (store (<4 x s32>) into unknown-address + 16) 1014 %vec:_(<8 x s32>) = G_IMPLICIT_DEF 1015 %vec1:_(<8 x s32>) = G_IMPLICIT_DEF 1016 %umax:_(<8 x s32>) = G_UMAX %vec, %vec1 1017 %1:_(p0) = COPY $x0 1018 G_STORE %umax(<8 x s32>), %1(p0) :: (store (<8 x s32>)) 1019 1020... 1021--- 1022name: v2s64_umax 1023tracksRegLiveness: true 1024body: | 1025 bb.0: 1026 liveins: $q0 1027 1028 ; CHECK-LABEL: name: v2s64_umax 1029 ; CHECK: liveins: $q0 1030 ; CHECK-NEXT: {{ $}} 1031 ; CHECK-NEXT: %vec:_(<2 x s64>) = G_IMPLICIT_DEF 1032 ; CHECK-NEXT: %vec1:_(<2 x s64>) = G_IMPLICIT_DEF 1033 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), %vec(<2 x s64>), %vec1 1034 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 1035 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64) 1036 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]] 1037 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND %vec, [[ICMP]] 1038 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND %vec1, [[XOR]] 1039 ; CHECK-NEXT: %umax:_(<2 x s64>) = G_OR [[AND]], [[AND1]] 1040 ; CHECK-NEXT: $q0 = COPY %umax(<2 x s64>) 1041 ; CHECK-NEXT: RET_ReallyLR implicit $q0 1042 %vec:_(<2 x s64>) = G_IMPLICIT_DEF 1043 %vec1:_(<2 x s64>) = G_IMPLICIT_DEF 1044 %umax:_(<2 x s64>) = G_UMAX %vec, %vec1 1045 $q0 = COPY %umax 1046 RET_ReallyLR implicit $q0 1047 1048... 1049--- 1050name: v4s64_umax 1051tracksRegLiveness: true 1052body: | 1053 bb.0: 1054 liveins: $x0, $q0, $q1 1055 1056 ; CHECK-LABEL: name: v4s64_umax 1057 ; CHECK: liveins: $x0, $q0, $q1 1058 ; CHECK-NEXT: {{ $}} 1059 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF 1060 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]] 1061 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1 1062 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[C]](s64), [[C]](s64) 1063 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP]], [[BUILD_VECTOR]] 1064 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP]] 1065 ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR]] 1066 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND]], [[AND1]] 1067 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s64>) = G_ICMP intpred(ugt), [[DEF]](<2 x s64>), [[DEF]] 1068 ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[ICMP1]], [[BUILD_VECTOR]] 1069 ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[ICMP1]] 1070 ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[XOR1]] 1071 ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[AND2]], [[AND3]] 1072 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 1073 ; CHECK-NEXT: G_STORE [[OR]](<2 x s64>), [[COPY]](p0) :: (store (<2 x s64>), align 32) 1074 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 16 1075 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64) 1076 ; CHECK-NEXT: G_STORE [[OR1]](<2 x s64>), [[PTR_ADD]](p0) :: (store (<2 x s64>) into unknown-address + 16) 1077 %vec:_(<4 x s64>) = G_IMPLICIT_DEF 1078 %vec1:_(<4 x s64>) = G_IMPLICIT_DEF 1079 %umax:_(<4 x s64>) = G_UMAX %vec, %vec1 1080 %1:_(p0) = COPY $x0 1081 G_STORE %umax(<4 x s64>), %1(p0) :: (store (<4 x s64>)) 1082 1083... 1084 1085