xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/legalize-combines.mir (revision 2bf4eeeeb60daba9534dd55088067fcf5a65f86b)
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -O0 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s
3
4--- |
5  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
6  target triple = "aarch64--"
7  define void @test_combines_2() { ret void }
8  define void @test_combines_3() { ret void }
9  define void @test_combines_4() { ret void }
10  define void @test_combines_5() { ret void }
11  define void @test_combines_6() { ret void }
12...
13
14---
15name:            test_combines_2
16body: |
17  bb.0:
18    liveins: $w0
19
20    ; Here the types don't match.
21    ; CHECK-LABEL: name: test_combines_2
22    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
23    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
24    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ADD]](s32)
25    ; CHECK: $w0 = COPY [[COPY]](s32)
26    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
27    ; CHECK: $x0 = COPY [[COPY1]](s64)
28    %0:_(s32) = COPY $w0
29
30    %1:_(s32) = G_ADD %0, %0
31    %2:_(s64) = G_MERGE_VALUES %0, %1
32    %3:_(s1) = G_EXTRACT %2, 0
33    %5:_(s32) = G_ANYEXT %3
34    $w0 = COPY %5
35    %4:_(s64) = COPY %2
36    $x0 = COPY %4
37...
38
39---
40name:            test_combines_3
41body: |
42  bb.0:
43    liveins: $w0
44
45    ; CHECK-LABEL: name: test_combines_3
46    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
47    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
48    ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
49    ; CHECK: $w0 = COPY [[ADD1]](s32)
50    %0:_(s32) = COPY $w0
51
52    %1:_(s32) = G_ADD %0, %0
53    %2:_(s64) = G_MERGE_VALUES %0, %1
54    %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %2
55    %5:_(s32) = G_ADD %3, %4
56    $w0 = COPY %5
57...
58
59---
60name:            test_combines_4
61body: |
62  bb.0:
63    liveins: $x0
64
65    ; CHECK-LABEL: name: test_combines_4
66    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
67    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[COPY]](s64)
68    ; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY1]], [[COPY1]]
69    ; CHECK: $x0 = COPY [[ADD]](s64)
70    %0:_(s64) = COPY $x0
71
72    %1:_(s128) = G_MERGE_VALUES %0, %0
73    %2:_(s64) = G_EXTRACT %1, 0
74    %3:_(s64) = G_ADD %2, %2
75    $x0 = COPY %3
76...
77
78---
79name:            test_combines_5
80body: |
81  bb.0:
82    liveins: $w0
83
84    ; CHECK-LABEL: name: test_combines_5
85    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
86    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
87    ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
88    ; CHECK: $w0 = COPY [[ADD1]](s32)
89    %0:_(s32) = COPY $w0
90
91    %1:_(s32) = G_ADD %0, %0
92    %2:_(s64) = G_MERGE_VALUES %0, %1
93    %6:_(s64) = COPY %2
94    %7:_(s64) = COPY %6
95    %8:_(s64) = COPY %7
96    %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %8
97    %5:_(s32) = G_ADD %3, %4
98    $w0 = COPY %5
99...
100
101---
102name:            test_combines_6
103body: |
104  bb.0:
105    liveins: $w0
106
107    ; CHECK-LABEL: name: test_combines_6
108    ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
109    ; CHECK: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY]]
110    ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ADD]](s32)
111    ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[MV]](s64)
112    ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64)
113    ; CHECK: [[ADD1:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
114    ; CHECK: $w0 = COPY [[ADD1]](s32)
115    ; CHECK: $x0 = COPY [[COPY2]](s64)
116    %0:_(s32) = COPY $w0
117
118    %1:_(s32) = G_ADD %0, %0
119    %2:_(s64) = G_MERGE_VALUES %0, %1
120    %6:_(s64) = COPY %2
121    %7:_(s64) = COPY %6
122    %8:_(s64) = COPY %7
123    %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %8
124    %5:_(s32) = G_ADD %3, %4
125    $w0 = COPY %5
126    $x0 = COPY %7
127...
128