xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/legalize-and.mir (revision a40c984976d9cfead9800132720986f73b9f442d) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -mtriple=aarch64 -run-pass=legalizer %s -o - | FileCheck %s
3---
4name:            test_scalar_and_small
5body:             |
6  bb.0.entry:
7    ; CHECK-LABEL: name: test_scalar_and_small
8    ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
9    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
10    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64)
11    ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
12    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[TRUNC]], [[TRUNC1]]
13    ; CHECK-NEXT: $w0 = COPY [[AND]](s32)
14    ; CHECK-NEXT: $x0 = COPY [[COPY]](s64)
15    %0:_(s64) = COPY $x0
16    %1:_(s64) = COPY $x1
17    %2:_(s8) = G_TRUNC %0(s64)
18    %3:_(s8) = G_TRUNC %1(s64)
19    %4:_(s8) = G_AND %2, %3
20    %6:_(s32) = G_ANYEXT %4(s8)
21    $w0 = COPY %6(s32)
22    %5:_(s64) = G_ANYEXT %2(s8)
23    $x0 = COPY %5(s64)
24
25...
26---
27name:            test_nonpow2
28body:             |
29  bb.0.entry:
30    ; CHECK-LABEL: name: test_nonpow2
31    ; CHECK: %ptr:_(p0) = COPY $x0
32    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD %ptr(p0) :: (load (s64), align 16)
33    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
34    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
35    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C1]](s64)
36    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
37    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16) from unknown-address + 8, align 8)
38    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
39    ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C2]](s64)
40    ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD1]](p0) :: (load (s8) from unknown-address + 10, align 2)
41    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
42    ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD1]](s32), [[DEF]](s32)
43    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
44    ; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[MV]], [[C3]](s64)
45    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[SHL]], [[ZEXTLOAD]]
46    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(s64) = G_OR [[C]], [[LOAD]]
47    ; CHECK-NEXT: [[OR2:%[0-9]+]]:_(s64) = G_OR [[OR]], [[C]]
48    ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:_(s64) = G_LOAD %ptr(p0) :: (load (s64), align 16)
49    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
50    ; CHECK-NEXT: [[ZEXTLOAD1:%[0-9]+]]:_(s64) = G_ZEXTLOAD [[COPY1]](p0) :: (load (s16) from unknown-address + 8, align 8)
51    ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C2]](s64)
52    ; CHECK-NEXT: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[PTR_ADD2]](p0) :: (load (s8) from unknown-address + 10, align 2)
53    ; CHECK-NEXT: [[MV1:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[LOAD3]](s32), [[DEF]](s32)
54    ; CHECK-NEXT: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[MV1]], [[C3]](s64)
55    ; CHECK-NEXT: [[OR3:%[0-9]+]]:_(s64) = G_OR [[SHL1]], [[ZEXTLOAD1]]
56    ; CHECK-NEXT: [[OR4:%[0-9]+]]:_(s64) = G_OR [[C]], [[LOAD2]]
57    ; CHECK-NEXT: [[OR5:%[0-9]+]]:_(s64) = G_OR [[OR3]], [[C]]
58    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[OR1]], [[OR4]]
59    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[OR2]], [[OR5]]
60    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY [[AND]](s64)
61    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[AND1]](s64)
62    ; CHECK-NEXT: G_STORE [[COPY2]](s64), %ptr(p0) :: (store (s64), align 16)
63    ; CHECK-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[TRUNC]], [[C3]](s64)
64    ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C2]](s64)
65    ; CHECK-NEXT: G_STORE [[TRUNC]](s32), [[PTR_ADD]](p0) :: (store (s16) into unknown-address + 8, align 8)
66    ; CHECK-NEXT: G_STORE [[LSHR]](s32), [[PTR_ADD3]](p0) :: (store (s8) into unknown-address + 10, align 2)
67    %ptr:_(p0) = COPY $x0
68    %a:_(s88) = G_LOAD %ptr(p0) :: (load (s88))
69    %b:_(s88) = G_LOAD %ptr(p0) :: (load (s88))
70    %and:_(s88) = G_AND %a, %b
71    G_STORE %and(s88), %ptr(p0) :: (store (s88))
72...
73---
74name:            test_s318_and
75tracksRegLiveness: true
76body:             |
77  bb.0:
78    liveins: $x0
79
80    ; CHECK-LABEL: name: test_s318_and
81    ; CHECK: liveins: $x0
82    ; CHECK-NEXT: {{  $}}
83    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
84    ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
85    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
86    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
87    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
88    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
89    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
90    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
91    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4611686018427387903
92    ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C]]
93    ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[AND1]], [[C]]
94    ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[AND2]], [[C]]
95    ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[AND3]], [[C]]
96    ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[AND4]], [[C1]]
97    ; CHECK-NEXT: G_STORE [[AND5]](s64), %ptr(p0) :: (store (s64), align 64)
98    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
99    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C2]](s64)
100    ; CHECK-NEXT: G_STORE [[AND6]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
101    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
102    ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C3]](s64)
103    ; CHECK-NEXT: G_STORE [[AND7]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
104    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
105    ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C4]](s64)
106    ; CHECK-NEXT: G_STORE [[AND8]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
107    ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
108    ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C5]](s64)
109    ; CHECK-NEXT: G_STORE [[AND9]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
110    ; CHECK-NEXT: RET_ReallyLR implicit $x0
111    %a:_(s318) = G_IMPLICIT_DEF
112    %b:_(s318) = G_IMPLICIT_DEF
113    %ptr:_(p0) = COPY $x0
114    %and:_(s318) = G_AND %a, %b
115    G_STORE %and(s318), %ptr(p0) :: (store (s318))
116    RET_ReallyLR implicit $x0
117...
118---
119name:            test_s158_and
120tracksRegLiveness: true
121body:             |
122  bb.0:
123    liveins: $x0
124    ; CHECK-LABEL: name: test_s158_and
125    ; CHECK: liveins: $x0
126    ; CHECK-NEXT: {{  $}}
127    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
128    ; CHECK-NEXT: %ptr:_(p0) = COPY $x0
129    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
130    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
131    ; CHECK-NEXT: [[AND2:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
132    ; CHECK-NEXT: [[AND3:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
133    ; CHECK-NEXT: [[AND4:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
134    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -1
135    ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4611686018427387903
136    ; CHECK-NEXT: [[AND5:%[0-9]+]]:_(s64) = G_AND [[AND]], [[C]]
137    ; CHECK-NEXT: [[AND6:%[0-9]+]]:_(s64) = G_AND [[AND1]], [[C]]
138    ; CHECK-NEXT: [[AND7:%[0-9]+]]:_(s64) = G_AND [[AND2]], [[C]]
139    ; CHECK-NEXT: [[AND8:%[0-9]+]]:_(s64) = G_AND [[AND3]], [[C]]
140    ; CHECK-NEXT: [[AND9:%[0-9]+]]:_(s64) = G_AND [[AND4]], [[C1]]
141    ; CHECK-NEXT: G_STORE [[AND5]](s64), %ptr(p0) :: (store (s64), align 64)
142    ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
143    ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C2]](s64)
144    ; CHECK-NEXT: G_STORE [[AND6]](s64), [[PTR_ADD]](p0) :: (store (s64) into unknown-address + 8)
145    ; CHECK-NEXT: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
146    ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C3]](s64)
147    ; CHECK-NEXT: G_STORE [[AND7]](s64), [[PTR_ADD1]](p0) :: (store (s64) into unknown-address + 16, align 16)
148    ; CHECK-NEXT: [[C4:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
149    ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C4]](s64)
150    ; CHECK-NEXT: G_STORE [[AND8]](s64), [[PTR_ADD2]](p0) :: (store (s64) into unknown-address + 24)
151    ; CHECK-NEXT: [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 32
152    ; CHECK-NEXT: [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD %ptr, [[C5]](s64)
153    ; CHECK-NEXT: G_STORE [[AND9]](s64), [[PTR_ADD3]](p0) :: (store (s64) into unknown-address + 32, align 32)
154    ; CHECK-NEXT: RET_ReallyLR implicit $x0
155    %a:_(s318) = G_IMPLICIT_DEF
156    %b:_(s318) = G_IMPLICIT_DEF
157    %ptr:_(p0) = COPY $x0
158    %and:_(s318) = G_AND %a, %b
159    G_STORE %and(s318), %ptr(p0) :: (store (s318))
160    RET_ReallyLR implicit $x0
161
162...
163---
164name:            test_vector_and_v16s16
165body:             |
166  bb.0.entry:
167    ; CHECK-LABEL: name: test_vector_and_v16s16
168    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
169    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s16>) = COPY $q1
170    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s16>) = G_AND [[COPY]], [[COPY]]
171    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<8 x s16>) = G_AND [[COPY1]], [[COPY1]]
172    ; CHECK-NEXT: $q0 = COPY [[AND]](<8 x s16>)
173    ; CHECK-NEXT: $q1 = COPY [[AND1]](<8 x s16>)
174    %1:_(<8 x s16>) = COPY $q0
175    %2:_(<8 x s16>) = COPY $q1
176    %0:_(<16 x s16>) = G_CONCAT_VECTORS %1(<8 x s16>), %2(<8 x s16>)
177    %3:_(<16 x s16>) = G_AND %0, %0
178    %4:_(<8 x s16>), %5:_(<8 x s16>) = G_UNMERGE_VALUES %3(<16 x s16>)
179    $q0 = COPY %4(<8 x s16>)
180    $q1 = COPY %5(<8 x s16>)
181
182...
183---
184name:            test_vector_and_v32s8
185body:             |
186  bb.0.entry:
187    ; CHECK-LABEL: name: test_vector_and_v32s8
188    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
189    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
190    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x s8>) = G_AND [[COPY]], [[COPY]]
191    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<16 x s8>) = G_AND [[COPY1]], [[COPY1]]
192    ; CHECK-NEXT: $q0 = COPY [[AND]](<16 x s8>)
193    ; CHECK-NEXT: $q1 = COPY [[AND1]](<16 x s8>)
194    %0:_(<16 x s8>) = COPY $q0
195    %1:_(<16 x s8>) = COPY $q1
196    %2:_(<32 x s8>) = G_CONCAT_VECTORS %0, %1
197    %3:_(<32 x s8>) = G_AND %2, %2
198    %7:_(<16 x s8>), %8:_(<16 x s8>) = G_UNMERGE_VALUES %3(<32 x s8>)
199    $q0 = COPY %7(<16 x s8>)
200    $q1 = COPY %8(<16 x s8>)
201
202...
203---
204name:            and_v2s1
205tracksRegLiveness: true
206body:             |
207  bb.1:
208    liveins: $d0, $d1, $d2, $d3
209
210    ; CHECK-LABEL: name: and_v2s1
211    ; CHECK: liveins: $d0, $d1, $d2, $d3
212    ; CHECK-NEXT: {{  $}}
213    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
214    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1
215    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<2 x s32>) = COPY $d2
216    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<2 x s32>) = COPY $d3
217    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY]](<2 x s32>), [[COPY1]]
218    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<2 x s32>) = G_ICMP intpred(eq), [[COPY2]](<2 x s32>), [[COPY3]]
219    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s32>) = G_AND [[ICMP]], [[ICMP1]]
220    ; CHECK-NEXT: $d0 = COPY [[AND]](<2 x s32>)
221    ; CHECK-NEXT: RET_ReallyLR implicit $d0
222    %0:_(<2 x s32>) = COPY $d0
223    %1:_(<2 x s32>) = COPY $d1
224    %2:_(<2 x s32>) = COPY $d2
225    %3:_(<2 x s32>) = COPY $d3
226    %4:_(<2 x s1>) = G_ICMP intpred(eq), %0(<2 x s32>), %1
227    %5:_(<2 x s1>) = G_ICMP intpred(eq), %2(<2 x s32>), %3
228    %6:_(<2 x s1>) = G_AND %4, %5
229    %7:_(<2 x s32>) = G_ANYEXT %6
230    $d0 = COPY %7:_(<2 x s32>)
231    RET_ReallyLR implicit $d0
232...
233---
234name:            and_v3s1
235tracksRegLiveness: true
236body:             |
237  bb.1:
238    liveins: $b0, $b1, $b2
239
240    ; CHECK-LABEL: name: and_v3s1
241    ; CHECK: liveins: $b0, $b1, $b2
242    ; CHECK-NEXT: {{  $}}
243    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s8) = COPY $b0
244    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s8) = COPY $b1
245    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s8) = COPY $b2
246    ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY]](s8)
247    ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY1]](s8)
248    ; CHECK-NEXT: [[ANYEXT2:%[0-9]+]]:_(s16) = G_ANYEXT [[COPY2]](s8)
249    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
250    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[ANYEXT]](s16), [[ANYEXT1]](s16), [[ANYEXT2]](s16), [[DEF]](s16)
251    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[BUILD_VECTOR]], [[BUILD_VECTOR]]
252    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[AND]](<4 x s16>)
253    ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[UV]](s16)
254    ; CHECK-NEXT: $b0 = COPY [[TRUNC]](s8)
255    ; CHECK-NEXT: RET_ReallyLR implicit $b0
256    %1:_(s8) = COPY $b0
257    %2:_(s8) = COPY $b1
258    %3:_(s8) = COPY $b2
259    %4:_(<3 x s8>) = G_BUILD_VECTOR %1(s8), %2(s8), %3(s8)
260    %0:_(<3 x s1>) = G_TRUNC %4(<3 x s8>)
261    %5:_(<3 x s1>) = G_AND %0, %0
262    %7:_(<3 x s8>) = G_ANYEXT %5(<3 x s1>)
263    %8:_(s8), %9:_(s8), %10:_(s8) = G_UNMERGE_VALUES %7(<3 x s8>)
264    $b0 = COPY %8:_(s8)
265    RET_ReallyLR implicit $b0
266...
267---
268name:            and_v4s1
269tracksRegLiveness: true
270body:             |
271  bb.1:
272    liveins: $d0, $d1, $d2, $d3
273
274    ; CHECK-LABEL: name: and_v4s1
275    ; CHECK: liveins: $d0, $d1, $d2, $d3
276    ; CHECK-NEXT: {{  $}}
277    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
278    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s16>) = COPY $d1
279    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<4 x s16>) = COPY $d2
280    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<4 x s16>) = COPY $d3
281    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY]](<4 x s16>), [[COPY1]]
282    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<4 x s16>) = G_ICMP intpred(eq), [[COPY2]](<4 x s16>), [[COPY3]]
283    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s16>) = G_AND [[ICMP]], [[ICMP1]]
284    ; CHECK-NEXT: $d0 = COPY [[AND]](<4 x s16>)
285    ; CHECK-NEXT: RET_ReallyLR implicit $d0
286    %0:_(<4 x s16>) = COPY $d0
287    %1:_(<4 x s16>) = COPY $d1
288    %2:_(<4 x s16>) = COPY $d2
289    %3:_(<4 x s16>) = COPY $d3
290    %4:_(<4 x s1>) = G_ICMP intpred(eq), %0(<4 x s16>), %1
291    %5:_(<4 x s1>) = G_ICMP intpred(eq), %2(<4 x s16>), %3
292    %6:_(<4 x s1>) = G_AND %4, %5
293    %7:_(<4 x s16>) = G_ANYEXT %6
294    $d0 = COPY %7:_(<4 x s16>)
295    RET_ReallyLR implicit $d0
296...
297---
298name:            and_v8s1
299tracksRegLiveness: true
300body:             |
301  bb.1:
302    liveins: $d0, $d1, $d2, $d3
303
304    ; CHECK-LABEL: name: and_v8s1
305    ; CHECK: liveins: $d0, $d1, $d2, $d3
306    ; CHECK-NEXT: {{  $}}
307    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
308    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
309    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<8 x s8>) = COPY $d2
310    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<8 x s8>) = COPY $d3
311    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY]](<8 x s8>), [[COPY1]]
312    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<8 x s8>) = G_ICMP intpred(eq), [[COPY2]](<8 x s8>), [[COPY3]]
313    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s8>) = G_AND [[ICMP]], [[ICMP1]]
314    ; CHECK-NEXT: $d0 = COPY [[AND]](<8 x s8>)
315    ; CHECK-NEXT: RET_ReallyLR implicit $d0
316    %0:_(<8 x s8>) = COPY $d0
317    %1:_(<8 x s8>) = COPY $d1
318    %2:_(<8 x s8>) = COPY $d2
319    %3:_(<8 x s8>) = COPY $d3
320    %4:_(<8 x s1>) = G_ICMP intpred(eq), %0(<8 x s8>), %1
321    %5:_(<8 x s1>) = G_ICMP intpred(eq), %2(<8 x s8>), %3
322    %6:_(<8 x s1>) = G_AND %4, %5
323    %7:_(<8 x s8>) = G_ANYEXT %6
324    $d0 = COPY %7:_(<8 x s8>)
325    RET_ReallyLR implicit $d0
326...
327---
328name:            and_v16s1
329tracksRegLiveness: true
330body:             |
331  bb.1:
332    liveins: $q0, $q1, $q2, $q3
333
334    ; CHECK-LABEL: name: and_v16s1
335    ; CHECK: liveins: $q0, $q1, $q2, $q3
336    ; CHECK-NEXT: {{  $}}
337    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
338    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s8>) = COPY $q1
339    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(<16 x s8>) = COPY $q2
340    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(<16 x s8>) = COPY $q3
341    ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY]](<16 x s8>), [[COPY1]]
342    ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:_(<16 x s8>) = G_ICMP intpred(eq), [[COPY2]](<16 x s8>), [[COPY3]]
343    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x s8>) = G_AND [[ICMP]], [[ICMP1]]
344    ; CHECK-NEXT: $q0 = COPY [[AND]](<16 x s8>)
345    ; CHECK-NEXT: RET_ReallyLR implicit $q0
346    %0:_(<16 x s8>) = COPY $q0
347    %1:_(<16 x s8>) = COPY $q1
348    %2:_(<16 x s8>) = COPY $q2
349    %3:_(<16 x s8>) = COPY $q3
350    %4:_(<16 x s1>) = G_ICMP intpred(eq), %0(<16 x s8>), %1
351    %5:_(<16 x s1>) = G_ICMP intpred(eq), %2(<16 x s8>), %3
352    %6:_(<16 x s1>) = G_AND %4, %5
353    %7:_(<16 x s8>) = G_ANYEXT %6
354    $q0 = COPY %7:_(<16 x s8>)
355    RET_ReallyLR implicit $q0
356...
357