1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 2; RUN: llc -mtriple=aarch64-linux-gnu -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - 2>&1 | FileCheck %s 3 4define i32 @call_nneg(i16 %a) { 5 ; CHECK-LABEL: name: call_nneg 6 ; CHECK: bb.1.entry: 7 ; CHECK-NEXT: liveins: $w0 8 ; CHECK-NEXT: {{ $}} 9 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 10 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 11 ; CHECK-NEXT: %2:_(s32) = nneg G_ZEXT [[TRUNC]](s16) 12 ; CHECK-NEXT: $w0 = COPY %2(s32) 13 ; CHECK-NEXT: RET_ReallyLR implicit $w0 14entry: 15 %result = zext nneg i16 %a to i32 16 ret i32 %result 17} 18 19define i32 @call_not_nneg(i16 %a) { 20 ; CHECK-LABEL: name: call_not_nneg 21 ; CHECK: bb.1.entry: 22 ; CHECK-NEXT: liveins: $w0 23 ; CHECK-NEXT: {{ $}} 24 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 25 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) 26 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[TRUNC]](s16) 27 ; CHECK-NEXT: $w0 = COPY [[ZEXT]](s32) 28 ; CHECK-NEXT: RET_ReallyLR implicit $w0 29entry: 30 %result = zext i16 %a to i32 31 ret i32 %result 32} 33 34define i32 @call_disjoint(i32 %a, i32 %b) { 35 ; CHECK-LABEL: name: call_disjoint 36 ; CHECK: bb.1.entry: 37 ; CHECK-NEXT: liveins: $w0, $w1 38 ; CHECK-NEXT: {{ $}} 39 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 40 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 41 ; CHECK-NEXT: %2:_(s32) = disjoint G_OR [[COPY]], [[COPY1]] 42 ; CHECK-NEXT: $w0 = COPY %2(s32) 43 ; CHECK-NEXT: RET_ReallyLR implicit $w0 44entry: 45 %result = or disjoint i32 %a, %b 46 ret i32 %result 47} 48 49define i32 @call_add(i32 %a, i32 %b) { 50 ; CHECK-LABEL: name: call_add 51 ; CHECK: bb.1.entry: 52 ; CHECK-NEXT: liveins: $w0, $w1 53 ; CHECK-NEXT: {{ $}} 54 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 55 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 56 ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = nsw G_ADD [[COPY]], [[COPY1]] 57 ; CHECK-NEXT: $w0 = COPY [[ADD]](s32) 58 ; CHECK-NEXT: RET_ReallyLR implicit $w0 59entry: 60 %result = add nsw i32 %a, %b 61 ret i32 %result 62} 63 64define i32 @call_not_disjoint(i32 %a, i32 %b) { 65 ; CHECK-LABEL: name: call_not_disjoint 66 ; CHECK: bb.1.entry: 67 ; CHECK-NEXT: liveins: $w0, $w1 68 ; CHECK-NEXT: {{ $}} 69 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 70 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1 71 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]] 72 ; CHECK-NEXT: $w0 = COPY [[OR]](s32) 73 ; CHECK-NEXT: RET_ReallyLR implicit $w0 74entry: 75 %result = or i32 %a, %b 76 ret i32 %result 77} 78 79define <2 x i64> @call_not_disjoint_vector(<2 x i64> %a, <2 x i64> %b) { 80 ; CHECK-LABEL: name: call_not_disjoint_vector 81 ; CHECK: bb.1.entry: 82 ; CHECK-NEXT: liveins: $q0, $q1 83 ; CHECK-NEXT: {{ $}} 84 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 85 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 86 ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[COPY]], [[COPY1]] 87 ; CHECK-NEXT: $q0 = COPY [[OR]](<2 x s64>) 88 ; CHECK-NEXT: RET_ReallyLR implicit $q0 89entry: 90 %result = or <2 x i64> %a, %b 91 ret <2 x i64> %result 92} 93 94define <2 x i64> @call_disjoint_vector(<2 x i64> %a, <2 x i64> %b) { 95 ; CHECK-LABEL: name: call_disjoint_vector 96 ; CHECK: bb.1.entry: 97 ; CHECK-NEXT: liveins: $q0, $q1 98 ; CHECK-NEXT: {{ $}} 99 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0 100 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1 101 ; CHECK-NEXT: %2:_(<2 x s64>) = disjoint G_OR [[COPY]], [[COPY1]] 102 ; CHECK-NEXT: $q0 = COPY %2(<2 x s64>) 103 ; CHECK-NEXT: RET_ReallyLR implicit $q0 104entry: 105 %result = or disjoint <2 x i64> %a, %b 106 ret <2 x i64> %result 107} 108 109define <2 x i64> @call_nneg_vector(<2 x i32> %a) { 110 ; CHECK-LABEL: name: call_nneg_vector 111 ; CHECK: bb.1.entry: 112 ; CHECK-NEXT: liveins: $d0 113 ; CHECK-NEXT: {{ $}} 114 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 115 ; CHECK-NEXT: %1:_(<2 x s64>) = nneg G_ZEXT [[COPY]](<2 x s32>) 116 ; CHECK-NEXT: $q0 = COPY %1(<2 x s64>) 117 ; CHECK-NEXT: RET_ReallyLR implicit $q0 118entry: 119 %result = zext nneg <2 x i32> %a to <2 x i64> 120 ret <2 x i64> %result 121} 122 123define <2 x i64> @call_not_nneg_vector(<2 x i32> %a) { 124 ; CHECK-LABEL: name: call_not_nneg_vector 125 ; CHECK: bb.1.entry: 126 ; CHECK-NEXT: liveins: $d0 127 ; CHECK-NEXT: {{ $}} 128 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0 129 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<2 x s64>) = G_ZEXT [[COPY]](<2 x s32>) 130 ; CHECK-NEXT: $q0 = COPY [[ZEXT]](<2 x s64>) 131 ; CHECK-NEXT: RET_ReallyLR implicit $q0 132entry: 133 %result = zext <2 x i32> %a to <2 x i64> 134 ret <2 x i64> %result 135} 136