1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py 2# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s 3--- | 4 target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" 5 6 define void @sdiv_exact() { ret void } 7 define void @sdiv_noexact() { ret void } 8 define void @sdiv_exact_minsize() #0 { ret void } 9 define void @div_v4s32() { ret void } 10 define void @div_v4s32_splat() { ret void } 11 12 attributes #0 = { minsize } 13 14... 15--- 16name: sdiv_exact 17body: | 18 bb.1: 19 liveins: $w0 20 21 ; CHECK-LABEL: name: sdiv_exact 22 ; CHECK: liveins: $w0 23 ; CHECK-NEXT: {{ $}} 24 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 25 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 26 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -991146299 27 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(s32) = exact G_ASHR [[COPY]], [[C]](s32) 28 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(s32) = G_MUL [[ASHR]], [[C1]] 29 ; CHECK-NEXT: $w0 = COPY [[MUL]](s32) 30 ; CHECK-NEXT: RET_ReallyLR implicit $w0 31 %0:_(s32) = COPY $w0 32 %1:_(s32) = G_CONSTANT i32 104 33 %2:_(s32) = exact G_SDIV %0, %1 34 $w0 = COPY %2(s32) 35 RET_ReallyLR implicit $w0 36 37... 38--- 39name: sdiv_noexact 40body: | 41 bb.1: 42 liveins: $w0 43 44 ; CHECK-LABEL: name: sdiv_noexact 45 ; CHECK: liveins: $w0 46 ; CHECK-NEXT: {{ $}} 47 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 48 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 104 49 ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = G_SDIV [[COPY]], [[C]] 50 ; CHECK-NEXT: $w0 = COPY [[SDIV]](s32) 51 ; CHECK-NEXT: RET_ReallyLR implicit $w0 52 %0:_(s32) = COPY $w0 53 %1:_(s32) = G_CONSTANT i32 104 54 %2:_(s32) = G_SDIV %0, %1 55 $w0 = COPY %2(s32) 56 RET_ReallyLR implicit $w0 57 58... 59--- 60name: sdiv_exact_minsize 61body: | 62 bb.1: 63 liveins: $w0 64 65 ; CHECK-LABEL: name: sdiv_exact_minsize 66 ; CHECK: liveins: $w0 67 ; CHECK-NEXT: {{ $}} 68 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0 69 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 104 70 ; CHECK-NEXT: [[SDIV:%[0-9]+]]:_(s32) = exact G_SDIV [[COPY]], [[C]] 71 ; CHECK-NEXT: $w0 = COPY [[SDIV]](s32) 72 ; CHECK-NEXT: RET_ReallyLR implicit $w0 73 %0:_(s32) = COPY $w0 74 %1:_(s32) = G_CONSTANT i32 104 75 %2:_(s32) = exact G_SDIV %0, %1 76 $w0 = COPY %2(s32) 77 RET_ReallyLR implicit $w0 78 79... 80--- 81name: div_v4s32 82body: | 83 bb.1: 84 liveins: $q0 85 86 ; CHECK-LABEL: name: div_v4s32 87 ; CHECK: liveins: $q0 88 ; CHECK-NEXT: {{ $}} 89 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 90 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 91 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -991146299 92 ; CHECK-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 954437177 93 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32) 94 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C2]](s32), [[C1]](s32), [[C2]](s32) 95 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(<4 x s32>) = exact G_ASHR [[COPY]], [[BUILD_VECTOR]](<4 x s32>) 96 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[ASHR]], [[BUILD_VECTOR1]] 97 ; CHECK-NEXT: $q0 = COPY [[MUL]](<4 x s32>) 98 ; CHECK-NEXT: RET_ReallyLR implicit $q0 99 %0:_(<4 x s32>) = COPY $q0 100 %c1:_(s32) = G_CONSTANT i32 104 101 %c2:_(s32) = G_CONSTANT i32 72 102 %1:_(<4 x s32>) = G_BUILD_VECTOR %c1(s32), %c2(s32), %c1(s32), %c2(s32) 103 %3:_(<4 x s32>) = exact G_SDIV %0, %1 104 $q0 = COPY %3(<4 x s32>) 105 RET_ReallyLR implicit $q0 106 107... 108--- 109name: div_v4s32_splat 110body: | 111 bb.1: 112 liveins: $q0 113 114 ; CHECK-LABEL: name: div_v4s32_splat 115 ; CHECK: liveins: $q0 116 ; CHECK-NEXT: {{ $}} 117 ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0 118 ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 3 119 ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 -991146299 120 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32) 121 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C1]](s32), [[C1]](s32), [[C1]](s32), [[C1]](s32) 122 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:_(<4 x s32>) = exact G_ASHR [[COPY]], [[BUILD_VECTOR]](<4 x s32>) 123 ; CHECK-NEXT: [[MUL:%[0-9]+]]:_(<4 x s32>) = G_MUL [[ASHR]], [[BUILD_VECTOR1]] 124 ; CHECK-NEXT: $q0 = COPY [[MUL]](<4 x s32>) 125 ; CHECK-NEXT: RET_ReallyLR implicit $q0 126 %0:_(<4 x s32>) = COPY $q0 127 %c1:_(s32) = G_CONSTANT i32 104 128 %1:_(<4 x s32>) = G_BUILD_VECTOR %c1(s32), %c1(s32), %c1(s32), %c1(s32) 129 %3:_(<4 x s32>) = exact G_SDIV %0, %1 130 $q0 = COPY %3(<4 x s32>) 131 RET_ReallyLR implicit $q0 132 133... 134