xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/combine-add.mir (revision 14dc97df5ef3a9178fc4175303f0f86ed4e3f98e) 
1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2# RUN: llc -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s
3
4---
5name:            add_lhs_sub_reg
6alignment:       4
7tracksRegLiveness: true
8frameInfo:
9  maxAlignment:    1
10machineFunctionInfo: {}
11body:             |
12  bb.0:
13    liveins: $w0, $w1
14    ; CHECK-LABEL: name: add_lhs_sub_reg
15    ; CHECK: liveins: $w0, $w1
16    ; CHECK-NEXT: {{  $}}
17    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
18    ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
19    %0:_(s32) = COPY $w0
20    %1:_(s32) = COPY $w1
21    %2:_(s32) = G_SUB %0, %1
22    %3:_(s32) = G_ADD %2, %1
23    $w0 = COPY %3
24...
25---
26name:            add_lhs_sub_reg_wide
27alignment:       4
28tracksRegLiveness: true
29frameInfo:
30  maxAlignment:    1
31machineFunctionInfo: {}
32body:             |
33  bb.0:
34    liveins: $q0, $q1
35    ; CHECK-LABEL: name: add_lhs_sub_reg_wide
36    ; CHECK: liveins: $q0, $q1
37    ; CHECK-NEXT: {{  $}}
38    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $q0
39    ; CHECK-NEXT: $q0 = COPY [[COPY]](s128)
40    %0:_(s128) = COPY $q0
41    %1:_(s128) = COPY $q1
42    %2:_(s128) = G_SUB %0, %1
43    %3:_(s128) = G_ADD %2, %1
44    $q0 = COPY %3
45...
46---
47name:            add_lhs_sub_reg_vec
48alignment:       4
49tracksRegLiveness: true
50frameInfo:
51  maxAlignment:    1
52machineFunctionInfo: {}
53body:             |
54  bb.0:
55    liveins: $x0, $x1
56    ; CHECK-LABEL: name: add_lhs_sub_reg_vec
57    ; CHECK: liveins: $x0, $x1
58    ; CHECK-NEXT: {{  $}}
59    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $x0
60    ; CHECK-NEXT: $x0 = COPY [[COPY]](<4 x s16>)
61    %0:_(<4 x s16>) = COPY $x0
62    %1:_(<4 x s16>) = COPY $x1
63    %2:_(<4 x s16>) = G_SUB %0, %1
64    %3:_(<4 x s16>) = G_ADD %2, %1
65    $x0 = COPY %3
66...
67---
68name:            add_rhs_sub_reg
69alignment:       4
70tracksRegLiveness: true
71frameInfo:
72  maxAlignment:    1
73machineFunctionInfo: {}
74body:             |
75  bb.0:
76    liveins: $w0, $w1
77    ; CHECK-LABEL: name: add_rhs_sub_reg
78    ; CHECK: liveins: $w0, $w1
79    ; CHECK-NEXT: {{  $}}
80    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
81    ; CHECK-NEXT: $w0 = COPY [[COPY]](s32)
82    %0:_(s32) = COPY $w0
83    %1:_(s32) = COPY $w1
84    %2:_(s32) = G_SUB %0, %1
85    %3:_(s32) = G_ADD %1, %2
86    $w0 = COPY %3
87...
88---
89name:            add_rhs_sub_reg_wide
90alignment:       4
91tracksRegLiveness: true
92frameInfo:
93  maxAlignment:    1
94machineFunctionInfo: {}
95body:             |
96  bb.0:
97    liveins: $q0, $q1
98    ; CHECK-LABEL: name: add_rhs_sub_reg_wide
99    ; CHECK: liveins: $q0, $q1
100    ; CHECK-NEXT: {{  $}}
101    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s128) = COPY $q0
102    ; CHECK-NEXT: $q0 = COPY [[COPY]](s128)
103    %0:_(s128) = COPY $q0
104    %1:_(s128) = COPY $q1
105    %2:_(s128) = G_SUB %0, %1
106    %3:_(s128) = G_ADD %1, %2
107    $q0 = COPY %3
108...
109---
110name:            add_rhs_sub_reg_vec
111alignment:       4
112tracksRegLiveness: true
113frameInfo:
114  maxAlignment:    1
115machineFunctionInfo: {}
116body:             |
117  bb.0:
118    liveins: $x0, $x1
119    ; CHECK-LABEL: name: add_rhs_sub_reg_vec
120    ; CHECK: liveins: $x0, $x1
121    ; CHECK-NEXT: {{  $}}
122    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $x0
123    ; CHECK-NEXT: $x0 = COPY [[COPY]](<4 x s16>)
124    %0:_(<4 x s16>) = COPY $x0
125    %1:_(<4 x s16>) = COPY $x1
126    %2:_(<4 x s16>) = G_SUB %0, %1
127    %3:_(<4 x s16>) = G_ADD %1, %2
128    $x0 = COPY %3
129...
130---
131name:            fadd_by_zero
132tracksRegLiveness: true
133body:             |
134  bb.0:
135    liveins: $d0
136    ; CHECK-LABEL: name: fadd_by_zero
137    ; CHECK: liveins: $d0
138    ; CHECK-NEXT: {{  $}}
139    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
140    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0.000000e+00
141    ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s64) = G_FADD [[COPY]], [[C]]
142    ; CHECK-NEXT: $d0 = COPY [[FADD]](s64)
143    %0:_(s64) = COPY $d0
144    %1:_(s64) = G_FCONSTANT double 0.000000e+00
145    %2:_(s64) = G_FADD %0, %1(s64)
146    $d0 = COPY %2(s64)
147...
148---
149name:            fadd_vector_by_zero
150alignment:       4
151tracksRegLiveness: true
152frameInfo:
153  maxAlignment:    1
154machineFunctionInfo: {}
155body:             |
156  bb.0:
157    liveins: $q0
158    ; CHECK-LABEL: name: fadd_vector_by_zero
159    ; CHECK: liveins: $q0
160    ; CHECK-NEXT: {{  $}}
161    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
162    ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00
163    ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[C]](s32), [[C]](s32), [[C]](s32), [[C]](s32)
164    ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(<4 x s32>) = G_FADD [[COPY]], [[BUILD_VECTOR]]
165    ; CHECK-NEXT: $q0 = COPY [[FADD]](<4 x s32>)
166    %0:_(<4 x s32>) = COPY $q0
167    %1:_(s32) = G_FCONSTANT float 0.0
168    %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)
169    %3:_(<4 x s32>) = G_FADD %0, %2(<4 x s32>)
170    $q0 = COPY %3(<4 x s32>)
171...
172
173---
174name:            fadd_by_neg_zero
175tracksRegLiveness: true
176body:             |
177  bb.0:
178    liveins: $d0
179    ; CHECK-LABEL: name: fadd_by_neg_zero
180    ; CHECK: liveins: $d0
181    ; CHECK-NEXT: {{  $}}
182    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0
183    ; CHECK-NEXT: $d0 = COPY [[COPY]](s64)
184    %0:_(s64) = COPY $d0
185    %1:_(s64) = G_FCONSTANT double -0.000000e+00
186    %2:_(s64) = G_FADD %0, %1(s64)
187    $d0 = COPY %2(s64)
188...
189---
190name:            fadd_vector_by_neg_zero
191alignment:       4
192tracksRegLiveness: true
193frameInfo:
194  maxAlignment:    1
195machineFunctionInfo: {}
196body:             |
197  bb.0:
198    liveins: $q0
199    ; CHECK-LABEL: name: fadd_vector_by_neg_zero
200    ; CHECK: liveins: $q0
201    ; CHECK-NEXT: {{  $}}
202    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
203    ; CHECK-NEXT: $q0 = COPY [[COPY]](<4 x s32>)
204    %0:_(<4 x s32>) = COPY $q0
205    %1:_(s32) = G_FCONSTANT float -0.0
206    %2:_(<4 x s32>) = G_BUILD_VECTOR %1(s32), %1(s32), %1(s32), %1(s32)
207    %3:_(<4 x s32>) = G_FADD %0, %2(<4 x s32>)
208    $q0 = COPY %3(<4 x s32>)
209...
210---
211name:            saddl_v8i8_v8i32
212tracksRegLiveness: true
213body:             |
214  bb.1:
215    liveins: $d0, $d1
216
217    ; CHECK-LABEL: name: saddl_v8i8_v8i32
218    ; CHECK: liveins: $d0, $d1
219    ; CHECK-NEXT: {{  $}}
220    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
221    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
222    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
223    ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY1]](<8 x s8>)
224    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[SEXT]], [[SEXT1]]
225    ; CHECK-NEXT: [[SEXT2:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[ADD]](<8 x s16>)
226    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SEXT2]](<8 x s32>)
227    ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
228    ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
229    ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
230    %0:_(<8 x s8>) = COPY $d0
231    %1:_(<8 x s8>) = COPY $d1
232    %2:_(<8 x s32>) = G_SEXT %0(<8 x s8>)
233    %3:_(<8 x s32>) = G_SEXT %1(<8 x s8>)
234    %4:_(<8 x s32>) = G_ADD %2, %3
235    %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
236    $q0 = COPY %5(<4 x s32>)
237    $q1 = COPY %6(<4 x s32>)
238    RET_ReallyLR implicit $q0, implicit $q1
239...
240
241---
242name:            uaddl_v8i8_v8i32
243tracksRegLiveness: true
244body:             |
245  bb.1:
246    liveins: $d0, $d1
247
248    ; CHECK-LABEL: name: uaddl_v8i8_v8i32
249    ; CHECK: liveins: $d0, $d1
250    ; CHECK-NEXT: {{  $}}
251    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
252    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
253    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
254    ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY1]](<8 x s8>)
255    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<8 x s16>) = G_ADD [[ZEXT]], [[ZEXT1]]
256    ; CHECK-NEXT: [[ZEXT2:%[0-9]+]]:_(<8 x s32>) = G_ZEXT [[ADD]](<8 x s16>)
257    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[ZEXT2]](<8 x s32>)
258    ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
259    ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
260    ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
261    %0:_(<8 x s8>) = COPY $d0
262    %1:_(<8 x s8>) = COPY $d1
263    %2:_(<8 x s32>) = G_ZEXT %0(<8 x s8>)
264    %3:_(<8 x s32>) = G_ZEXT %1(<8 x s8>)
265    %4:_(<8 x s32>) = G_ADD %2, %3
266    %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
267    $q0 = COPY %5(<4 x s32>)
268    $q1 = COPY %6(<4 x s32>)
269    RET_ReallyLR implicit $q0, implicit $q1
270...
271
272---
273name:            ssubl_v8i8_v8i32
274tracksRegLiveness: true
275body:             |
276  bb.1:
277    liveins: $d0, $d1
278
279    ; CHECK-LABEL: name: ssubl_v8i8_v8i32
280    ; CHECK: liveins: $d0, $d1
281    ; CHECK-NEXT: {{  $}}
282    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
283    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
284    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY]](<8 x s8>)
285    ; CHECK-NEXT: [[SEXT1:%[0-9]+]]:_(<8 x s16>) = G_SEXT [[COPY1]](<8 x s8>)
286    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[SEXT]], [[SEXT1]]
287    ; CHECK-NEXT: [[SEXT2:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[SUB]](<8 x s16>)
288    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SEXT2]](<8 x s32>)
289    ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
290    ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
291    ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
292    %0:_(<8 x s8>) = COPY $d0
293    %1:_(<8 x s8>) = COPY $d1
294    %2:_(<8 x s32>) = G_SEXT %0(<8 x s8>)
295    %3:_(<8 x s32>) = G_SEXT %1(<8 x s8>)
296    %4:_(<8 x s32>) = G_SUB %2, %3
297    %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
298    $q0 = COPY %5(<4 x s32>)
299    $q1 = COPY %6(<4 x s32>)
300    RET_ReallyLR implicit $q0, implicit $q1
301...
302
303---
304name:            usubl_v8i8_v8i32
305tracksRegLiveness: true
306body:             |
307  bb.1:
308    liveins: $d0, $d1
309
310    ; CHECK-LABEL: name: usubl_v8i8_v8i32
311    ; CHECK: liveins: $d0, $d1
312    ; CHECK-NEXT: {{  $}}
313    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
314    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s8>) = COPY $d1
315    ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY]](<8 x s8>)
316    ; CHECK-NEXT: [[ZEXT1:%[0-9]+]]:_(<8 x s16>) = G_ZEXT [[COPY1]](<8 x s8>)
317    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<8 x s16>) = G_SUB [[ZEXT]], [[ZEXT1]]
318    ; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(<8 x s32>) = G_SEXT [[SUB]](<8 x s16>)
319    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[SEXT]](<8 x s32>)
320    ; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
321    ; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
322    ; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
323    %0:_(<8 x s8>) = COPY $d0
324    %1:_(<8 x s8>) = COPY $d1
325    %2:_(<8 x s32>) = G_ZEXT %0(<8 x s8>)
326    %3:_(<8 x s32>) = G_ZEXT %1(<8 x s8>)
327    %4:_(<8 x s32>) = G_SUB %2, %3
328    %5:_(<4 x s32>), %6:_(<4 x s32>) = G_UNMERGE_VALUES %4(<8 x s32>)
329    $q0 = COPY %5(<4 x s32>)
330    $q1 = COPY %6(<4 x s32>)
331    RET_ReallyLR implicit $q0, implicit $q1
332...
333