xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/builtin-return-address-pacret.ll (revision 46584de02c1a38a0ccde85cb5c16331380966c36)
1;; RUN: llc -mtriple aarch64               -global-isel -O0 %s -o - | FileCheck -enable-var-scope %s --check-prefixes=CHECK,CHECK-NOP
2;; RUN: llc -mtriple aarch64 -mattr=+v8.3a -global-isel -O0 %s -o - | FileCheck -enable-var-scope %s --check-prefixes=CHECK,CHECK-V83
3declare void @g0() #1
4declare void @g1(ptr) #1
5declare void @g2(i32, ptr) #1
6
7declare ptr @llvm.returnaddress(i32 immarg) #2
8
9define ptr @f0() #0 {
10entry:
11  %0 = call ptr @llvm.returnaddress(i32 0)
12  call void @g1(ptr %0)
13  %1 = call ptr @llvm.returnaddress(i32 1)
14  call void @g2(i32 1, ptr %1)
15  %2 = call ptr @llvm.returnaddress(i32 2)
16  ret ptr %2
17}
18;; CHECK-LABEL:    f0:
19;; CHECK-NOT:      {{(mov|ldr)}} x30
20;; CHECK-NOP:      hint #7
21;; CHECK-V83:      mov [[COPY_X30:x[0-9]+]], x30
22;; CHECK-V83:      xpaci [[COPY_X30]]
23;; CHECK:          bl g1
24;; CHECK:          ldr x[[T0:[0-9]+]], [x29]
25;; CHECK-NOP-NEXT: ldr x30, [x[[T0]], #8]
26;; CHECK-NOP-NEXT: hint #7
27;; CHECK-V83-NEXT: ldr x[[LD0:[0-9]+]], [x[[T0]], #8]
28;; CHECK-V83-NEXT: xpaci x[[LD0]]
29;; CHECK:          bl g2
30;; CHECK:          ldr x[[T1:[0-9]+]], [x29]
31;; CHECK-NEXT:     ldr x[[T1]], [x[[T1]]]
32;; CHECK-NOP-NEXT: ldr x30, [x[[T1]], #8]
33;; CHECK-NOP-NEXT: hint #7
34;; CHECK-NOP-NEXT: mov x0, x30
35;; CHECK-V83-NEXT: ldr x0, [x[[T1]], #8]
36;; CHECK-V83-NEXT: xpaci x0
37
38define ptr @f1() #0 {
39entry:
40  %0 = call ptr @llvm.returnaddress(i32 1)
41  call void @g1(ptr %0)
42  %1 = call ptr @llvm.returnaddress(i32 2)
43  call void @g2(i32 1, ptr %1)
44  %2 = call ptr @llvm.returnaddress(i32 0)
45  ret ptr %2
46}
47;; CHECK-LABEL:    f1:
48;; CHECK-DAG:      ldr x[[T0:[0-9]+]], [x29]
49;; CHECK-NOP-DAG:  str x30, [sp, #[[OFF:[0-9]+]]
50;; CHECK-NOP:      ldr x30, [x[[T0]], #8]
51;; CHECK-NOP-NEXT: hint #7
52;; CHECK-V83-DAG:  str x30, [sp, #[[OFF:[0-9]+]]
53;; CHECK-V83:      ldr x[[T1:[0-9]+]], [x[[T0]], #8]
54;; CHECK-V83-NEXT: xpaci x[[T1]]
55
56;; CHECK:          bl g1
57;; CHECK:          ldr x[[T2:[0-9]+]], [x29]
58;; CHECK-NEXT:     ldr x[[T2]], [x[[T2]]]
59;; CHECK-NOP-NEXT: ldr x30, [x[[T2]], #8]
60;; CHECK-NOP-NEXT: hint #7
61;; CHECK-V83-NEXT: ldr x[[T3:[0-9]+]], [x[[T2]], #8]
62;; CHECK-V83-NEXT: xpaci x[[T3]]
63;; CHECK:          bl g2
64
65;; CHECK-NOP:      ldr x30, [sp, #[[OFF]]]
66;; CHECK-NOP-NEXT: hint #7
67;; CHECK-NOP-NEXT: mov x0, x30
68
69;; CHECK-V83:      ldr x0, [sp, #[[OFF]]]
70;; CHECK-V83-NEXT: xpaci x0
71;; CHECK-NOT:      x0
72;; CHECK:          ret
73
74define ptr @f2() #0 {
75entry:
76  call void @g0()
77  %0 = call ptr @llvm.returnaddress(i32 0)
78  ret ptr %0
79}
80;; CHECK-LABEL:    f2
81;; CHECK:          bl g0
82;; CHECK-NOP:      ldr x30, [sp,
83;; CHECK-NOP-NEXT: hint #7
84;; CHECK-NOP-NEXT: mov x0, x30
85
86;; CHECK-V83:      ldr x0, [sp,
87;; CHECK-V83-NEXT: xpaci x0
88;; CHECK-NOT:      x0
89;; CHECK:          ret
90
91define ptr @f3() #0 {
92entry:
93  %0 = call ptr @llvm.returnaddress(i32 0)
94  ret ptr %0
95}
96;; CHECK-LABEL:    f3:
97;; CHECK-NOP:      str x30, [sp,
98;; CHECK-NOP-NEXT: hint #7
99;; CHECK-NOP-NEXT: mov x0, x30
100
101;; CHECK-V83:      mov x0, x30
102;; CHECK-V83-NEXT: xpaci x0
103;; CHECK-NOT:      x0
104;; CHECK:          ret
105attributes #0 = { nounwind }
106attributes #1 = { nounwind }
107attributes #2 = { nounwind readnone }
108