xref: /llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/arm64-callingconv.ll (revision 31d6a572579a5d1d9ae14a1a9d4ffbdb1b098e49) 
1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2; RUN: llc -O0 -stop-after=irtranslator -global-isel -global-isel-abort=1 -verify-machineinstrs %s -o - | FileCheck %s
3
4target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
5target triple = "aarch64-linux-gnu"
6
7define i32 @args_i32(i32 %w0, i32 %w1, i32 %w2, i32 %w3,
8  ; CHECK-LABEL: name: args_i32
9  ; CHECK: bb.1 (%ir-block.0):
10  ; CHECK-NEXT:   liveins: $w0, $w1, $w2, $w3, $w4, $w5, $w6, $w7
11  ; CHECK-NEXT: {{  $}}
12  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s32) = COPY $w0
13  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
14  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
15  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s32) = COPY $w3
16  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s32) = COPY $w4
17  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(s32) = COPY $w5
18  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(s32) = COPY $w6
19  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:_(s32) = COPY $w7
20  ; CHECK-NEXT:   $w0 = COPY [[COPY]](s32)
21  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
22                     i32 %w4, i32 %w5, i32 %w6, i32 %w7) {
23  ret i32 %w0
24}
25
26define i64 @args_i64(i64 %x0, i64 %x1, i64 %x2, i64 %x3,
27  ; CHECK-LABEL: name: args_i64
28  ; CHECK: bb.1 (%ir-block.0):
29  ; CHECK-NEXT:   liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
30  ; CHECK-NEXT: {{  $}}
31  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x0
32  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
33  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
34  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
35  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(s64) = COPY $x4
36  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(s64) = COPY $x5
37  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(s64) = COPY $x6
38  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:_(s64) = COPY $x7
39  ; CHECK-NEXT:   $x0 = COPY [[COPY]](s64)
40  ; CHECK-NEXT:   RET_ReallyLR implicit $x0
41                     i64 %x4, i64 %x5, i64 %x6, i64 %x7) {
42  ret i64 %x0
43}
44
45
46define ptr @args_ptrs(ptr %x0, ptr %x1, ptr %x2, ptr %x3,
47  ; CHECK-LABEL: name: args_ptrs
48  ; CHECK: bb.1 (%ir-block.0):
49  ; CHECK-NEXT:   liveins: $x0, $x1, $x2, $x3, $x4, $x5, $x6, $x7
50  ; CHECK-NEXT: {{  $}}
51  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
52  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
53  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(p0) = COPY $x2
54  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(p0) = COPY $x3
55  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(p0) = COPY $x4
56  ; CHECK-NEXT:   [[COPY5:%[0-9]+]]:_(p0) = COPY $x5
57  ; CHECK-NEXT:   [[COPY6:%[0-9]+]]:_(p0) = COPY $x6
58  ; CHECK-NEXT:   [[COPY7:%[0-9]+]]:_(p0) = COPY $x7
59  ; CHECK-NEXT:   $x0 = COPY [[COPY]](p0)
60  ; CHECK-NEXT:   RET_ReallyLR implicit $x0
61                      ptr %x4, ptr %x5, ptr %x6, ptr %x7) {
62  ret ptr %x0
63}
64
65define [1 x double] @args_arr([1 x double] %d0) {
66  ; CHECK-LABEL: name: args_arr
67  ; CHECK: bb.1 (%ir-block.0):
68  ; CHECK-NEXT:   liveins: $d0
69  ; CHECK-NEXT: {{  $}}
70  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $d0
71  ; CHECK-NEXT:   $d0 = COPY [[COPY]](s64)
72  ; CHECK-NEXT:   RET_ReallyLR implicit $d0
73  ret [1 x double] %d0
74}
75
76declare void @varargs(i32, double, i64, ...)
77define void @test_varargs() {
78  ; CHECK-LABEL: name: test_varargs
79  ; CHECK: bb.1 (%ir-block.0):
80  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
81  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00
82  ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
83  ; CHECK-NEXT:   [[C3:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
84  ; CHECK-NEXT:   [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
85  ; CHECK-NEXT:   [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 4
86  ; CHECK-NEXT:   [[C6:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00
87  ; CHECK-NEXT:   [[C7:%[0-9]+]]:_(s64) = G_FCONSTANT double 2.000000e+00
88  ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
89  ; CHECK-NEXT:   [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[C3]](s8)
90  ; CHECK-NEXT:   [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[C4]](s16)
91  ; CHECK-NEXT:   $w0 = COPY [[C]](s32)
92  ; CHECK-NEXT:   $d0 = COPY [[C1]](s64)
93  ; CHECK-NEXT:   $x1 = COPY [[C2]](s64)
94  ; CHECK-NEXT:   $w2 = COPY [[ANYEXT]](s32)
95  ; CHECK-NEXT:   $w3 = COPY [[ANYEXT1]](s32)
96  ; CHECK-NEXT:   $w4 = COPY [[C5]](s32)
97  ; CHECK-NEXT:   $s1 = COPY [[C6]](s32)
98  ; CHECK-NEXT:   $d2 = COPY [[C7]](s64)
99  ; CHECK-NEXT:   BL @varargs, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $w0, implicit $d0, implicit $x1, implicit $w2, implicit $w3, implicit $w4, implicit $s1, implicit $d2
100  ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
101  ; CHECK-NEXT:   RET_ReallyLR
102  call void(i32, double, i64, ...) @varargs(i32 42, double 1.0, i64 12, i8 3, i16 1, i32 4, float 1.0, double 2.0)
103  ret void
104}
105
106; signext/zeroext parameters on the stack: not part of any real ABI as far as I
107; know, but ELF currently allocates 8 bytes for a signext parameter on the
108; stack. The ADJCALLSTACK ops should reflect this, even if the difference is
109; theoretical.
110declare void @stack_ext_needed([8 x i64], i8 signext %in)
111define void @test_stack_ext_needed() {
112  ; CHECK-LABEL: name: test_stack_ext_needed
113  ; CHECK: bb.1 (%ir-block.0):
114  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
115  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 42
116  ; CHECK-NEXT:   ADJCALLSTACKDOWN 8, 0, implicit-def $sp, implicit $sp
117  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $sp
118  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
119  ; CHECK-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C1]](s64)
120  ; CHECK-NEXT:   G_STORE [[C]](s8), [[PTR_ADD]](p0) :: (store (s8) into stack)
121  ; CHECK-NEXT:   $x0 = COPY [[DEF]](s64)
122  ; CHECK-NEXT:   $x1 = COPY [[DEF]](s64)
123  ; CHECK-NEXT:   $x2 = COPY [[DEF]](s64)
124  ; CHECK-NEXT:   $x3 = COPY [[DEF]](s64)
125  ; CHECK-NEXT:   $x4 = COPY [[DEF]](s64)
126  ; CHECK-NEXT:   $x5 = COPY [[DEF]](s64)
127  ; CHECK-NEXT:   $x6 = COPY [[DEF]](s64)
128  ; CHECK-NEXT:   $x7 = COPY [[DEF]](s64)
129  ; CHECK-NEXT:   BL @stack_ext_needed, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4, implicit $x5, implicit $x6, implicit $x7
130  ; CHECK-NEXT:   ADJCALLSTACKUP 8, 0, implicit-def $sp, implicit $sp
131  ; CHECK-NEXT:   RET_ReallyLR
132  call void @stack_ext_needed([8 x i64] undef, i8 signext 42)
133  ret void
134}
135
136; Check that we can lower incoming i128 types into constituent s64 gprs.
137define void @callee_s128(i128 %a, i128 %b, ptr %ptr) {
138  ; CHECK-LABEL: name: callee_s128
139  ; CHECK: bb.1 (%ir-block.0):
140  ; CHECK-NEXT:   liveins: $x0, $x1, $x2, $x3, $x4
141  ; CHECK-NEXT: {{  $}}
142  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(s64) = COPY $x0
143  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
144  ; CHECK-NEXT:   [[MV:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY]](s64), [[COPY1]](s64)
145  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(s64) = COPY $x2
146  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(s64) = COPY $x3
147  ; CHECK-NEXT:   [[MV1:%[0-9]+]]:_(s128) = G_MERGE_VALUES [[COPY2]](s64), [[COPY3]](s64)
148  ; CHECK-NEXT:   [[COPY4:%[0-9]+]]:_(p0) = COPY $x4
149  ; CHECK-NEXT:   G_STORE [[MV1]](s128), [[COPY4]](p0) :: (store (s128) into %ir.ptr)
150  ; CHECK-NEXT:   RET_ReallyLR
151  store i128 %b, ptr %ptr
152  ret void
153}
154
155; Check we can lower outgoing s128 arguments into s64 gprs.
156define void @caller_s128(ptr %ptr) {
157  ; CHECK-LABEL: name: caller_s128
158  ; CHECK: bb.1 (%ir-block.0):
159  ; CHECK-NEXT:   liveins: $x0
160  ; CHECK-NEXT: {{  $}}
161  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $x0
162  ; CHECK-NEXT:   [[LOAD:%[0-9]+]]:_(s128) = G_LOAD [[COPY]](p0) :: (load (s128) from %ir.ptr)
163  ; CHECK-NEXT:   ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
164  ; CHECK-NEXT:   [[UV:%[0-9]+]]:_(s64), [[UV1:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
165  ; CHECK-NEXT:   [[UV2:%[0-9]+]]:_(s64), [[UV3:%[0-9]+]]:_(s64) = G_UNMERGE_VALUES [[LOAD]](s128)
166  ; CHECK-NEXT:   $x0 = COPY [[UV]](s64)
167  ; CHECK-NEXT:   $x1 = COPY [[UV1]](s64)
168  ; CHECK-NEXT:   $x2 = COPY [[UV2]](s64)
169  ; CHECK-NEXT:   $x3 = COPY [[UV3]](s64)
170  ; CHECK-NEXT:   $x4 = COPY [[COPY]](p0)
171  ; CHECK-NEXT:   BL @callee_s128, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $x3, implicit $x4
172  ; CHECK-NEXT:   ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
173  ; CHECK-NEXT:   RET_ReallyLR
174  %v = load i128, ptr %ptr
175  call void @callee_s128(i128 %v, i128 %v, ptr %ptr)
176  ret void
177}
178
179
180declare i64 @i8i16callee(i64 %a1, i64 %a2, i64 %a3, i8 signext %a4, i16 signext %a5, i64 %a6, i64 %a7, i64 %a8, i8 signext %b1, i16 signext %b2, i8 signext %b3, i8 signext %b4) nounwind readnone noinline
181
182define i32 @i8i16caller() nounwind readnone {
183  ; CHECK-LABEL: name: i8i16caller
184  ; CHECK: bb.1.entry:
185  ; CHECK-NEXT:   [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
186  ; CHECK-NEXT:   [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 1
187  ; CHECK-NEXT:   [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
188  ; CHECK-NEXT:   [[C3:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
189  ; CHECK-NEXT:   [[C4:%[0-9]+]]:_(s16) = G_CONSTANT i16 4
190  ; CHECK-NEXT:   [[C5:%[0-9]+]]:_(s64) = G_CONSTANT i64 5
191  ; CHECK-NEXT:   [[C6:%[0-9]+]]:_(s64) = G_CONSTANT i64 6
192  ; CHECK-NEXT:   [[C7:%[0-9]+]]:_(s64) = G_CONSTANT i64 7
193  ; CHECK-NEXT:   [[C8:%[0-9]+]]:_(s8) = G_CONSTANT i8 97
194  ; CHECK-NEXT:   [[C9:%[0-9]+]]:_(s16) = G_CONSTANT i16 98
195  ; CHECK-NEXT:   [[C10:%[0-9]+]]:_(s8) = G_CONSTANT i8 99
196  ; CHECK-NEXT:   [[C11:%[0-9]+]]:_(s8) = G_CONSTANT i8 100
197  ; CHECK-NEXT:   ADJCALLSTACKDOWN 32, 0, implicit-def $sp, implicit $sp
198  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(p0) = COPY $sp
199  ; CHECK-NEXT:   [[C12:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
200  ; CHECK-NEXT:   [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C12]](s64)
201  ; CHECK-NEXT:   G_STORE [[C8]](s8), [[PTR_ADD]](p0) :: (store (s8) into stack)
202  ; CHECK-NEXT:   [[C13:%[0-9]+]]:_(s64) = G_CONSTANT i64 8
203  ; CHECK-NEXT:   [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C13]](s64)
204  ; CHECK-NEXT:   G_STORE [[C9]](s16), [[PTR_ADD1]](p0) :: (store (s16) into stack + 8, align 1)
205  ; CHECK-NEXT:   [[C14:%[0-9]+]]:_(s64) = G_CONSTANT i64 16
206  ; CHECK-NEXT:   [[PTR_ADD2:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C14]](s64)
207  ; CHECK-NEXT:   G_STORE [[C10]](s8), [[PTR_ADD2]](p0) :: (store (s8) into stack + 16)
208  ; CHECK-NEXT:   [[C15:%[0-9]+]]:_(s64) = G_CONSTANT i64 24
209  ; CHECK-NEXT:   [[PTR_ADD3:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C15]](s64)
210  ; CHECK-NEXT:   G_STORE [[C11]](s8), [[PTR_ADD3]](p0) :: (store (s8) into stack + 24)
211  ; CHECK-NEXT:   $x0 = COPY [[C]](s64)
212  ; CHECK-NEXT:   $x1 = COPY [[C1]](s64)
213  ; CHECK-NEXT:   $x2 = COPY [[C2]](s64)
214  ; CHECK-NEXT:   [[SEXT:%[0-9]+]]:_(s32) = G_SEXT [[C3]](s8)
215  ; CHECK-NEXT:   $w3 = COPY [[SEXT]](s32)
216  ; CHECK-NEXT:   [[SEXT1:%[0-9]+]]:_(s32) = G_SEXT [[C4]](s16)
217  ; CHECK-NEXT:   $w4 = COPY [[SEXT1]](s32)
218  ; CHECK-NEXT:   $x5 = COPY [[C5]](s64)
219  ; CHECK-NEXT:   $x6 = COPY [[C6]](s64)
220  ; CHECK-NEXT:   $x7 = COPY [[C7]](s64)
221  ; CHECK-NEXT:   BL @i8i16callee, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $x1, implicit $x2, implicit $w3, implicit $w4, implicit $x5, implicit $x6, implicit $x7, implicit-def $x0
222  ; CHECK-NEXT:   ADJCALLSTACKUP 32, 0, implicit-def $sp, implicit $sp
223  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(s64) = COPY $x0
224  ; CHECK-NEXT:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s64)
225  ; CHECK-NEXT:   $w0 = COPY [[TRUNC]](s32)
226  ; CHECK-NEXT:   RET_ReallyLR implicit $w0
227entry:
228  %call = tail call i64 @i8i16callee(i64 0, i64 1, i64 2, i8 signext 3, i16 signext 4, i64 5, i64 6, i64 7, i8 97, i16  98, i8  99, i8  100)
229  %conv = trunc i64 %call to i32
230  ret i32 %conv
231}
232
233define void @arg_v2i64(<2 x i64> %arg) {
234  ; CHECK-LABEL: name: arg_v2i64
235  ; CHECK: bb.1 (%ir-block.0):
236  ; CHECK-NEXT:   liveins: $q0
237  ; CHECK-NEXT: {{  $}}
238  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
239  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
240  ; CHECK-NEXT:   G_STORE [[COPY]](<2 x s64>), [[DEF]](p0) :: (store (<2 x s64>) into `ptr undef`)
241  ; CHECK-NEXT:   RET_ReallyLR
242  store <2 x i64> %arg, ptr undef
243  ret void
244}
245
246define void @arg_v8i64(<8 x i64> %arg) {
247  ; CHECK-LABEL: name: arg_v8i64
248  ; CHECK: bb.1 (%ir-block.0):
249  ; CHECK-NEXT:   liveins: $q0, $q1, $q2, $q3
250  ; CHECK-NEXT: {{  $}}
251  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
252  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
253  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
254  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
255  ; CHECK-NEXT:   [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[COPY]](<2 x s64>), [[COPY1]](<2 x s64>), [[COPY2]](<2 x s64>), [[COPY3]](<2 x s64>)
256  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
257  ; CHECK-NEXT:   G_STORE [[CONCAT_VECTORS]](<8 x s64>), [[DEF]](p0) :: (store (<8 x s64>) into `ptr undef`)
258  ; CHECK-NEXT:   RET_ReallyLR
259  store <8 x i64> %arg, ptr undef
260  ret void
261}
262
263define void @arg_v4f32(<4 x float> %arg) {
264  ; CHECK-LABEL: name: arg_v4f32
265  ; CHECK: bb.1 (%ir-block.0):
266  ; CHECK-NEXT:   liveins: $q0
267  ; CHECK-NEXT: {{  $}}
268  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
269  ; CHECK-NEXT:   [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
270  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
271  ; CHECK-NEXT:   G_STORE [[BITCAST]](<4 x s32>), [[DEF]](p0) :: (store (<4 x s32>) into `ptr undef`)
272  ; CHECK-NEXT:   RET_ReallyLR
273  store <4 x float> %arg, ptr undef
274  ret void
275}
276
277define void @ret_arg_v16f32(<16 x float> %arg) {
278  ; CHECK-LABEL: name: ret_arg_v16f32
279  ; CHECK: bb.1 (%ir-block.0):
280  ; CHECK-NEXT:   liveins: $q0, $q1, $q2, $q3
281  ; CHECK-NEXT: {{  $}}
282  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
283  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:_(<2 x s64>) = COPY $q1
284  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:_(<2 x s64>) = COPY $q2
285  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:_(<2 x s64>) = COPY $q3
286  ; CHECK-NEXT:   [[BITCAST:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY]](<2 x s64>)
287  ; CHECK-NEXT:   [[BITCAST1:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x s64>)
288  ; CHECK-NEXT:   [[BITCAST2:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY2]](<2 x s64>)
289  ; CHECK-NEXT:   [[BITCAST3:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY3]](<2 x s64>)
290  ; CHECK-NEXT:   [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[BITCAST]](<4 x s32>), [[BITCAST1]](<4 x s32>), [[BITCAST2]](<4 x s32>), [[BITCAST3]](<4 x s32>)
291  ; CHECK-NEXT:   [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
292  ; CHECK-NEXT:   G_STORE [[CONCAT_VECTORS]](<16 x s32>), [[DEF]](p0) :: (store (<16 x s32>) into `ptr undef`)
293  ; CHECK-NEXT:   RET_ReallyLR
294  store <16 x float> %arg, ptr undef
295  ret void
296}
297