xref: /llvm-project/llvm/test/Bitcode/arm-bf16-upgrade.ll (revision ae1396c7d4d83366695137f69f046719fd199408) 
1; RUN: llvm-dis < %s.bc | FileCheck %s
2
3; Bitcode was generated from file below
4
5define arm_aapcs_vfpcc <2 x float> @test_vbfdot_f32(<2 x float> %r, <4 x bfloat> %a, <4 x bfloat> %b) {
6; CHECK-LABEL: @test_vbfdot_f32
7entry:
8  %0 = bitcast <4 x bfloat> %a to <8 x i8>
9  %1 = bitcast <4 x bfloat> %b to <8 x i8>
10  %vbfdot1.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v8i8(<2 x float> %r, <8 x i8> %0, <8 x i8> %1)
11  ; CHECK: %2 = bitcast <8 x i8> %0 to <4 x bfloat>
12  ; CHECK-NEXT: %3 = bitcast <8 x i8> %1 to <4 x bfloat>
13  ; CHECK-NEXT: %vbfdot1.i = call <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float> %r, <4 x bfloat> %2, <4 x bfloat> %3)
14  ret <2 x float> %vbfdot1.i
15}
16
17define <4 x float> @test_vbfdotq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
18; CHECK-LABEL: @test_vbfdotq_f32
19entry:
20  %0 = bitcast <8 x bfloat> %a to <16 x i8>
21  %1 = bitcast <8 x bfloat> %b to <16 x i8>
22  %vbfdot1.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
23  ; CHECK: %2 = bitcast <16 x i8> %0 to <8 x bfloat>
24  ; CHECK-NEXT: %3 = bitcast <16 x i8> %1 to <8 x bfloat>
25  ; CHECK-NEXT: %vbfdot1.i = call <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float> %r, <8 x bfloat> %2, <8 x bfloat> %3)
26  ret <4 x float> %vbfdot1.i
27}
28
29define <4 x float> @test_vbfmmlaq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
30; CHECK-LABEL: @test_vbfmmlaq_f32
31entry:
32  %0 = bitcast <8 x bfloat> %a to <16 x i8>
33  %1 = bitcast <8 x bfloat> %b to <16 x i8>
34  %vbfmmla1.i = call <4 x float> @llvm.arm.neon.bfmmla.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
35  ; CHECK: %2 = bitcast <16 x i8> %0 to <8 x bfloat>
36  ; CHECK-NEXT: %3 = bitcast <16 x i8> %1 to <8 x bfloat>
37  ; CHECK-NEXT: %vbfmmla1.i = call <4 x float> @llvm.arm.neon.bfmmla(<4 x float> %r, <8 x bfloat> %2, <8 x bfloat> %3)
38  ret <4 x float> %vbfmmla1.i
39}
40
41define <4 x float> @test_vbfmlalbq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
42; CHECK-LABEL: @test_vbfmlalbq_laneq_f32
43entry:
44  %vecinit35 = shufflevector <8 x bfloat> %b, <8 x bfloat> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
45  %0 = bitcast <8 x bfloat> %a to <16 x i8>
46  %1 = bitcast <8 x bfloat> %vecinit35 to <16 x i8>
47  %vbfmlalb1.i = call <4 x float> @llvm.arm.neon.bfmlalb.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
48  ; CHECK: %2 = bitcast <16 x i8> %0 to <8 x bfloat>
49  ; CHECK-NEXT: %3 = bitcast <16 x i8> %1 to <8 x bfloat>
50  ; CHECK-NEXT: %vbfmlalb1.i = call <4 x float> @llvm.arm.neon.bfmlalb(<4 x float> %r, <8 x bfloat> %2, <8 x bfloat> %3)
51  ret <4 x float> %vbfmlalb1.i
52}
53
54define <4 x float> @test_vbfmlaltq_laneq_f32(<4 x float> %r, <8 x bfloat> %a, <8 x bfloat> %b) {
55; CHECK-LABEL: @test_vbfmlaltq_laneq_f32
56entry:
57  %vecinit35 = shufflevector <8 x bfloat> %b, <8 x bfloat> undef, <8 x i32> <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
58  %0 = bitcast <8 x bfloat> %a to <16 x i8>
59  %1 = bitcast <8 x bfloat> %vecinit35 to <16 x i8>
60  %vbfmlalt1.i = call <4 x float> @llvm.arm.neon.bfmlalt.v4f32.v16i8(<4 x float> %r, <16 x i8> %0, <16 x i8> %1)
61  ; CHECK: %2 = bitcast <16 x i8> %0 to <8 x bfloat>
62  ; CHECK-NEXT: %3 = bitcast <16 x i8> %1 to <8 x bfloat>
63  ; CHECK-NEXT: %vbfmlalt1.i = call <4 x float> @llvm.arm.neon.bfmlalt(<4 x float> %r, <8 x bfloat> %2, <8 x bfloat> %3)
64  ret <4 x float> %vbfmlalt1.i
65}
66
67declare <2 x float> @llvm.arm.neon.bfdot.v2f32.v8i8(<2 x float>, <8 x i8>, <8 x i8>)
68; CHECK: declare <2 x float> @llvm.arm.neon.bfdot.v2f32.v4bf16(<2 x float>, <4 x bfloat>, <4 x bfloat>)
69declare <4 x float> @llvm.arm.neon.bfdot.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>)
70; CHECK: declare <4 x float> @llvm.arm.neon.bfdot.v4f32.v8bf16(<4 x float>, <8 x bfloat>, <8 x bfloat>)
71declare <4 x float> @llvm.arm.neon.bfmmla.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>)
72; CHECK: declare <4 x float> @llvm.arm.neon.bfmmla(<4 x float>, <8 x bfloat>, <8 x bfloat>)
73declare <4 x float> @llvm.arm.neon.bfmlalb.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>)
74; CHECK: declare <4 x float> @llvm.arm.neon.bfmlalb(<4 x float>, <8 x bfloat>, <8 x bfloat>)
75declare <4 x float> @llvm.arm.neon.bfmlalt.v4f32.v16i8(<4 x float>, <16 x i8>, <16 x i8>)
76; CHECK: declare <4 x float> @llvm.arm.neon.bfmlalt(<4 x float>, <8 x bfloat>, <8 x bfloat>)