1; RUN: opt -mtriple amdgcn-- -passes='print<uniformity>' -disable-output %s 2>&1 | FileCheck %s 2 3; CHECK: DIVERGENT: %tmp5 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %tmp2 4; CHECK: DIVERGENT: %tmp10 = load volatile float, ptr addrspace(1) %tmp5, align 4 5; CHECK: DIVERGENT: %tmp11 = load volatile float, ptr addrspace(1) %tmp5, align 4 6 7; The post dominator tree does not have a root node in this case 8define amdgpu_kernel void @no_return_blocks(ptr addrspace(1) noalias nocapture readonly %arg, ptr addrspace(1) noalias nocapture readonly %arg1) #0 { 9bb0: 10 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0 11 %tmp2 = sext i32 %tmp to i64 12 %tmp5 = getelementptr inbounds float, ptr addrspace(1) %arg, i64 %tmp2 13 %tmp6 = load volatile float, ptr addrspace(1) %tmp5, align 4 14 %tmp8 = fcmp olt float %tmp6, 0.000000e+00 15 br i1 %tmp8, label %bb1, label %bb2 16 17bb1: 18 %tmp10 = load volatile float, ptr addrspace(1) %tmp5, align 4 19 br label %bb2 20 21bb2: 22 %tmp11 = load volatile float, ptr addrspace(1) %tmp5, align 4 23 br label %bb1 24} 25 26; Function Attrs: nounwind readnone 27declare i32 @llvm.amdgcn.workitem.id.x() #1 28 29attributes #0 = { nounwind } 30attributes #1 = { nounwind readnone } 31