1; RUN: opt %s -mtriple amdgcn-- -passes='print<uniformity>' -disable-output 2>&1 | FileCheck %s 2 3; This test contains an unstructured loop. 4; +-------------- entry ----------------+ 5; | | 6; V V 7; i1 = phi(0, i3) i2 = phi(0, i3) 8; j1 = i1 + 1 ---> i3 = phi(j1, j2) <--- j2 = i2 + 2 9; ^ | ^ 10; | V | 11; +-------- switch (tid / i3) ----------+ 12; | 13; V 14; if (i3 == 5) // divergent 15; because sync dependent on (tid / i3). 16 17define i32 @unstructured_loop(i1 %entry_cond) { 18; CHECK-LABEL: for function 'unstructured_loop' 19; CHECK: DIVERGENT: i1 %entry_cond 20 21entry: 22 %tid = call i32 @llvm.amdgcn.workitem.id.x() 23 br i1 %entry_cond, label %loop_entry_1, label %loop_entry_2 24loop_entry_1: 25; CHECK: DIVERGENT: %i1 = 26 %i1 = phi i32 [ 0, %entry ], [ %i3, %loop_latch ] 27 %j1 = add i32 %i1, 1 28 br label %loop_body 29loop_entry_2: 30; CHECK: DIVERGENT: %i2 = 31 %i2 = phi i32 [ 0, %entry ], [ %i3, %loop_latch ] 32 %j2 = add i32 %i2, 2 33 br label %loop_body 34loop_body: 35; CHECK: DIVERGENT: %i3 = 36 %i3 = phi i32 [ %j1, %loop_entry_1 ], [ %j2, %loop_entry_2 ] 37 br label %loop_latch 38loop_latch: 39 %div = sdiv i32 %tid, %i3 40 switch i32 %div, label %branch [ i32 1, label %loop_entry_1 41 i32 2, label %loop_entry_2 ] 42branch: 43; CHECK: DIVERGENT: %cmp = 44; CHECK: DIVERGENT: br i1 %cmp, 45 %cmp = icmp eq i32 %i3, 5 46 br i1 %cmp, label %then, label %else 47then: 48 ret i32 0 49else: 50 ret i32 1 51} 52 53declare i32 @llvm.amdgcn.workitem.id.x() #0 54 55attributes #0 = { nounwind readnone } 56