1; RUN: opt %s -mtriple amdgcn-- -passes='print<uniformity>' -disable-output 2>&1 | FileCheck %s 2 3; CHECK=LABEL: UniformityInfo for function 'basic': 4; CHECK: CYCLES ASSSUMED DIVERGENT: 5; CHECK: depth=1: entries(P T) Q 6define amdgpu_kernel void @basic(i32 %a, i32 %b, i32 %c) { 7entry: 8 %cond.uni = icmp slt i32 %a, 0 9 %tid = call i32 @llvm.amdgcn.workitem.id.x() 10 %cond.div = icmp slt i32 %tid, 0 11 br i1 %cond.div, label %T, label %P 12 13P: 14; CHECK: DIVERGENT: %pp.phi = 15; CHECK: DIVERGENT: %pp = 16 %pp.phi = phi i32 [ %a, %entry], [ %b, %T ] 17 %pp = add i32 %b, 1 18 br label %Q 19 20Q: 21; CHECK: DIVERGENT: %qq = 22; CHECK: DIVERGENT: %qq.div = 23 %qq = add i32 %b, 1 24 %qq.div = add i32 %pp.phi, 1 25 br i1 %cond.uni, label %T, label %exit 26 27T: 28; CHECK: DIVERGENT: %t.phi = 29; CHECK: DIVERGENT: %tt = 30 %t.phi = phi i32 [ %qq, %Q ], [ %a, %entry ] 31 %tt = add i32 %b, 1 32 br label %P 33 34exit: 35; CHECK-NOT: DIVERGENT: %ee = 36 %ee = add i32 %b, 1 37 ret void 38} 39 40; CHECK=LABEL: UniformityInfo for function 'nested': 41; CHECK: CYCLES ASSSUMED DIVERGENT: 42; CHECK: depth=1: entries(P T) Q A C B 43define amdgpu_kernel void @nested(i32 %a, i32 %b, i32 %c) { 44entry: 45 %cond.uni = icmp slt i32 %a, 0 46 %tid = call i32 @llvm.amdgcn.workitem.id.x() 47 %cond.div = icmp slt i32 %tid, 0 48 br i1 %cond.div, label %T, label %P 49 50P: 51 %pp.phi = phi i32 [ %a, %entry], [ %b, %T ] 52 %pp = add i32 %b, 1 53 br i1 %cond.uni, label %B, label %Q 54 55Q: 56 %qq = add i32 %b, 1 57 br i1 %cond.uni, label %T, label %exit 58 59A: 60 %aa = add i32 %b, 1 61 br label %B 62 63B: 64 %bb = add i32 %b, 1 65 br label %C 66 67C: 68 %cc = add i32 %b, 1 69 br i1 %cond.uni, label %Q, label %A 70 71T: 72 %t.phi = phi i32 [ %qq, %Q ], [ %a, %entry ] 73 %tt = add i32 %b, 1 74 br i1 %cond.uni, label %A, label %P 75 76exit: 77 %ee = add i32 %b, 1 78 ret void 79} 80 81; Just make sure that this does not asert. It is important that Q is recognized 82; as the header of the outermost cycle. The incorrect assert was exercised by 83; this hierarchy: 84; 85; CycleInfo for function: irreducible_outer_cycle 86; depth=1: entries(Q R) C B D 87; depth=2: entries(R) C B D 88; depth=3: entries(B) D 89; 90; CHECK-LABEL: UniformityInfo for function 'irreducible_outer_cycle': 91; CHECK: CYCLES ASSSUMED DIVERGENT: 92; CHECK: depth=1: entries(Q R) C B D 93define void @irreducible_outer_cycle(i1 %c1, i1 %c2, i1 %c3) { 94entry: 95 br i1 %c1, label %P, label %Q 96 97P: 98 br i1 false, label %Q, label %R 99 100Q: 101 br label %R 102 103R: 104 br i1 false, label %Q, label %B 105 106B: 107 br i1 false, label %C, label %D 108 109D: 110 br label %B 111 112C: 113 br i1 false, label %R, label %exit 114 115exit: 116 ret void 117} 118 119declare i32 @llvm.amdgcn.workitem.id.x() #0 120