1# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s 2 3--- 4# CHECK-LABEL: MachineUniformityInfo for function: temporal_diverge 5name: temporal_diverge 6alignment: 1 7legalized: true 8tracksRegLiveness: true 9registers: 10 - { id: 3, class: _ } 11 - { id: 4, class: vgpr_32 } 12 - { id: 5, class: sgpr_32 } 13 - { id: 6, class: sgpr_32 } 14liveins: 15 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' } 16 - { reg: '$vgpr0', virtual-reg: '%4' } 17 - { reg: '$sgpr2', virtual-reg: '%5' } 18 - { reg: '$sgpr3', virtual-reg: '%6' } 19body: | 20 bb.1: 21 liveins: $sgpr0_sgpr1 22 23 %15:_(s64) = G_CONSTANT i64 0 24 25 bb.2: 26 successors: %bb.3, %bb.2 27 28 %11:_(s64) = G_PHI %12(s64), %bb.2, %15(s64), %bb.1 29 %18:_(s1) = G_CONSTANT i1 false 30 %12:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %18(s1), %11(s64) 31 ; CHECK: DIVERGENT: SI_LOOP 32 SI_LOOP %12(s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec 33 G_BR %bb.3 34 35 bb.3: 36 ; CHECK: DIVERGENT: %{{[0-9]+}}: %{{[0-9]+}}:_(s64) = G_PHI 37 %14:_(s64) = G_PHI %12(s64), %bb.2 38 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %14(s64) 39 S_ENDPGM 0 40 41... 42--- 43# CHECK-LABEL: MachineUniformityInfo for function: phi_at_exit 44name: phi_at_exit 45alignment: 1 46legalized: true 47tracksRegLiveness: true 48registers: 49 - { id: 3, class: _ } 50 - { id: 4, class: vgpr_32 } 51 - { id: 5, class: sgpr_32 } 52 - { id: 6, class: sgpr_32 } 53liveins: 54 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' } 55 - { reg: '$vgpr0', virtual-reg: '%4' } 56 - { reg: '$sgpr2', virtual-reg: '%5' } 57 - { reg: '$sgpr3', virtual-reg: '%6' } 58body: | 59 bb.1: 60 successors: %bb.2, %bb.3 61 liveins: $sgpr0_sgpr1 62 63 %3:_(p4) = COPY $sgpr0_sgpr1 64 %7:_(p4) = COPY %3(p4) 65 %8:_(s64) = G_CONSTANT i64 40 66 %9:_(p4) = G_PTR_ADD %7, %8(s64) 67 %10:_(s32) = G_LOAD %9(p4) :: (load (s32), addrspace 4) 68 %11:_(s32) = G_CONSTANT i32 0 69 %12:_(s1) = G_ICMP intpred(sge), %10(s32), %11 70 G_BRCOND %12(s1), %bb.3 71 G_BR %bb.2 72 73 bb.2: 74 %24:_(s64) = G_CONSTANT i64 0 75 %14:_(s1) = G_CONSTANT i1 false 76 G_BR %bb.4 77 78 bb.3: 79 G_BR %bb.6 80 81 bb.4: 82 successors: %bb.5, %bb.4 83 84 %15:_(s64) = G_PHI %24(s64), %bb.2, %16(s64), %bb.4 85 %16:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %14(s1), %15(s64) 86 ; CHECK: DIVERGENT: SI_LOOP 87 SI_LOOP %16(s64), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec 88 G_BR %bb.5 89 90 bb.5: 91 ; CHECK: DIVERGENT: %{{[0-9]+}}: %{{[0-9]+}}:_(s64) = G_PHI 92 %18:_(s64) = G_PHI %16(s64), %bb.4 93 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %18(s64) 94 G_BR %bb.3 95 96 bb.6: 97 S_ENDPGM 0 98 99... 100--- 101# CHECK-LABEL: MachineUniformityInfo for function: phi_after_exit 102name: phi_after_exit 103alignment: 1 104legalized: true 105tracksRegLiveness: true 106registers: 107 - { id: 3, class: _ } 108 - { id: 4, class: vgpr_32 } 109 - { id: 5, class: sgpr_32 } 110 - { id: 6, class: sgpr_32 } 111liveins: 112 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' } 113 - { reg: '$vgpr0', virtual-reg: '%4' } 114 - { reg: '$sgpr2', virtual-reg: '%5' } 115 - { reg: '$sgpr3', virtual-reg: '%6' } 116body: | 117 bb.1: 118 successors: %bb.2, %bb.3 119 liveins: $sgpr0_sgpr1 120 121 %3:_(p4) = COPY $sgpr0_sgpr1 122 %7:_(p4) = COPY %3(p4) 123 %8:_(s64) = G_CONSTANT i64 40 124 %9:_(p4) = G_PTR_ADD %7, %8(s64) 125 %10:_(s32) = G_LOAD %9(p4) :: (dereferenceable invariant load (s32), addrspace 4) 126 %11:_(s32) = G_CONSTANT i32 0 127 %12:_(s1) = G_ICMP intpred(sge), %10(s32), %11 128 G_BRCOND %12(s1), %bb.3 129 G_BR %bb.2 130 131 bb.2: 132 %24:_(s64) = G_CONSTANT i64 0 133 %14:_(s1) = G_CONSTANT i1 false 134 G_BR %bb.4 135 136 bb.3: 137 G_BR %bb.6 138 139 bb.4: 140 successors: %bb.5, %bb.4 141 142 %15:_(s64) = G_PHI %24(s64), %bb.2, %16(s64), %bb.4 143 %16:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %14(s1), %15(s64) 144 ; CHECK: DIVERGENT: SI_LOOP 145 SI_LOOP %16(s64), %bb.4, implicit-def $exec, implicit-def $scc, implicit $exec 146 G_BR %bb.5 147 148 bb.5: 149 ; CHECK: DIVERGENT: %{{[0-9]+}}: %{{[0-9]+}}:_(s64) = G_PHI 150 %18:_(s64) = G_PHI %16(s64), %bb.4 151 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %18(s64) 152 G_BR %bb.3 153 154 bb.6: 155 S_ENDPGM 0 156 157... 158--- 159# CHECK-LABEL: MachineUniformityInfo for function: temporal_diverge_inloop 160name: temporal_diverge_inloop 161alignment: 1 162legalized: true 163tracksRegLiveness: true 164registers: 165 - { id: 3, class: _ } 166 - { id: 4, class: vgpr_32 } 167 - { id: 5, class: sgpr_32 } 168 - { id: 6, class: sgpr_32 } 169liveins: 170 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' } 171 - { reg: '$vgpr0', virtual-reg: '%4' } 172 - { reg: '$sgpr2', virtual-reg: '%5' } 173 - { reg: '$sgpr3', virtual-reg: '%6' } 174body: | 175 bb.1: 176 liveins: $sgpr0_sgpr1 177 178 %3:_(p4) = COPY $sgpr0_sgpr1 179 %7:_(p4) = COPY %3(p4) 180 %8:_(s64) = G_CONSTANT i64 40 181 %9:_(p4) = G_PTR_ADD %7, %8(s64) 182 %10:_(s32) = G_LOAD %9(p4) :: (dereferenceable invariant load (s32), addrspace 4) 183 %12:_(s32) = G_CONSTANT i32 0 184 %13:_(s1) = G_ICMP intpred(slt), %10(s32), %12 185 186 bb.2: 187 %25:_(s64) = G_CONSTANT i64 0 188 189 bb.3: 190 successors: %bb.4, %bb.3 191 192 %15:_(s64) = G_PHI %25(s64), %bb.2, %16(s64), %bb.3 193 %24:_(s1) = G_CONSTANT i1 false 194 %16:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %24(s1), %15(s64) 195 ; CHECK: DIVERGENT: SI_LOOP 196 SI_LOOP %16(s64), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec 197 G_BR %bb.4 198 199 bb.4: 200 ; CHECK: DIVERGENT: %{{[0-9]+}}: %{{[0-9]+}}:_(s64) = G_PHI 201 successors: %bb.5, %bb.2 202 203 %18:_(s64) = G_PHI %16(s64), %bb.3 204 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %18(s64) 205 G_BRCOND %13(s1), %bb.2 206 G_BR %bb.5 207 208 bb.5: 209 S_ENDPGM 0 210 211... 212--- 213# CHECK-LABEL: MachineUniformityInfo for function: temporal_uniform_indivloop 214name: temporal_uniform_indivloop 215alignment: 1 216legalized: true 217tracksRegLiveness: true 218registers: 219 - { id: 3, class: _ } 220 - { id: 4, class: vgpr_32 } 221 - { id: 5, class: sgpr_32 } 222 - { id: 6, class: sgpr_32 } 223liveins: 224 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' } 225 - { reg: '$vgpr0', virtual-reg: '%4' } 226 - { reg: '$sgpr2', virtual-reg: '%5' } 227 - { reg: '$sgpr3', virtual-reg: '%6' } 228body: | 229 bb.1: 230 liveins: $sgpr0_sgpr1 231 232 %3:_(p4) = COPY $sgpr0_sgpr1 233 %19:_(s64) = G_CONSTANT i64 0 234 %7:_(p4) = COPY %3(p4) 235 %8:_(s64) = G_CONSTANT i64 40 236 %9:_(p4) = G_PTR_ADD %7, %8(s64) 237 %10:_(s32) = G_LOAD %9(p4) :: (dereferenceable invariant load (s32), addrspace 4) 238 %12:_(s32) = G_CONSTANT i32 0 239 %13:_(s1) = G_ICMP intpred(sge), %10(s32), %12 240 241 bb.2: 242 %15:_(s64) = G_PHI %16(s64), %bb.4, %19(s64), %bb.1 243 %24:_(s1) = G_CONSTANT i1 true 244 %16:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %24(s1), %15(s64) 245 246 bb.3: 247 successors: %bb.4, %bb.3 248 249 G_BRCOND %13(s1), %bb.3 250 G_BR %bb.4 251 252 bb.4: 253 successors: %bb.5, %bb.2 254 255 ; CHECK: DIVERGENT: SI_LOOP 256 SI_LOOP %16(s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec 257 G_BR %bb.5 258 259 bb.5: 260 ; CHECK: DIVERGENT: %{{[0-9]+}}: %{{[0-9]+}}:_(s64) = G_PHI 261 %18:_(s64) = G_PHI %16(s64), %bb.4 262 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %18(s64) 263 S_ENDPGM 0 264 265... 266--- 267# CHECK-LABEL: MachineUniformityInfo for function: temporal_diverge_loopuser 268name: temporal_diverge_loopuser 269alignment: 1 270legalized: true 271tracksRegLiveness: true 272registers: 273 - { id: 3, class: _ } 274 - { id: 4, class: vgpr_32 } 275 - { id: 5, class: sgpr_32 } 276 - { id: 6, class: sgpr_32 } 277liveins: 278 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' } 279 - { reg: '$vgpr0', virtual-reg: '%4' } 280 - { reg: '$sgpr2', virtual-reg: '%5' } 281 - { reg: '$sgpr3', virtual-reg: '%6' } 282body: | 283 bb.1: 284 liveins: $sgpr0_sgpr1 285 286 %3:_(p4) = COPY $sgpr0_sgpr1 287 %19:_(s64) = G_CONSTANT i64 0 288 289 bb.2: 290 successors: %bb.3, %bb.2 291 292 %10:_(s64) = G_PHI %11(s64), %bb.2, %19(s64), %bb.1 293 %24:_(s1) = G_CONSTANT i1 false 294 %11:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %24(s1), %10(s64) 295 ; CHECK: DIVERGENT: SI_LOOP 296 SI_LOOP %11(s64), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec 297 G_BR %bb.3 298 299 bb.3: 300 ; CHECK: DIVERGENT: %{{[0-9]+}}: %{{[0-9]+}}:_(s64) = G_PHI 301 ; CHECK-NOT: DIVERGENT: %{{[0-9]+}}: %{{[0-9]+}}:_(s64) = G_PHI 302 %13:_(s64) = G_PHI %11(s64), %bb.2 303 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %13(s64) 304 %14:_(p4) = COPY %3(p4) 305 %15:_(s64) = G_CONSTANT i64 40 306 %16:_(p4) = G_PTR_ADD %14, %15(s64) 307 %17:_(s32) = G_LOAD %16(p4) :: (dereferenceable invariant load (s32), addrspace 4) 308 %25:_(s32) = G_CONSTANT i32 0 309 %18:_(s1) = G_ICMP intpred(slt), %17(s32), %25 310 311 bb.4: 312 successors: %bb.5, %bb.4 313 314 G_BRCOND %18(s1), %bb.4 315 G_BR %bb.5 316 317 bb.5: 318 S_ENDPGM 0 319 320... 321--- 322# CHECK-LABEL: MachineUniformityInfo for function: temporal_diverge_loopuser_nested 323name: temporal_diverge_loopuser_nested 324alignment: 1 325legalized: true 326tracksRegLiveness: true 327registers: 328 - { id: 3, class: _ } 329 - { id: 4, class: vgpr_32 } 330 - { id: 5, class: sgpr_32 } 331 - { id: 6, class: sgpr_32 } 332liveins: 333 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' } 334 - { reg: '$vgpr0', virtual-reg: '%4' } 335 - { reg: '$sgpr2', virtual-reg: '%5' } 336 - { reg: '$sgpr3', virtual-reg: '%6' } 337body: | 338 bb.1: 339 liveins: $sgpr0_sgpr1 340 341 %3:_(p4) = COPY $sgpr0_sgpr1 342 %7:_(p4) = COPY %3(p4) 343 %8:_(s64) = G_CONSTANT i64 40 344 %9:_(p4) = G_PTR_ADD %7, %8(s64) 345 %10:_(s32) = G_LOAD %9(p4) :: (dereferenceable invariant load (s32), addrspace 4) 346 %12:_(s32) = G_CONSTANT i32 0 347 %13:_(s1) = G_ICMP intpred(sge), %10(s32), %12 348 349 bb.2: 350 %23:_(s64) = G_CONSTANT i64 0 351 352 bb.3: 353 successors: %bb.4, %bb.3 354 355 %15:_(s64) = G_PHI %23(s64), %bb.2, %16(s64), %bb.3 356 %25:_(s1) = G_CONSTANT i1 false 357 %16:sreg_64_xexec(s64) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %25(s1), %15(s64) 358 ; CHECK: DIVERGENT: SI_LOOP 359 SI_LOOP %16(s64), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec 360 G_BR %bb.4 361 362 bb.4: 363 ; CHECK: DIVERGENT: %{{[0-9]+}}: %{{[0-9]+}}:_(s64) = G_PHI 364 %18:_(s64) = G_PHI %16(s64), %bb.3 365 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %18(s64) 366 367 bb.5: 368 369 bb.6: 370 successors: %bb.8, %bb.5 371 372 G_BRCOND %13(s1), %bb.8 373 G_BR %bb.5 374 375 bb.7: 376 S_ENDPGM 0 377 378 bb.8: 379 successors: %bb.7, %bb.2 380 381 %24:_(s1) = G_CONSTANT i1 false 382 G_BRCOND %24(s1), %bb.7 383 G_BR %bb.2 384 385... 386