1# RUN: llc -mtriple=amdgcn-- -run-pass=print-machine-uniformity -o - %s 2>&1 | FileCheck %s 2 3--- 4name: test1 5tracksRegLiveness: true 6body: | 7 bb.0: 8 ; CHECK-LABEL: MachineUniformityInfo for function: test1 9 %2:vgpr_32 = IMPLICIT_DEF 10 %1:vgpr_32 = IMPLICIT_DEF 11 %0:vgpr_32 = IMPLICIT_DEF 12 %3:sreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 13 %5:vreg_64 = COPY %3 14 %6:vreg_64 = COPY %3 15 ; CHECK: DIVERGENT{{.*}}FLAT_ATOMIC_SWAP_RTN 16 %4:vgpr_32 = FLAT_ATOMIC_SWAP_RTN killed %5, %2, 0, 1, implicit $exec, implicit $flat_scr :: (load store seq_cst (s32)) 17 ; CHECK: DIVERGENT{{.*}}FLAT_ATOMIC_SWAP_RTN 18 %7:vgpr_32 = FLAT_ATOMIC_SWAP_RTN killed %6, %2, 0, 1, implicit $exec, implicit $flat_scr ; No memopernads 19 $vgpr0 = COPY %4 20 SI_RETURN implicit $vgpr0 21... 22 23--- 24name: test2 25tracksRegLiveness: true 26body: | 27 bb.0: 28 ; CHECK-LABEL: MachineUniformityInfo for function: test2 29 %3:vgpr_32 = IMPLICIT_DEF 30 %2:vgpr_32 = IMPLICIT_DEF 31 %1:vgpr_32 = IMPLICIT_DEF 32 %0:vgpr_32 = IMPLICIT_DEF 33 %4:sreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 34 %5:sreg_64 = REG_SEQUENCE %3, %subreg.sub0, %2, %subreg.sub1 35 %7:vreg_64 = COPY %4 36 %8:vreg_64 = COPY %5 37 ; CHECK: DIVERGENT{{.*}}FLAT_ATOMIC_CMPSWAP_RTN 38 %6:vgpr_32 = FLAT_ATOMIC_CMPSWAP_RTN killed %7, killed %8, 0, 1, implicit $exec, implicit $flat_scr :: (load store seq_cst seq_cst (s32)) 39 %9:sreg_64_xexec = V_CMP_EQ_U32_e64 %6, %2, implicit $exec 40 %10:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, killed %9, implicit $exec 41 $vgpr0 = COPY %6 42 $vgpr1 = COPY %10 43 SI_RETURN implicit $vgpr0, implicit $vgpr1 44... 45 46--- 47name: atomic_inc 48tracksRegLiveness: true 49body: | 50 bb.0: 51 ; CHECK-LABEL: MachineUniformityInfo for function: atomic_inc 52 %2:vgpr_32 = IMPLICIT_DEF 53 %1:vgpr_32 = IMPLICIT_DEF 54 %0:vgpr_32 = IMPLICIT_DEF 55 %3:sreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 56 %5:vreg_64 = COPY %3 57 ; CHECK: DIVERGENT{{.*}}GLOBAL_ATOMIC_INC_RTN 58 %4:vgpr_32 = GLOBAL_ATOMIC_INC_RTN killed %5, %2, 0, 1, implicit $exec :: (load store (s32), addrspace 1) 59 $vgpr0 = COPY %4 60 SI_RETURN implicit $vgpr0 61... 62 63--- 64name: atomic_inc_64 65tracksRegLiveness: true 66body: | 67 bb.0: 68 ; CHECK-LABEL: MachineUniformityInfo for function: atomic_inc_64 69 %3:vgpr_32 = IMPLICIT_DEF 70 %2:vgpr_32 = IMPLICIT_DEF 71 %1:vgpr_32 = IMPLICIT_DEF 72 %0:vgpr_32 = IMPLICIT_DEF 73 %4:sreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1 74 %5:sreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 75 %7:vreg_64 = COPY %5 76 %8:vreg_64 = COPY %4 77 ; CHECK: DIVERGENT{{.*}}GLOBAL_ATOMIC_INC_X2_RTN 78 %6:vreg_64 = GLOBAL_ATOMIC_INC_X2_RTN killed %7, killed %8, 0, 1, implicit $exec :: (load store (s64), addrspace 1) 79 %9:vgpr_32 = COPY %6.sub1 80 %10:vgpr_32 = COPY %6.sub0 81 $vgpr0 = COPY %10 82 $vgpr1 = COPY %9 83 SI_RETURN implicit $vgpr0, implicit $vgpr1 84... 85 86--- 87name: atomic_dec 88tracksRegLiveness: true 89body: | 90 bb.0: 91 ; CHECK-LABEL: MachineUniformityInfo for function: atomic_dec 92 %2:vgpr_32 = IMPLICIT_DEF 93 %1:vgpr_32 = IMPLICIT_DEF 94 %0:vgpr_32 = IMPLICIT_DEF 95 %3:sreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 96 %5:vreg_64 = COPY %3 97 ; CHECK: DIVERGENT{{.*}}GLOBAL_ATOMIC_DEC_RTN 98 %4:vgpr_32 = GLOBAL_ATOMIC_DEC_RTN killed %5, %2, 0, 1, implicit $exec :: (load store (s32), addrspace 1) 99 $vgpr0 = COPY %4 100 SI_RETURN implicit $vgpr0 101... 102 103 104--- 105name: atomic_dec_64 106tracksRegLiveness: true 107body: | 108 bb.0: 109 ; CHECK-LABEL: MachineUniformityInfo for function: atomic_dec_64 110 %3:vgpr_32 = IMPLICIT_DEF 111 %2:vgpr_32 = IMPLICIT_DEF 112 %1:vgpr_32 = IMPLICIT_DEF 113 %0:vgpr_32 = IMPLICIT_DEF 114 %4:sreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1 115 %5:sreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1 116 %7:vreg_64 = COPY %5 117 %8:vreg_64 = COPY %4 118 ; CHECK: DIVERGENT{{.*}}GLOBAL_ATOMIC_DEC_X2_RTN 119 %6:vreg_64 = GLOBAL_ATOMIC_DEC_X2_RTN killed %7, killed %8, 0, 1, implicit $exec :: (load store (s64), addrspace 1) 120 %9:vgpr_32 = COPY %6.sub1 121 %10:vgpr_32 = COPY %6.sub0 122 $vgpr0 = COPY %10 123 $vgpr1 = COPY %9 124 SI_RETURN implicit $vgpr0, implicit $vgpr1 125... 126