1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 2; RUN: opt -passes='loop(loop-deletion),loop-mssa(loop-predication,licm<allowspeculation>,simple-loop-unswitch<nontrivial>),loop(loop-predication)' -S < %s | FileCheck %s 3 4target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2" 5target triple = "x86_64-unknown-linux-gnu" 6 7define void @test(i32 %arg) { 8; CHECK-LABEL: define void @test 9; CHECK-SAME: (i32 [[ARG:%.*]]) { 10; CHECK-NEXT: bb: 11; CHECK-NEXT: br label [[BB1:%.*]] 12; CHECK: bb1: 13; CHECK-NEXT: br label [[BB2:%.*]] 14; CHECK: bb2: 15; CHECK-NEXT: br i1 false, label [[BB3_PREHEADER:%.*]], label [[BB1]] 16; CHECK: bb3.preheader: 17; CHECK-NEXT: [[LOAD_LE:%.*]] = load i32, ptr null, align 4 18; CHECK-NEXT: br label [[BB3:%.*]] 19; CHECK: bb3.loopexit: 20; CHECK-NEXT: br label [[BB3]] 21; CHECK: bb3: 22; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[ADD:%.*]], [[BB3_LOOPEXIT:%.*]] ], [ 0, [[BB3_PREHEADER]] ] 23; CHECK-NEXT: [[ADD]] = add i32 [[PHI]], 1 24; CHECK-NEXT: [[ICMP:%.*]] = icmp ult i32 [[PHI]], [[LOAD_LE]] 25; CHECK-NEXT: br i1 [[ICMP]], label [[BB5:%.*]], label [[BB4:%.*]] 26; CHECK: bb4: 27; CHECK-NEXT: ret void 28; CHECK: bb5: 29; CHECK-NEXT: [[CALL:%.*]] = call i1 @llvm.experimental.widenable.condition() 30; CHECK-NEXT: br i1 [[CALL]], label [[BB9_PREHEADER:%.*]], label [[BB14:%.*]] 31; CHECK: bb9.preheader: 32; CHECK-NEXT: br label [[BB9:%.*]] 33; CHECK: bb6: 34; CHECK-NEXT: [[ADD7:%.*]] = add i32 [[PHI10:%.*]], 1 35; CHECK-NEXT: [[ICMP8:%.*]] = icmp ugt i32 [[PHI10]], 1 36; CHECK-NEXT: br i1 [[ICMP8]], label [[BB3_LOOPEXIT]], label [[BB9]] 37; CHECK: bb9: 38; CHECK-NEXT: [[PHI10]] = phi i32 [ [[ADD7]], [[BB6:%.*]] ], [ [[PHI]], [[BB9_PREHEADER]] ] 39; CHECK-NEXT: [[ICMP11:%.*]] = icmp ult i32 [[PHI10]], [[ARG]] 40; CHECK-NEXT: [[CALL12:%.*]] = call i1 @llvm.experimental.widenable.condition() 41; CHECK-NEXT: [[AND:%.*]] = and i1 [[ICMP11]], true 42; CHECK-NEXT: br i1 [[AND]], label [[BB6]], label [[BB13:%.*]] 43; CHECK: bb13: 44; CHECK-NEXT: ret void 45; CHECK: bb14: 46; CHECK-NEXT: ret void 47; 48bb: 49 br label %bb1 50 51bb1: ; preds = %bb2, %bb 52 %load = load i32, ptr null, align 4 53 br label %bb2 54 55bb2: ; preds = %bb1 56 br i1 false, label %bb3, label %bb1 57 58bb3: ; preds = %bb6, %bb2 59 %phi = phi i32 [ %add, %bb6 ], [ 0, %bb2 ] 60 %add = add i32 %phi, 1 61 %icmp = icmp ult i32 %phi, %load 62 br i1 %icmp, label %bb5, label %bb4 63 64bb4: ; preds = %bb3 65 ret void 66 67bb5: ; preds = %bb3 68 %call = call i1 @llvm.experimental.widenable.condition() 69 br i1 %call, label %bb9, label %bb14 70 71bb6: ; preds = %bb9 72 %add7 = add i32 %phi10, 1 73 %icmp8 = icmp ugt i32 %phi10, 1 74 br i1 %icmp8, label %bb3, label %bb9 75 76bb9: ; preds = %bb6, %bb5 77 %phi10 = phi i32 [ %add7, %bb6 ], [ %phi, %bb5 ] 78 %icmp11 = icmp ult i32 %phi10, %arg 79 %call12 = call i1 @llvm.experimental.widenable.condition() 80 %and = and i1 %icmp11, %call12 81 br i1 %and, label %bb6, label %bb13 82 83bb13: ; preds = %bb9 84 ret void 85 86bb14: ; preds = %bb5 87 ret void 88} 89 90; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(inaccessiblemem: readwrite) 91declare noundef i1 @llvm.experimental.widenable.condition() #0 92 93attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(inaccessiblemem: readwrite) } 94