xref: /llvm-project/llvm/test/Analysis/MemorySSA/multi-edges.ll (revision 8e44f13c6d294e6b4864441b22045b507782540c)
1; RUN: opt -aa-pipeline=basic-aa -passes='print<memoryssa>,verify<memoryssa>' -disable-output < %s 2>&1 | FileCheck %s
2;
3; Makes sure we have a sane model if both successors of some block is the same
4; block.
5
6define i32 @foo(i1 %a) {
7entry:
8  %0 = alloca i32, align 4
9; CHECK: 1 = MemoryDef(liveOnEntry)
10; CHECK-NEXT: store i32 4
11  store i32 4, ptr %0
12  br i1 %a, label %Loop.Body, label %Loop.End
13
14Loop.Body:
15; CHECK: 4 = MemoryPhi({entry,1},{Loop.End,3})
16; CHECK-NEXT: 2 = MemoryDef(4)
17; CHECK-NEXT: store i32 5
18  store i32 5, ptr %0, align 4
19  br i1 %a, label %Loop.End, label %Loop.End ; WhyDoWeEvenHaveThatLever.gif
20
21Loop.End:
22; CHECK: 3 = MemoryPhi({entry,1},{Loop.Body,2},{Loop.Body,2})
23; CHECK-NEXT: MemoryUse(3)
24; CHECK-NEXT: %1 = load
25  %1 = load i32, ptr %0, align 4
26  %2 = icmp eq i32 5, %1
27  br i1 %2, label %Ret, label %Loop.Body
28
29Ret:
30  ret i32 %1
31}
32