xref: /llvm-project/llvm/test/Analysis/CostModel/AMDGPU/shifts.ll (revision 4178e33470763b406f614b646c8b01d24309e20b) 
1; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
2; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 -mattr=+half-rate-64-ops < %s | FileCheck -check-prefixes=FAST64 %s
3; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mattr=-half-rate-64-ops < %s | FileCheck -check-prefixes=SLOW64 %s
4; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 -mattr=+half-rate-64-ops < %s | FileCheck -check-prefixes=FAST64-SIZE %s
5; RUN: opt -passes="print<cost-model>" -cost-kind=code-size 2>&1 -disable-output -mtriple=amdgcn-unknown-amdhsa -mattr=-half-rate-64-ops < %s | FileCheck -check-prefixes=SLOW64-SIZE %s
6; END.
7
8define amdgpu_kernel void @shl() #0 {
9; FAST64-LABEL: 'shl'
10; FAST64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i8 = shl i8 undef, undef
11; FAST64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = shl <2 x i8> undef, undef
12; FAST64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = shl <3 x i8> undef, undef
13; FAST64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = shl <4 x i8> undef, undef
14; FAST64-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = shl <5 x i8> undef, undef
15; FAST64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i16 = shl i16 undef, undef
16; FAST64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = shl <2 x i16> undef, undef
17; FAST64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v3i16 = shl <3 x i16> undef, undef
18; FAST64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = shl <4 x i16> undef, undef
19; FAST64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v5i16 = shl <5 x i16> undef, undef
20; FAST64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i32 = shl i32 undef, undef
21; FAST64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = shl <2 x i32> undef, undef
22; FAST64-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = shl <3 x i32> undef, undef
23; FAST64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = shl <4 x i32> undef, undef
24; FAST64-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = shl <5 x i32> undef, undef
25; FAST64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i64 = shl i64 undef, undef
26; FAST64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = shl <2 x i64> undef, undef
27; FAST64-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = shl <3 x i64> undef, undef
28; FAST64-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = shl <4 x i64> undef, undef
29; FAST64-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = shl <5 x i64> undef, undef
30; FAST64-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: ret void
31;
32; SLOW64-LABEL: 'shl'
33; SLOW64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i8 = shl i8 undef, undef
34; SLOW64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = shl <2 x i8> undef, undef
35; SLOW64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = shl <3 x i8> undef, undef
36; SLOW64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = shl <4 x i8> undef, undef
37; SLOW64-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = shl <5 x i8> undef, undef
38; SLOW64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i16 = shl i16 undef, undef
39; SLOW64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i16 = shl <2 x i16> undef, undef
40; SLOW64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v3i16 = shl <3 x i16> undef, undef
41; SLOW64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i16 = shl <4 x i16> undef, undef
42; SLOW64-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v5i16 = shl <5 x i16> undef, undef
43; SLOW64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i32 = shl i32 undef, undef
44; SLOW64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = shl <2 x i32> undef, undef
45; SLOW64-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = shl <3 x i32> undef, undef
46; SLOW64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = shl <4 x i32> undef, undef
47; SLOW64-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = shl <5 x i32> undef, undef
48; SLOW64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %i64 = shl i64 undef, undef
49; SLOW64-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v2i64 = shl <2 x i64> undef, undef
50; SLOW64-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %v3i64 = shl <3 x i64> undef, undef
51; SLOW64-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %v4i64 = shl <4 x i64> undef, undef
52; SLOW64-NEXT:  Cost Model: Found an estimated cost of 96 for instruction: %v5i64 = shl <5 x i64> undef, undef
53; SLOW64-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: ret void
54;
55; FAST64-SIZE-LABEL: 'shl'
56; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i8 = shl i8 undef, undef
57; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = shl <2 x i8> undef, undef
58; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = shl <3 x i8> undef, undef
59; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = shl <4 x i8> undef, undef
60; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = shl <5 x i8> undef, undef
61; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i16 = shl i16 undef, undef
62; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = shl <2 x i16> undef, undef
63; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v3i16 = shl <3 x i16> undef, undef
64; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = shl <4 x i16> undef, undef
65; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v5i16 = shl <5 x i16> undef, undef
66; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i32 = shl i32 undef, undef
67; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = shl <2 x i32> undef, undef
68; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = shl <3 x i32> undef, undef
69; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = shl <4 x i32> undef, undef
70; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = shl <5 x i32> undef, undef
71; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i64 = shl i64 undef, undef
72; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = shl <2 x i64> undef, undef
73; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = shl <3 x i64> undef, undef
74; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = shl <4 x i64> undef, undef
75; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = shl <5 x i64> undef, undef
76; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: ret void
77;
78; SLOW64-SIZE-LABEL: 'shl'
79; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i8 = shl i8 undef, undef
80; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = shl <2 x i8> undef, undef
81; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = shl <3 x i8> undef, undef
82; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = shl <4 x i8> undef, undef
83; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = shl <5 x i8> undef, undef
84; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i16 = shl i16 undef, undef
85; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i16 = shl <2 x i16> undef, undef
86; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v3i16 = shl <3 x i16> undef, undef
87; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i16 = shl <4 x i16> undef, undef
88; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v5i16 = shl <5 x i16> undef, undef
89; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i32 = shl i32 undef, undef
90; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = shl <2 x i32> undef, undef
91; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = shl <3 x i32> undef, undef
92; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = shl <4 x i32> undef, undef
93; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = shl <5 x i32> undef, undef
94; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i64 = shl i64 undef, undef
95; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = shl <2 x i64> undef, undef
96; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = shl <3 x i64> undef, undef
97; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = shl <4 x i64> undef, undef
98; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = shl <5 x i64> undef, undef
99; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: ret void
100;
101  %i8 = shl i8 undef, undef
102  %v2i8 = shl <2 x i8> undef, undef
103  %v3i8 = shl <3 x i8> undef, undef
104  %v4i8 = shl <4 x i8> undef, undef
105  %v5i8 = shl <5 x i8> undef, undef
106  %i16 = shl i16 undef, undef
107  %v2i16 = shl <2 x i16> undef, undef
108  %v3i16 = shl <3 x i16> undef, undef
109  %v4i16 = shl <4 x i16> undef, undef
110  %v5i16 = shl <5 x i16> undef, undef
111  %i32 = shl i32 undef, undef
112  %v2i32 = shl <2 x i32> undef, undef
113  %v3i32 = shl <3 x i32> undef, undef
114  %v4i32 = shl <4 x i32> undef, undef
115  %v5i32 = shl <5 x i32> undef, undef
116  %i64 = shl i64 undef, undef
117  %v2i64 = shl <2 x i64> undef, undef
118  %v3i64 = shl <3 x i64> undef, undef
119  %v4i64 = shl <4 x i64> undef, undef
120  %v5i64 = shl <5 x i64> undef, undef
121  ret void
122}
123
124define amdgpu_kernel void @lshr() #0 {
125; FAST64-LABEL: 'lshr'
126; FAST64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i8 = lshr i8 undef, undef
127; FAST64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = lshr <2 x i8> undef, undef
128; FAST64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = lshr <3 x i8> undef, undef
129; FAST64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = lshr <4 x i8> undef, undef
130; FAST64-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = lshr <5 x i8> undef, undef
131; FAST64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i16 = lshr i16 undef, undef
132; FAST64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = lshr <2 x i16> undef, undef
133; FAST64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v3i16 = lshr <3 x i16> undef, undef
134; FAST64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = lshr <4 x i16> undef, undef
135; FAST64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v5i16 = lshr <5 x i16> undef, undef
136; FAST64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i32 = lshr i32 undef, undef
137; FAST64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = lshr <2 x i32> undef, undef
138; FAST64-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = lshr <3 x i32> undef, undef
139; FAST64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = lshr <4 x i32> undef, undef
140; FAST64-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = lshr <5 x i32> undef, undef
141; FAST64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i64 = lshr i64 undef, undef
142; FAST64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = lshr <2 x i64> undef, undef
143; FAST64-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = lshr <3 x i64> undef, undef
144; FAST64-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = lshr <4 x i64> undef, undef
145; FAST64-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = lshr <5 x i64> undef, undef
146; FAST64-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: ret void
147;
148; SLOW64-LABEL: 'lshr'
149; SLOW64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i8 = lshr i8 undef, undef
150; SLOW64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = lshr <2 x i8> undef, undef
151; SLOW64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = lshr <3 x i8> undef, undef
152; SLOW64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = lshr <4 x i8> undef, undef
153; SLOW64-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = lshr <5 x i8> undef, undef
154; SLOW64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i16 = lshr i16 undef, undef
155; SLOW64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i16 = lshr <2 x i16> undef, undef
156; SLOW64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v3i16 = lshr <3 x i16> undef, undef
157; SLOW64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i16 = lshr <4 x i16> undef, undef
158; SLOW64-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v5i16 = lshr <5 x i16> undef, undef
159; SLOW64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i32 = lshr i32 undef, undef
160; SLOW64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = lshr <2 x i32> undef, undef
161; SLOW64-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = lshr <3 x i32> undef, undef
162; SLOW64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = lshr <4 x i32> undef, undef
163; SLOW64-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = lshr <5 x i32> undef, undef
164; SLOW64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %i64 = lshr i64 undef, undef
165; SLOW64-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v2i64 = lshr <2 x i64> undef, undef
166; SLOW64-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %v3i64 = lshr <3 x i64> undef, undef
167; SLOW64-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %v4i64 = lshr <4 x i64> undef, undef
168; SLOW64-NEXT:  Cost Model: Found an estimated cost of 96 for instruction: %v5i64 = lshr <5 x i64> undef, undef
169; SLOW64-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: ret void
170;
171; FAST64-SIZE-LABEL: 'lshr'
172; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i8 = lshr i8 undef, undef
173; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = lshr <2 x i8> undef, undef
174; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = lshr <3 x i8> undef, undef
175; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = lshr <4 x i8> undef, undef
176; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = lshr <5 x i8> undef, undef
177; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i16 = lshr i16 undef, undef
178; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = lshr <2 x i16> undef, undef
179; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v3i16 = lshr <3 x i16> undef, undef
180; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = lshr <4 x i16> undef, undef
181; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v5i16 = lshr <5 x i16> undef, undef
182; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i32 = lshr i32 undef, undef
183; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = lshr <2 x i32> undef, undef
184; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = lshr <3 x i32> undef, undef
185; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = lshr <4 x i32> undef, undef
186; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = lshr <5 x i32> undef, undef
187; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i64 = lshr i64 undef, undef
188; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = lshr <2 x i64> undef, undef
189; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = lshr <3 x i64> undef, undef
190; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = lshr <4 x i64> undef, undef
191; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = lshr <5 x i64> undef, undef
192; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: ret void
193;
194; SLOW64-SIZE-LABEL: 'lshr'
195; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i8 = lshr i8 undef, undef
196; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = lshr <2 x i8> undef, undef
197; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = lshr <3 x i8> undef, undef
198; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = lshr <4 x i8> undef, undef
199; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = lshr <5 x i8> undef, undef
200; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i16 = lshr i16 undef, undef
201; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i16 = lshr <2 x i16> undef, undef
202; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v3i16 = lshr <3 x i16> undef, undef
203; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i16 = lshr <4 x i16> undef, undef
204; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v5i16 = lshr <5 x i16> undef, undef
205; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i32 = lshr i32 undef, undef
206; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = lshr <2 x i32> undef, undef
207; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = lshr <3 x i32> undef, undef
208; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = lshr <4 x i32> undef, undef
209; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = lshr <5 x i32> undef, undef
210; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i64 = lshr i64 undef, undef
211; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = lshr <2 x i64> undef, undef
212; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = lshr <3 x i64> undef, undef
213; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = lshr <4 x i64> undef, undef
214; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = lshr <5 x i64> undef, undef
215; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: ret void
216;
217  %i8 = lshr i8 undef, undef
218  %v2i8 = lshr <2 x i8> undef, undef
219  %v3i8 = lshr <3 x i8> undef, undef
220  %v4i8 = lshr <4 x i8> undef, undef
221  %v5i8 = lshr <5 x i8> undef, undef
222  %i16 = lshr i16 undef, undef
223  %v2i16 = lshr <2 x i16> undef, undef
224  %v3i16 = lshr <3 x i16> undef, undef
225  %v4i16 = lshr <4 x i16> undef, undef
226  %v5i16 = lshr <5 x i16> undef, undef
227  %i32 = lshr i32 undef, undef
228  %v2i32 = lshr <2 x i32> undef, undef
229  %v3i32 = lshr <3 x i32> undef, undef
230  %v4i32 = lshr <4 x i32> undef, undef
231  %v5i32 = lshr <5 x i32> undef, undef
232  %i64 = lshr i64 undef, undef
233  %v2i64 = lshr <2 x i64> undef, undef
234  %v3i64 = lshr <3 x i64> undef, undef
235  %v4i64 = lshr <4 x i64> undef, undef
236  %v5i64 = lshr <5 x i64> undef, undef
237  ret void
238}
239
240define amdgpu_kernel void @ashr() #0 {
241; FAST64-LABEL: 'ashr'
242; FAST64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i8 = ashr i8 undef, undef
243; FAST64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = ashr <2 x i8> undef, undef
244; FAST64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = ashr <3 x i8> undef, undef
245; FAST64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = ashr <4 x i8> undef, undef
246; FAST64-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = ashr <5 x i8> undef, undef
247; FAST64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i16 = ashr i16 undef, undef
248; FAST64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = ashr <2 x i16> undef, undef
249; FAST64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v3i16 = ashr <3 x i16> undef, undef
250; FAST64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = ashr <4 x i16> undef, undef
251; FAST64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v5i16 = ashr <5 x i16> undef, undef
252; FAST64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i32 = ashr i32 undef, undef
253; FAST64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = ashr <2 x i32> undef, undef
254; FAST64-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = ashr <3 x i32> undef, undef
255; FAST64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = ashr <4 x i32> undef, undef
256; FAST64-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = ashr <5 x i32> undef, undef
257; FAST64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i64 = ashr i64 undef, undef
258; FAST64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = ashr <2 x i64> undef, undef
259; FAST64-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = ashr <3 x i64> undef, undef
260; FAST64-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = ashr <4 x i64> undef, undef
261; FAST64-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = ashr <5 x i64> undef, undef
262; FAST64-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: ret void
263;
264; SLOW64-LABEL: 'ashr'
265; SLOW64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i8 = ashr i8 undef, undef
266; SLOW64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = ashr <2 x i8> undef, undef
267; SLOW64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = ashr <3 x i8> undef, undef
268; SLOW64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = ashr <4 x i8> undef, undef
269; SLOW64-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = ashr <5 x i8> undef, undef
270; SLOW64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i16 = ashr i16 undef, undef
271; SLOW64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i16 = ashr <2 x i16> undef, undef
272; SLOW64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v3i16 = ashr <3 x i16> undef, undef
273; SLOW64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i16 = ashr <4 x i16> undef, undef
274; SLOW64-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v5i16 = ashr <5 x i16> undef, undef
275; SLOW64-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i32 = ashr i32 undef, undef
276; SLOW64-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = ashr <2 x i32> undef, undef
277; SLOW64-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = ashr <3 x i32> undef, undef
278; SLOW64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = ashr <4 x i32> undef, undef
279; SLOW64-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = ashr <5 x i32> undef, undef
280; SLOW64-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %i64 = ashr i64 undef, undef
281; SLOW64-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v2i64 = ashr <2 x i64> undef, undef
282; SLOW64-NEXT:  Cost Model: Found an estimated cost of 12 for instruction: %v3i64 = ashr <3 x i64> undef, undef
283; SLOW64-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %v4i64 = ashr <4 x i64> undef, undef
284; SLOW64-NEXT:  Cost Model: Found an estimated cost of 96 for instruction: %v5i64 = ashr <5 x i64> undef, undef
285; SLOW64-NEXT:  Cost Model: Found an estimated cost of 10 for instruction: ret void
286;
287; FAST64-SIZE-LABEL: 'ashr'
288; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i8 = ashr i8 undef, undef
289; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = ashr <2 x i8> undef, undef
290; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = ashr <3 x i8> undef, undef
291; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = ashr <4 x i8> undef, undef
292; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = ashr <5 x i8> undef, undef
293; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i16 = ashr i16 undef, undef
294; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %v2i16 = ashr <2 x i16> undef, undef
295; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v3i16 = ashr <3 x i16> undef, undef
296; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v4i16 = ashr <4 x i16> undef, undef
297; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v5i16 = ashr <5 x i16> undef, undef
298; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i32 = ashr i32 undef, undef
299; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = ashr <2 x i32> undef, undef
300; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = ashr <3 x i32> undef, undef
301; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = ashr <4 x i32> undef, undef
302; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = ashr <5 x i32> undef, undef
303; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i64 = ashr i64 undef, undef
304; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = ashr <2 x i64> undef, undef
305; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = ashr <3 x i64> undef, undef
306; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = ashr <4 x i64> undef, undef
307; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = ashr <5 x i64> undef, undef
308; FAST64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: ret void
309;
310; SLOW64-SIZE-LABEL: 'ashr'
311; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i8 = ashr i8 undef, undef
312; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i8 = ashr <2 x i8> undef, undef
313; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v3i8 = ashr <3 x i8> undef, undef
314; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i8 = ashr <4 x i8> undef, undef
315; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v5i8 = ashr <5 x i8> undef, undef
316; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i16 = ashr i16 undef, undef
317; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i16 = ashr <2 x i16> undef, undef
318; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v3i16 = ashr <3 x i16> undef, undef
319; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i16 = ashr <4 x i16> undef, undef
320; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v5i16 = ashr <5 x i16> undef, undef
321; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %i32 = ashr i32 undef, undef
322; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %v2i32 = ashr <2 x i32> undef, undef
323; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 3 for instruction: %v3i32 = ashr <3 x i32> undef, undef
324; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v4i32 = ashr <4 x i32> undef, undef
325; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 5 for instruction: %v5i32 = ashr <5 x i32> undef, undef
326; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %i64 = ashr i64 undef, undef
327; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 4 for instruction: %v2i64 = ashr <2 x i64> undef, undef
328; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 6 for instruction: %v3i64 = ashr <3 x i64> undef, undef
329; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %v4i64 = ashr <4 x i64> undef, undef
330; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 48 for instruction: %v5i64 = ashr <5 x i64> undef, undef
331; SLOW64-SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: ret void
332;
333  %i8 = ashr i8 undef, undef
334  %v2i8 = ashr <2 x i8> undef, undef
335  %v3i8 = ashr <3 x i8> undef, undef
336  %v4i8 = ashr <4 x i8> undef, undef
337  %v5i8 = ashr <5 x i8> undef, undef
338  %i16 = ashr i16 undef, undef
339  %v2i16 = ashr <2 x i16> undef, undef
340  %v3i16 = ashr <3 x i16> undef, undef
341  %v4i16 = ashr <4 x i16> undef, undef
342  %v5i16 = ashr <5 x i16> undef, undef
343  %i32 = ashr i32 undef, undef
344  %v2i32 = ashr <2 x i32> undef, undef
345  %v3i32 = ashr <3 x i32> undef, undef
346  %v4i32 = ashr <4 x i32> undef, undef
347  %v5i32 = ashr <5 x i32> undef, undef
348  %i64 = ashr i64 undef, undef
349  %v2i64 = ashr <2 x i64> undef, undef
350  %v3i64 = ashr <3 x i64> undef, undef
351  %v4i64 = ashr <4 x i64> undef, undef
352  %v5i64 = ashr <5 x i64> undef, undef
353  ret void
354}
355
356attributes #0 = { nounwind }
357