1; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py 2; RUN: opt -passes="print<cost-model>" 2>&1 -disable-output -mtriple aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s 3 4target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" 5 6define void @test_urem_srem_expand() { 7; CHECK-LABEL: 'test_urem_srem_expand' 8; CHECK-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %legal_type_urem_0 = urem <vscale x 16 x i8> undef, undef 9; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %legal_type_urem_1 = urem <vscale x 8 x i16> undef, undef 10; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %legal_type_urem_2 = urem <vscale x 4 x i32> undef, undef 11; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %legal_type_urem_3 = urem <vscale x 2 x i64> undef, undef 12; CHECK-NEXT: Cost Model: Found an estimated cost of 18 for instruction: %legal_type_srem_0 = srem <vscale x 16 x i8> undef, undef 13; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %legal_type_srem_1 = srem <vscale x 8 x i16> undef, undef 14; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %legal_type_srem_2 = srem <vscale x 4 x i32> undef, undef 15; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %legal_type_srem_3 = srem <vscale x 2 x i64> undef, undef 16; CHECK-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %split_type_urem_0 = urem <vscale x 32 x i8> undef, undef 17; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %split_type_urem_1 = urem <vscale x 16 x i16> undef, undef 18; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %split_type_urem_2 = urem <vscale x 8 x i32> undef, undef 19; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %split_type_urem_3 = urem <vscale x 4 x i64> undef, undef 20; CHECK-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %split_type_srem_0 = srem <vscale x 32 x i8> undef, undef 21; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %split_type_srem_1 = srem <vscale x 16 x i16> undef, undef 22; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %split_type_srem_2 = srem <vscale x 8 x i32> undef, undef 23; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %split_type_srem_3 = srem <vscale x 4 x i64> undef, undef 24; CHECK-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %widen_type_urem_0 = urem <vscale x 31 x i8> undef, undef 25; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %widen_type_urem_1 = urem <vscale x 15 x i16> undef, undef 26; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %widen_type_urem_2 = urem <vscale x 7 x i32> undef, undef 27; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %widen_type_urem_3 = urem <vscale x 3 x i64> undef, undef 28; CHECK-NEXT: Cost Model: Found an estimated cost of 36 for instruction: %widen_type_srem_0 = srem <vscale x 31 x i8> undef, undef 29; CHECK-NEXT: Cost Model: Found an estimated cost of 20 for instruction: %widen_type_srem_1 = srem <vscale x 15 x i16> undef, undef 30; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %widen_type_srem_2 = srem <vscale x 7 x i32> undef, undef 31; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %widen_type_srem_3 = srem <vscale x 3 x i64> undef, undef 32; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void 33; 34entry: 35 %legal_type_urem_0 = urem <vscale x 16 x i8> undef, undef 36 %legal_type_urem_1 = urem <vscale x 8 x i16> undef, undef 37 %legal_type_urem_2 = urem <vscale x 4 x i32> undef, undef 38 %legal_type_urem_3 = urem <vscale x 2 x i64> undef, undef 39 %legal_type_srem_0 = srem <vscale x 16 x i8> undef, undef 40 %legal_type_srem_1 = srem <vscale x 8 x i16> undef, undef 41 %legal_type_srem_2 = srem <vscale x 4 x i32> undef, undef 42 %legal_type_srem_3 = srem <vscale x 2 x i64> undef, undef 43 44 %split_type_urem_0 = urem <vscale x 32 x i8> undef, undef 45 %split_type_urem_1 = urem <vscale x 16 x i16> undef, undef 46 %split_type_urem_2 = urem <vscale x 8 x i32> undef, undef 47 %split_type_urem_3 = urem <vscale x 4 x i64> undef, undef 48 %split_type_srem_0 = srem <vscale x 32 x i8> undef, undef 49 %split_type_srem_1 = srem <vscale x 16 x i16> undef, undef 50 %split_type_srem_2 = srem <vscale x 8 x i32> undef, undef 51 %split_type_srem_3 = srem <vscale x 4 x i64> undef, undef 52 53 %widen_type_urem_0 = urem <vscale x 31 x i8> undef, undef 54 %widen_type_urem_1 = urem <vscale x 15 x i16> undef, undef 55 %widen_type_urem_2 = urem <vscale x 7 x i32> undef, undef 56 %widen_type_urem_3 = urem <vscale x 3 x i64> undef, undef 57 %widen_type_srem_0 = srem <vscale x 31 x i8> undef, undef 58 %widen_type_srem_1 = srem <vscale x 15 x i16> undef, undef 59 %widen_type_srem_2 = srem <vscale x 7 x i32> undef, undef 60 %widen_type_srem_3 = srem <vscale x 3 x i64> undef, undef 61 62 ret void 63} 64