1 //===-- XtensaInstrInfo.h - Xtensa Instruction Information ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 6 // See https://llvm.org/LICENSE.txt for license information. 7 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 // This file contains the Xtensa implementation of the TargetInstrInfo class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H 16 #define LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H 17 18 #include "Xtensa.h" 19 #include "XtensaRegisterInfo.h" 20 #include "llvm/CodeGen/TargetInstrInfo.h" 21 #include "llvm/CodeGen/TargetRegisterInfo.h" 22 23 #define GET_INSTRINFO_HEADER 24 25 #include "XtensaGenInstrInfo.inc" 26 27 namespace llvm { 28 29 class XtensaTargetMachine; 30 class XtensaSubtarget; 31 class XtensaInstrInfo : public XtensaGenInstrInfo { 32 const XtensaRegisterInfo RI; 33 const XtensaSubtarget &STI; 34 35 public: 36 XtensaInstrInfo(const XtensaSubtarget &STI); 37 38 void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, 39 MachineBasicBlock::iterator I) const; 40 41 unsigned getInstSizeInBytes(const MachineInstr &MI) const override; 42 43 // Return the XtensaRegisterInfo, which this class owns. 44 const XtensaRegisterInfo &getRegisterInfo() const { return RI; } 45 46 Register isLoadFromStackSlot(const MachineInstr &MI, 47 int &FrameIndex) const override; 48 49 Register isStoreToStackSlot(const MachineInstr &MI, 50 int &FrameIndex) const override; 51 52 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 53 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 54 bool KillSrc, bool RenamableDest = false, 55 bool RenamableSrc = false) const override; 56 57 void storeRegToStackSlot( 58 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, 59 bool isKill, int FrameIndex, const TargetRegisterClass *RC, 60 const TargetRegisterInfo *TRI, Register VReg, 61 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; 62 63 void loadRegFromStackSlot( 64 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 65 Register DestReg, int FrameIdx, const TargetRegisterClass *RC, 66 const TargetRegisterInfo *TRI, Register VReg, 67 MachineInstr::MIFlag Flags = MachineInstr::NoFlags) const override; 68 69 // Get the load and store opcodes for a given register class and offset. 70 void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, 71 unsigned &StoreOpcode, int64_t offset) const; 72 73 // Emit code before MBBI in MI to move immediate value Value into 74 // physical register Reg. 75 void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 76 unsigned *Reg, int64_t Value) const; 77 78 bool 79 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override; 80 81 MachineBasicBlock *getBranchDestBlock(const MachineInstr &MI) const override; 82 83 bool isBranchOffsetInRange(unsigned BranchOpc, 84 int64_t BrOffset) const override; 85 86 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, 87 MachineBasicBlock *&FBB, 88 SmallVectorImpl<MachineOperand> &Cond, 89 bool AllowModify) const override; 90 91 unsigned removeBranch(MachineBasicBlock &MBB, 92 int *BytesRemoved = nullptr) const override; 93 94 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, 95 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond, 96 const DebugLoc &DL, 97 int *BytesAdded = nullptr) const override; 98 99 void insertIndirectBranch(MachineBasicBlock &MBB, MachineBasicBlock &DestBB, 100 MachineBasicBlock &RestoreBB, const DebugLoc &DL, 101 int64_t BrOffset = 0, 102 RegScavenger *RS = nullptr) const override; 103 104 unsigned insertBranchAtInst(MachineBasicBlock &MBB, 105 MachineBasicBlock::iterator I, 106 MachineBasicBlock *TBB, 107 ArrayRef<MachineOperand> Cond, const DebugLoc &DL, 108 int *BytesAdded) const; 109 110 unsigned insertConstBranchAtInst(MachineBasicBlock &MBB, MachineInstr *I, 111 int64_t offset, 112 ArrayRef<MachineOperand> Cond, DebugLoc DL, 113 int *BytesAdded) const; 114 115 // Return true if MI is a conditional or unconditional branch. 116 // When returning true, set Cond to the mask of condition-code 117 // values on which the instruction will branch, and set Target 118 // to the operand that contains the branch target. This target 119 // can be a register or a basic block. 120 bool isBranch(const MachineBasicBlock::iterator &MI, 121 SmallVectorImpl<MachineOperand> &Cond, 122 const MachineOperand *&Target) const; 123 124 const XtensaSubtarget &getSubtarget() const { return STI; } 125 }; 126 } // end namespace llvm 127 128 #endif /* LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H */ 129