1 //===-- X86MCTargetDesc.h - X86 Target Descriptions -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file provides X86 specific target descriptions. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H 14 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86MCTARGETDESC_H 15 16 #include "llvm/ADT/SmallVector.h" 17 #include <cstdint> 18 #include <memory> 19 #include <string> 20 21 namespace llvm { 22 class formatted_raw_ostream; 23 class MCAsmBackend; 24 class MCCodeEmitter; 25 class MCContext; 26 class MCInst; 27 class MCInstPrinter; 28 class MCInstrInfo; 29 class MCObjectStreamer; 30 class MCObjectTargetWriter; 31 class MCObjectWriter; 32 class MCRegister; 33 class MCRegisterInfo; 34 class MCStreamer; 35 class MCSubtargetInfo; 36 class MCTargetOptions; 37 class MCTargetStreamer; 38 class Target; 39 class Triple; 40 class StringRef; 41 42 /// Flavour of dwarf regnumbers 43 /// 44 namespace DWARFFlavour { 45 enum { 46 X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2 47 }; 48 } 49 50 /// Native X86 register numbers 51 /// 52 namespace N86 { 53 enum { 54 EAX = 0, ECX = 1, EDX = 2, EBX = 3, ESP = 4, EBP = 5, ESI = 6, EDI = 7 55 }; 56 } 57 58 namespace X86_MC { 59 std::string ParseX86Triple(const Triple &TT); 60 61 unsigned getDwarfRegFlavour(const Triple &TT, bool isEH); 62 63 void initLLVMToSEHAndCVRegMapping(MCRegisterInfo *MRI); 64 65 66 /// Returns true if this instruction has a LOCK prefix. 67 bool hasLockPrefix(const MCInst &MI); 68 69 /// \param Op operand # of the memory operand. 70 /// 71 /// \returns true if the specified instruction has a 16-bit memory operand. 72 bool is16BitMemOperand(const MCInst &MI, unsigned Op, 73 const MCSubtargetInfo &STI); 74 75 /// \param Op operand # of the memory operand. 76 /// 77 /// \returns true if the specified instruction has a 32-bit memory operand. 78 bool is32BitMemOperand(const MCInst &MI, unsigned Op); 79 80 /// \param Op operand # of the memory operand. 81 /// 82 /// \returns true if the specified instruction has a 64-bit memory operand. 83 #ifndef NDEBUG 84 bool is64BitMemOperand(const MCInst &MI, unsigned Op); 85 #endif 86 87 /// Returns true if this instruction needs an Address-Size override prefix. 88 bool needsAddressSizeOverride(const MCInst &MI, const MCSubtargetInfo &STI, 89 int MemoryOperand, uint64_t TSFlags); 90 91 /// Create a X86 MCSubtargetInfo instance. This is exposed so Asm parser, etc. 92 /// do not need to go through TargetRegistry. 93 MCSubtargetInfo *createX86MCSubtargetInfo(const Triple &TT, StringRef CPU, 94 StringRef FS); 95 96 void emitInstruction(MCObjectStreamer &, const MCInst &Inst, 97 const MCSubtargetInfo &STI); 98 99 void emitPrefix(MCCodeEmitter &MCE, const MCInst &MI, SmallVectorImpl<char> &CB, 100 const MCSubtargetInfo &STI); 101 } 102 103 MCCodeEmitter *createX86MCCodeEmitter(const MCInstrInfo &MCII, 104 MCContext &Ctx); 105 106 MCAsmBackend *createX86_32AsmBackend(const Target &T, 107 const MCSubtargetInfo &STI, 108 const MCRegisterInfo &MRI, 109 const MCTargetOptions &Options); 110 MCAsmBackend *createX86_64AsmBackend(const Target &T, 111 const MCSubtargetInfo &STI, 112 const MCRegisterInfo &MRI, 113 const MCTargetOptions &Options); 114 115 /// Implements X86-only directives for assembly emission. 116 MCTargetStreamer *createX86AsmTargetStreamer(MCStreamer &S, 117 formatted_raw_ostream &OS, 118 MCInstPrinter *InstPrinter); 119 120 /// Implements X86-only directives for object files. 121 MCTargetStreamer *createX86ObjectTargetStreamer(MCStreamer &S, 122 const MCSubtargetInfo &STI); 123 124 /// Construct an X86 Windows COFF machine code streamer which will generate 125 /// PE/COFF format object files. 126 /// 127 /// Takes ownership of \p AB and \p CE. 128 MCStreamer *createX86WinCOFFStreamer(MCContext &C, 129 std::unique_ptr<MCAsmBackend> &&AB, 130 std::unique_ptr<MCObjectWriter> &&OW, 131 std::unique_ptr<MCCodeEmitter> &&CE); 132 133 MCStreamer *createX86ELFStreamer(const Triple &T, MCContext &Context, 134 std::unique_ptr<MCAsmBackend> &&MAB, 135 std::unique_ptr<MCObjectWriter> &&MOW, 136 std::unique_ptr<MCCodeEmitter> &&MCE); 137 138 /// Construct an X86 Mach-O object writer. 139 std::unique_ptr<MCObjectTargetWriter> 140 createX86MachObjectWriter(bool Is64Bit, uint32_t CPUType, uint32_t CPUSubtype); 141 142 /// Construct an X86 ELF object writer. 143 std::unique_ptr<MCObjectTargetWriter> 144 createX86ELFObjectWriter(bool IsELF64, uint8_t OSABI, uint16_t EMachine); 145 /// Construct an X86 Win COFF object writer. 146 std::unique_ptr<MCObjectTargetWriter> 147 createX86WinCOFFObjectWriter(bool Is64Bit); 148 149 /// \param Reg speicifed register. 150 /// \param Size the bit size of returned register. 151 /// \param High requires the high register. 152 /// 153 /// \returns the sub or super register of a specific X86 register. 154 MCRegister getX86SubSuperRegister(MCRegister Reg, unsigned Size, 155 bool High = false); 156 } // End llvm namespace 157 158 159 // Defines symbolic names for X86 registers. This defines a mapping from 160 // register name to register number. 161 // 162 #define GET_REGINFO_ENUM 163 #include "X86GenRegisterInfo.inc" 164 165 // Defines symbolic names for the X86 instructions. 166 // 167 #define GET_INSTRINFO_ENUM 168 #define GET_INSTRINFO_MC_HELPER_DECLS 169 #include "X86GenInstrInfo.inc" 170 171 #define GET_SUBTARGETINFO_ENUM 172 #include "X86GenSubtargetInfo.inc" 173 174 #define GET_X86_MNEMONIC_TABLES_H 175 #include "X86GenMnemonicTables.inc" 176 177 #endif 178