xref: /llvm-project/llvm/lib/Target/WebAssembly/WebAssembly.td (revision 35cce408eef1a253df12c0023c993d78b180b1f3)
1//- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8///
9/// \file
10/// This is a target description file for the WebAssembly architecture,
11/// which is also known as "wasm".
12///
13//===----------------------------------------------------------------------===//
14
15//===----------------------------------------------------------------------===//
16// Target-independent interfaces which we are implementing
17//===----------------------------------------------------------------------===//
18
19include "llvm/Target/Target.td"
20
21//===----------------------------------------------------------------------===//
22// WebAssembly Subtarget features.
23//===----------------------------------------------------------------------===//
24
25def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true",
26                                      "Enable Atomics">;
27
28def FeatureBulkMemory :
29      SubtargetFeature<"bulk-memory", "HasBulkMemory", "true",
30                       "Enable bulk memory operations">;
31
32def FeatureBulkMemoryOpt :
33      SubtargetFeature<"bulk-memory-opt", "HasBulkMemoryOpt", "true",
34                       "Enable bulk memory optimization operations">;
35
36def FeatureCallIndirectOverlong :
37      SubtargetFeature<"call-indirect-overlong", "HasCallIndirectOverlong", "true",
38                       "Enable overlong encoding for call_indirect immediates">;
39
40def FeatureExceptionHandling :
41      SubtargetFeature<"exception-handling", "HasExceptionHandling", "true",
42                       "Enable Wasm exception handling">;
43
44def FeatureExtendedConst :
45      SubtargetFeature<"extended-const", "HasExtendedConst", "true",
46                       "Enable extended const expressions">;
47
48def FeatureFP16 :
49      SubtargetFeature<"fp16", "HasFP16", "true",
50                       "Enable FP16 instructions">;
51
52def FeatureMultiMemory :
53      SubtargetFeature<"multimemory", "HasMultiMemory", "true",
54                       "Enable multiple memories">;
55
56def FeatureMultivalue :
57      SubtargetFeature<"multivalue",
58                       "HasMultivalue", "true",
59                       "Enable multivalue blocks, instructions, and functions">;
60
61def FeatureMutableGlobals :
62      SubtargetFeature<"mutable-globals", "HasMutableGlobals", "true",
63                       "Enable mutable globals">;
64
65def FeatureNontrappingFPToInt :
66      SubtargetFeature<"nontrapping-fptoint",
67                       "HasNontrappingFPToInt", "true",
68                       "Enable non-trapping float-to-int conversion operators">;
69
70def FeatureReferenceTypes :
71      SubtargetFeature<"reference-types", "HasReferenceTypes", "true",
72                       "Enable reference types">;
73
74def FeatureRelaxedSIMD :
75      SubtargetFeature<"relaxed-simd", "SIMDLevel", "RelaxedSIMD",
76                       "Enable relaxed-simd instructions">;
77
78def FeatureSignExt :
79      SubtargetFeature<"sign-ext", "HasSignExt", "true",
80                       "Enable sign extension operators">;
81
82def FeatureSIMD128 : SubtargetFeature<"simd128", "SIMDLevel", "SIMD128",
83                                      "Enable 128-bit SIMD">;
84
85def FeatureTailCall :
86      SubtargetFeature<"tail-call", "HasTailCall", "true",
87                       "Enable tail call instructions">;
88
89def FeatureWideArithmetic :
90      SubtargetFeature<"wide-arithmetic", "HasWideArithmetic", "true",
91                       "Enable wide-arithmetic instructions">;
92
93//===----------------------------------------------------------------------===//
94// Architectures.
95//===----------------------------------------------------------------------===//
96
97//===----------------------------------------------------------------------===//
98// Register File Description
99//===----------------------------------------------------------------------===//
100
101include "WebAssemblyRegisterInfo.td"
102
103//===----------------------------------------------------------------------===//
104// Instruction Descriptions
105//===----------------------------------------------------------------------===//
106
107include "WebAssemblyInstrInfo.td"
108
109def WebAssemblyInstrInfo : InstrInfo;
110
111//===----------------------------------------------------------------------===//
112// WebAssembly Processors supported.
113//===----------------------------------------------------------------------===//
114
115// Minimal Viable Product.
116def : ProcessorModel<"mvp", NoSchedModel, []>;
117
118// Generic processor: latest stable version.
119//
120// This includes features that have achieved phase 4 of the standards process,
121// and that are expected to work for most users in the current time, with
122// consideration given to available support in relevant engines and tools, and
123// the importance of the features.
124def : ProcessorModel<"generic", NoSchedModel,
125                      [FeatureBulkMemory, FeatureBulkMemoryOpt,
126                       FeatureCallIndirectOverlong, FeatureMultivalue,
127                       FeatureMutableGlobals, FeatureNontrappingFPToInt,
128                       FeatureReferenceTypes, FeatureSignExt]>;
129
130// Lime1: <https://github.com/WebAssembly/tool-conventions/blob/main/Lime.md#lime1>
131def : ProcessorModel<"lime1", NoSchedModel,
132                      [FeatureBulkMemoryOpt, FeatureCallIndirectOverlong,
133                       FeatureExtendedConst, FeatureMultivalue,
134                       FeatureMutableGlobals, FeatureNontrappingFPToInt,
135                       FeatureSignExt]>;
136
137// Latest and greatest experimental version of WebAssembly. Bugs included!
138def : ProcessorModel<"bleeding-edge", NoSchedModel,
139                      [FeatureAtomics, FeatureBulkMemory, FeatureBulkMemoryOpt,
140                       FeatureCallIndirectOverlong, FeatureExceptionHandling,
141                       FeatureExtendedConst, FeatureFP16, FeatureMultiMemory,
142                       FeatureMultivalue, FeatureMutableGlobals,
143                       FeatureNontrappingFPToInt, FeatureRelaxedSIMD,
144                       FeatureReferenceTypes, FeatureSIMD128, FeatureSignExt,
145                       FeatureTailCall]>;
146
147//===----------------------------------------------------------------------===//
148// Target Declaration
149//===----------------------------------------------------------------------===//
150
151def WebAssemblyAsmParser : AsmParser {
152  // The physical register names are not in the binary format or asm text
153  let ShouldEmitMatchRegisterName = 0;
154}
155
156def WebAssemblyAsmWriter : AsmWriter {
157  string AsmWriterClassName  = "InstPrinter";
158  int PassSubtarget = 0;
159  int Variant = 0;
160  bit isMCAsmWriter = 1;
161}
162
163def WebAssembly : Target {
164  let InstructionSet = WebAssemblyInstrInfo;
165  let AssemblyParsers  = [WebAssemblyAsmParser];
166  let AssemblyWriters = [WebAssemblyAsmWriter];
167}
168