1//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9def IsTargetXPLINK64 : Predicate<"Subtarget->isTargetXPLINK64()">; 10def IsTargetELF : Predicate<"Subtarget->isTargetELF()">; 11 12//===----------------------------------------------------------------------===// 13// Stack allocation 14//===----------------------------------------------------------------------===// 15 16// These pseudos carry values needed to compute the MaxcallFrameSize of the 17// function. The callseq_start node requires the hasSideEffects flag. 18let usesCustomInserter = 1, hasNoSchedulingInfo = 1, hasSideEffects = 1 in { 19 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 20 [(callseq_start timm:$amt1, timm:$amt2)]>; 21 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2), 22 [(callseq_end timm:$amt1, timm:$amt2)]>; 23} 24 25// Takes as input the value of the stack pointer after a dynamic allocation 26// has been made. Sets the output to the address of the dynamically- 27// allocated area itself, skipping the outgoing arguments. 28// 29// This expands to an LA or LAY instruction. We restrict the offset 30// to the range of LA and keep the LAY range in reserve for when 31// the size of the outgoing arguments is added. 32def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src), 33 [(set GR64:$dst, dynalloc12only:$src)]>; 34 35let Defs = [R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 36 usesCustomInserter = 1 in 37 def PROBED_ALLOCA : Pseudo<(outs GR64:$dst), 38 (ins GR64:$oldSP, GR64:$space), 39 [(set GR64:$dst, (z_probed_alloca GR64:$oldSP, GR64:$space))]>; 40 41let Defs = [R1D, R15D, CC], Uses = [R15D], hasNoSchedulingInfo = 1, 42 hasSideEffects = 1 in 43 def PROBED_STACKALLOC : Pseudo<(outs), (ins i64imm:$stacksize), []>; 44 45let Defs = [R3D, CC], Uses = [R3D, R4D], hasNoSchedulingInfo = 1, 46 hasSideEffects = 1 in 47 def XPLINK_STACKALLOC : Pseudo<(outs), (ins), []>; 48 49//===----------------------------------------------------------------------===// 50// Branch instructions 51//===----------------------------------------------------------------------===// 52 53// Conditional branches. 54let isBranch = 1, isTerminator = 1, Uses = [CC] in { 55 // It's easier for LLVM to handle these branches in their raw BRC/BRCL form 56 // with the condition-code mask being the first operand. It seems friendlier 57 // to use mnemonic forms like JE and JLH when writing out the assembly though. 58 let isCodeGenOnly = 1 in { 59 // An assembler extended mnemonic for BRC. 60 def BRC : CondBranchRI <"j#", 0xA74, z_br_ccmask>; 61 // An assembler extended mnemonic for BRCL. (The extension is "G" 62 // rather than "L" because "JL" is "Jump if Less".) 63 def BRCL : CondBranchRIL<"jg#", 0xC04>; 64 let isIndirectBranch = 1 in { 65 def BC : CondBranchRX<"b#", 0x47>; 66 def BCR : CondBranchRR<"b#r", 0x07>; 67 def BIC : CondBranchRXY<"bi#", 0xe347>, 68 Requires<[FeatureMiscellaneousExtensions2]>; 69 } 70 } 71 72 // Allow using the raw forms directly from the assembler (and occasional 73 // special code generation needs) as well. 74 def BRCAsm : AsmCondBranchRI <"brc", 0xA74>; 75 def BRCLAsm : AsmCondBranchRIL<"brcl", 0xC04>; 76 let isIndirectBranch = 1 in { 77 def BCAsm : AsmCondBranchRX<"bc", 0x47>; 78 def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; 79 def BICAsm : AsmCondBranchRXY<"bic", 0xe347>, 80 Requires<[FeatureMiscellaneousExtensions2]>; 81 } 82 83 // Define AsmParser extended mnemonics for each general condition-code mask 84 // (integer or floating-point) 85 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 86 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 87 def JAsm#V : FixedCondBranchRI <CV<V>, "j#", 0xA74>; 88 def JGAsm#V : FixedCondBranchRIL<CV<V>, "j{g|l}#", 0xC04>; 89 let isIndirectBranch = 1 in { 90 def BAsm#V : FixedCondBranchRX <CV<V>, "b#", 0x47>; 91 def BRAsm#V : FixedCondBranchRR <CV<V>, "b#r", 0x07>; 92 def BIAsm#V : FixedCondBranchRXY<CV<V>, "bi#", 0xe347>, 93 Requires<[FeatureMiscellaneousExtensions2]>; 94 } 95 } 96} 97 98// Unconditional branches. These are in fact simply variants of the 99// conditional branches with the condition mask set to "always". 100let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 101 def J : FixedCondBranchRI <CondAlways, "j", 0xA74, br>; 102 def JG : FixedCondBranchRIL<CondAlways, "j{g|lu}", 0xC04>; 103 let isIndirectBranch = 1 in { 104 def B : FixedCondBranchRX<CondAlways, "b", 0x47>; 105 def BR : FixedCondBranchRR<CondAlways, "br", 0x07, brind>; 106 def BI : FixedCondBranchRXY<CondAlways, "bi", 0xe347, brind>, 107 Requires<[FeatureMiscellaneousExtensions2]>; 108 } 109} 110 111// NOPs. These are again variants of the conditional branches, with the 112// condition mask set to "never". 113defm NOP : NeverCondBranchRX<"nop", 0x47>; 114defm NOPR : NeverCondBranchRR<"nopr", 0x07>; 115def JNOP : NeverCondBranchRI<"jnop", 0xA74>; 116def JGNOP : NeverCondBranchRIL<"j{g|l}nop", 0xC04>; 117 118// Fused compare-and-branch instructions. 119// 120// These instructions do not use or clobber the condition codes. 121// We nevertheless pretend that the relative compare-and-branch 122// instructions clobber CC, so that we can lower them to separate 123// comparisons and BRCLs if the branch ends up being out of range. 124let isBranch = 1, isTerminator = 1 in { 125 // As for normal branches, we handle these instructions internally in 126 // their raw CRJ-like form, but use assembly macros like CRJE when writing 127 // them out. Using the *Pair multiclasses, we also create the raw forms. 128 let Defs = [CC] in { 129 defm CRJ : CmpBranchRIEbPair<"crj", 0xEC76, GR32>; 130 defm CGRJ : CmpBranchRIEbPair<"cgrj", 0xEC64, GR64>; 131 defm CIJ : CmpBranchRIEcPair<"cij", 0xEC7E, GR32, imm32sx8>; 132 defm CGIJ : CmpBranchRIEcPair<"cgij", 0xEC7C, GR64, imm64sx8>; 133 defm CLRJ : CmpBranchRIEbPair<"clrj", 0xEC77, GR32>; 134 defm CLGRJ : CmpBranchRIEbPair<"clgrj", 0xEC65, GR64>; 135 defm CLIJ : CmpBranchRIEcPair<"clij", 0xEC7F, GR32, imm32zx8>; 136 defm CLGIJ : CmpBranchRIEcPair<"clgij", 0xEC7D, GR64, imm64zx8>; 137 } 138 let isIndirectBranch = 1 in { 139 defm CRB : CmpBranchRRSPair<"crb", 0xECF6, GR32>; 140 defm CGRB : CmpBranchRRSPair<"cgrb", 0xECE4, GR64>; 141 defm CIB : CmpBranchRISPair<"cib", 0xECFE, GR32, imm32sx8>; 142 defm CGIB : CmpBranchRISPair<"cgib", 0xECFC, GR64, imm64sx8>; 143 defm CLRB : CmpBranchRRSPair<"clrb", 0xECF7, GR32>; 144 defm CLGRB : CmpBranchRRSPair<"clgrb", 0xECE5, GR64>; 145 defm CLIB : CmpBranchRISPair<"clib", 0xECFF, GR32, imm32zx8>; 146 defm CLGIB : CmpBranchRISPair<"clgib", 0xECFD, GR64, imm64zx8>; 147 } 148 149 // Define AsmParser mnemonics for each integer condition-code mask. 150 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 151 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 152 let Defs = [CC] in { 153 def CRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "crj", 0xEC76, GR32>; 154 def CGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "cgrj", 0xEC64, GR64>; 155 def CIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cij", 0xEC7E, GR32, 156 imm32sx8>; 157 def CGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "cgij", 0xEC7C, GR64, 158 imm64sx8>; 159 def CLRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clrj", 0xEC77, GR32>; 160 def CLGRJAsm#V : FixedCmpBranchRIEb<ICV<V>, "clgrj", 0xEC65, GR64>; 161 def CLIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clij", 0xEC7F, GR32, 162 imm32zx8>; 163 def CLGIJAsm#V : FixedCmpBranchRIEc<ICV<V>, "clgij", 0xEC7D, GR64, 164 imm64zx8>; 165 } 166 let isIndirectBranch = 1 in { 167 def CRBAsm#V : FixedCmpBranchRRS<ICV<V>, "crb", 0xECF6, GR32>; 168 def CGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "cgrb", 0xECE4, GR64>; 169 def CIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cib", 0xECFE, GR32, 170 imm32sx8>; 171 def CGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "cgib", 0xECFC, GR64, 172 imm64sx8>; 173 def CLRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clrb", 0xECF7, GR32>; 174 def CLGRBAsm#V : FixedCmpBranchRRS<ICV<V>, "clgrb", 0xECE5, GR64>; 175 def CLIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clib", 0xECFF, GR32, 176 imm32zx8>; 177 def CLGIBAsm#V : FixedCmpBranchRIS<ICV<V>, "clgib", 0xECFD, GR64, 178 imm64zx8>; 179 } 180 } 181} 182 183// Decrement a register and branch if it is nonzero. These don't clobber CC, 184// but we might need to split long relative branches into sequences that do. 185let isBranch = 1, isTerminator = 1 in { 186 let Defs = [CC] in { 187 def BRCT : BranchUnaryRI<"brct", 0xA76, GR32>; 188 def BRCTG : BranchUnaryRI<"brctg", 0xA77, GR64>; 189 } 190 // This doesn't need to clobber CC since we never need to split it. 191 def BRCTH : BranchUnaryRIL<"brcth", 0xCC6, GRH32>, 192 Requires<[FeatureHighWord]>; 193 194 def BCT : BranchUnaryRX<"bct", 0x46,GR32>; 195 def BCTR : BranchUnaryRR<"bctr", 0x06, GR32>; 196 def BCTG : BranchUnaryRXY<"bctg", 0xE346, GR64>; 197 def BCTGR : BranchUnaryRRE<"bctgr", 0xB946, GR64>; 198} 199 200let isBranch = 1, isTerminator = 1 in { 201 let Defs = [CC] in { 202 def BRXH : BranchBinaryRSI<"brxh", 0x84, GR32>; 203 def BRXLE : BranchBinaryRSI<"brxle", 0x85, GR32>; 204 def BRXHG : BranchBinaryRIEe<"brxhg", 0xEC44, GR64>; 205 def BRXLG : BranchBinaryRIEe<"brxlg", 0xEC45, GR64>; 206 } 207 def BXH : BranchBinaryRS<"bxh", 0x86, GR32>; 208 def BXLE : BranchBinaryRS<"bxle", 0x87, GR32>; 209 def BXHG : BranchBinaryRSY<"bxhg", 0xEB44, GR64>; 210 def BXLEG : BranchBinaryRSY<"bxleg", 0xEB45, GR64>; 211} 212 213//===----------------------------------------------------------------------===// 214// Trap instructions 215//===----------------------------------------------------------------------===// 216 217// Unconditional trap. 218let hasCtrlDep = 1, hasSideEffects = 1 in 219 def Trap : Alias<4, (outs), (ins), [(trap)]>; 220 221// Conditional trap. 222let hasCtrlDep = 1, Uses = [CC], hasSideEffects = 1 in 223 def CondTrap : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 224 225// Fused compare-and-trap instructions. 226let hasCtrlDep = 1, hasSideEffects = 1 in { 227 // These patterns work the same way as for compare-and-branch. 228 defm CRT : CmpBranchRRFcPair<"crt", 0xB972, GR32>; 229 defm CGRT : CmpBranchRRFcPair<"cgrt", 0xB960, GR64>; 230 defm CLRT : CmpBranchRRFcPair<"clrt", 0xB973, GR32>; 231 defm CLGRT : CmpBranchRRFcPair<"clgrt", 0xB961, GR64>; 232 defm CIT : CmpBranchRIEaPair<"cit", 0xEC72, GR32, imm32sx16>; 233 defm CGIT : CmpBranchRIEaPair<"cgit", 0xEC70, GR64, imm64sx16>; 234 defm CLFIT : CmpBranchRIEaPair<"clfit", 0xEC73, GR32, imm32zx16>; 235 defm CLGIT : CmpBranchRIEaPair<"clgit", 0xEC71, GR64, imm64zx16>; 236 let Predicates = [FeatureMiscellaneousExtensions] in { 237 defm CLT : CmpBranchRSYbPair<"clt", 0xEB23, GR32>; 238 defm CLGT : CmpBranchRSYbPair<"clgt", 0xEB2B, GR64>; 239 } 240 241 foreach V = [ "E", "H", "L", "HE", "LE", "LH", 242 "NE", "NH", "NL", "NHE", "NLE", "NLH" ] in { 243 def CRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "crt", 0xB972, GR32>; 244 def CGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "cgrt", 0xB960, GR64>; 245 def CLRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clrt", 0xB973, GR32>; 246 def CLGRTAsm#V : FixedCmpBranchRRFc<ICV<V>, "clgrt", 0xB961, GR64>; 247 def CITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cit", 0xEC72, GR32, 248 imm32sx16>; 249 def CGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "cgit", 0xEC70, GR64, 250 imm64sx16>; 251 def CLFITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clfit", 0xEC73, GR32, 252 imm32zx16>; 253 def CLGITAsm#V : FixedCmpBranchRIEa<ICV<V>, "clgit", 0xEC71, GR64, 254 imm64zx16>; 255 let Predicates = [FeatureMiscellaneousExtensions] in { 256 def CLTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clt", 0xEB23, GR32>; 257 def CLGTAsm#V : FixedCmpBranchRSYb<ICV<V>, "clgt", 0xEB2B, GR64>; 258 } 259 } 260} 261 262//===----------------------------------------------------------------------===// 263// Call and return instructions 264//===----------------------------------------------------------------------===// 265 266// Define the general form of the call instructions for the asm parser. 267// These instructions don't hard-code %r14 as the return address register. 268let isCall = 1, Defs = [CC] in { 269 def BRAS : CallRI <"bras", 0xA75>; 270 def BRASL : CallRIL<"brasl", 0xC05>; 271 def BAS : CallRX <"bas", 0x4D>; 272 def BASR : CallRR <"basr", 0x0D>; 273} 274 275// A symbol in the ADA (z/OS only). 276def adasym : Operand<i64>; 277 278// z/OS XPLINK 279let Predicates = [IsTargetXPLINK64] in { 280 let isCall = 1, Defs = [R7D, CC], Uses = [FPC] in { 281 def CallBRASL_XPLINK64 : Alias<8, (outs), (ins pcrel32:$I2, variable_ops), 282 [(z_call pcrel32:$I2)]>; 283 def CallBASR_XPLINK64 : Alias<4, (outs), (ins ADDR64:$R2, variable_ops), 284 [(z_call ADDR64:$R2)]>; 285 } 286 287 let isCall = 1, Defs = [R3D, CC], Uses = [FPC] in { 288 def CallBASR_STACKEXT : Alias<4, (outs), (ins ADDR64:$R2), []>; 289 } 290 291 let hasNoSchedulingInfo = 1, Defs = [CC] in { 292 def ADA_ENTRY : Alias<12, (outs ADDR64:$Reg), (ins adasym:$addr, 293 ADDR64:$ADA, imm64:$Offset), 294 [(set i64:$Reg, (z_ada_entry i64:$addr, 295 i64:$ADA, i64:$Offset))]>; 296 } 297 let mayLoad = 1, AddedComplexity = 20, hasNoSchedulingInfo = 1, Defs = [CC] in { 298 def ADA_ENTRY_VALUE : Alias<12, (outs ADDR64:$Reg), (ins adasym:$addr, 299 ADDR64:$ADA, imm64:$Offset), 300 [(set i64:$Reg, (z_load (z_ada_entry 301 iPTR:$addr, iPTR:$ADA, i64:$Offset)))]>; 302 } 303} 304 305// Regular calls. 306// z/Linux ELF 307let Predicates = [IsTargetELF] in { 308 let isCall = 1, Defs = [R14D, CC], Uses = [FPC] in { 309 def CallBRASL : Alias<6, (outs), (ins pcrel32:$I2, variable_ops), 310 [(z_call pcrel32:$I2)]>; 311 def CallBASR : Alias<2, (outs), (ins ADDR64:$R2, variable_ops), 312 [(z_call ADDR64:$R2)]>; 313 } 314 315 // TLS calls. These will be lowered into a call to __tls_get_offset, 316 // with an extra relocation specifying the TLS symbol. 317 let isCall = 1, Defs = [R14D, CC] in { 318 def TLS_GDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 319 [(z_tls_gdcall tglobaltlsaddr:$I2)]>; 320 def TLS_LDCALL : Alias<6, (outs), (ins tlssym:$I2, variable_ops), 321 [(z_tls_ldcall tglobaltlsaddr:$I2)]>; 322 } 323} 324 325// Sibling calls. Indirect sibling calls must be via R6 for XPLink, 326// R1 used for ELF 327let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 328 def CallJG : Alias<6, (outs), (ins pcrel32:$I2), 329 [(z_sibcall pcrel32:$I2)]>; 330 def CallBR : Alias<2, (outs), (ins ADDR64:$R2), 331 [(z_sibcall ADDR64:$R2)]>; 332} 333 334// Conditional sibling calls. 335let CCMaskFirst = 1, isCall = 1, isTerminator = 1, isReturn = 1 in { 336 def CallBRCL : Alias<6, (outs), (ins cond4:$valid, cond4:$R1, 337 pcrel32:$I2), []>; 338 def CallBCR : Alias<2, (outs), (ins cond4:$valid, cond4:$R1, 339 ADDR64:$R2), []>; 340} 341 342// Fused compare and conditional sibling calls. 343let isCall = 1, isTerminator = 1, isReturn = 1 in { 344 def CRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 345 def CGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 346 def CIBCall : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 347 def CGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3, ADDR64:$R4), []>; 348 def CLRBCall : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3, ADDR64:$R4), []>; 349 def CLGRBCall : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3, ADDR64:$R4), []>; 350 def CLIBCall : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 351 def CLGIBCall : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3, ADDR64:$R4), []>; 352} 353 354let Predicates = [IsTargetXPLINK64] in { 355 // A return instruction (b 2(%r7)). 356 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 357 def Return_XPLINK : Alias<4, (outs), (ins), [(z_retglue)]>; 358 359 // A conditional return instruction (bc <cond>, 2(%r7)). 360 let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 361 def CondReturn_XPLINK : Alias<4, (outs), (ins cond4:$valid, cond4:$R1), []>; 362} 363 364let Predicates = [IsTargetELF] in { 365 // A return instruction (br %r14). 366 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in 367 def Return : Alias<2, (outs), (ins), [(z_retglue)]>; 368 369 // A conditional return instruction (bcr <cond>, %r14). 370 let isReturn = 1, isTerminator = 1, hasCtrlDep = 1, CCMaskFirst = 1, Uses = [CC] in 371 def CondReturn : Alias<2, (outs), (ins cond4:$valid, cond4:$R1), []>; 372} 373 374// Fused compare and conditional returns. 375let isReturn = 1, isTerminator = 1, hasCtrlDep = 1 in { 376 def CRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 377 def CGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 378 def CIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32sx8:$I2, cond4:$M3), []>; 379 def CGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64sx8:$I2, cond4:$M3), []>; 380 def CLRBReturn : Alias<6, (outs), (ins GR32:$R1, GR32:$R2, cond4:$M3), []>; 381 def CLGRBReturn : Alias<6, (outs), (ins GR64:$R1, GR64:$R2, cond4:$M3), []>; 382 def CLIBReturn : Alias<6, (outs), (ins GR32:$R1, imm32zx8:$I2, cond4:$M3), []>; 383 def CLGIBReturn : Alias<6, (outs), (ins GR64:$R1, imm64zx8:$I2, cond4:$M3), []>; 384} 385 386//===----------------------------------------------------------------------===// 387// Select instructions 388//===----------------------------------------------------------------------===// 389 390def Select32 : SelectWrapper<i32, GR32>, 391 Requires<[FeatureNoLoadStoreOnCond]>; 392def Select64 : SelectWrapper<i64, GR64>, 393 Requires<[FeatureNoLoadStoreOnCond]>; 394 395// We don't define 32-bit Mux stores if we don't have STOCFH, because the 396// low-only STOC should then always be used if possible. 397defm CondStore8Mux : CondStores<GRX32, nonvolatile_truncstorei8, 398 nonvolatile_anyextloadi8, bdxaddr20only>, 399 Requires<[FeatureHighWord]>; 400defm CondStore16Mux : CondStores<GRX32, nonvolatile_truncstorei16, 401 nonvolatile_anyextloadi16, bdxaddr20only>, 402 Requires<[FeatureHighWord]>; 403defm CondStore32Mux : CondStores<GRX32, simple_store, 404 simple_load, bdxaddr20only>, 405 Requires<[FeatureLoadStoreOnCond2]>; 406defm CondStore8 : CondStores<GR32, nonvolatile_truncstorei8, 407 nonvolatile_anyextloadi8, bdxaddr20only>; 408defm CondStore16 : CondStores<GR32, nonvolatile_truncstorei16, 409 nonvolatile_anyextloadi16, bdxaddr20only>; 410defm CondStore32 : CondStores<GR32, simple_store, 411 simple_load, bdxaddr20only>; 412 413defm : CondStores64<CondStore8, CondStore8Inv, nonvolatile_truncstorei8, 414 nonvolatile_anyextloadi8, bdxaddr20only>; 415defm : CondStores64<CondStore16, CondStore16Inv, nonvolatile_truncstorei16, 416 nonvolatile_anyextloadi16, bdxaddr20only>; 417defm : CondStores64<CondStore32, CondStore32Inv, nonvolatile_truncstorei32, 418 nonvolatile_anyextloadi32, bdxaddr20only>; 419defm CondStore64 : CondStores<GR64, simple_store, 420 simple_load, bdxaddr20only>; 421 422//===----------------------------------------------------------------------===// 423// Move instructions 424//===----------------------------------------------------------------------===// 425 426// Register moves. 427def LR : UnaryRR <"lr", 0x18, null_frag, GR32, GR32>; 428def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>; 429 430let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 431 def LTR : UnaryRR <"ltr", 0x12, null_frag, GR32, GR32>; 432 def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>; 433} 434 435let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 436 def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>; 437 438// Immediate moves. 439let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 440 // 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF, 441 // deopending on the choice of register. 442 def LHIMux : UnaryRIPseudo<bitconvert, GRX32, imm32sx16>, 443 Requires<[FeatureHighWord]>; 444 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>; 445 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>; 446 447 // Other 16-bit immediates. 448 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>; 449 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>; 450 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>; 451 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>; 452 453 // 32-bit immediates. 454 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>; 455 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>; 456 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>; 457} 458def LLGFI : InstAlias<"llgfi\t$R1, $RI1", (LLILF GR64:$R1, imm64lf32:$RI1)>; 459def LLGHI : InstAlias<"llghi\t$R1, $RI1", (LLILL GR64:$R1, imm64ll16:$RI1)>; 460 461// Register loads. 462let canFoldAsLoad = 1, SimpleBDXLoad = 1, mayLoad = 1 in { 463 // Expands to L, LY or LFH, depending on the choice of register. 464 def LMux : UnaryRXYPseudo<"l", z_load, GRX32, 4>, 465 Requires<[FeatureHighWord]>; 466 defm L : UnaryRXPair<"l", 0x58, 0xE358, z_load, GR32, 4>; 467 def LFH : UnaryRXY<"lfh", 0xE3CA, z_load, GRH32, 4>, 468 Requires<[FeatureHighWord]>; 469 def LG : UnaryRXY<"lg", 0xE304, z_load, GR64, 8>; 470 471 // These instructions are split after register allocation, so we don't 472 // want a custom inserter. 473 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 474 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src), 475 [(set GR128:$dst, (load bdxaddr20only128:$src))]>; 476 } 477} 478let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 479 def LT : UnaryRXY<"lt", 0xE312, z_load, GR32, 4>; 480 def LTG : UnaryRXY<"ltg", 0xE302, z_load, GR64, 8>; 481} 482 483let canFoldAsLoad = 1 in { 484 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_z_load, GR32>; 485 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_z_load, GR64>; 486} 487 488// Load and zero rightmost byte. 489let Predicates = [FeatureLoadAndZeroRightmostByte] in { 490 def LZRF : UnaryRXY<"lzrf", 0xE33B, null_frag, GR32, 4>; 491 def LZRG : UnaryRXY<"lzrg", 0xE32A, null_frag, GR64, 8>; 492 def : Pat<(and (i32 (z_load bdxaddr20only:$src)), 0xffffff00), 493 (LZRF bdxaddr20only:$src)>; 494 def : Pat<(and (i64 (z_load bdxaddr20only:$src)), 0xffffffffffffff00), 495 (LZRG bdxaddr20only:$src)>; 496} 497 498// Load and trap. 499let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 500 def LAT : UnaryRXY<"lat", 0xE39F, null_frag, GR32, 4>; 501 def LFHAT : UnaryRXY<"lfhat", 0xE3C8, null_frag, GRH32, 4>; 502 def LGAT : UnaryRXY<"lgat", 0xE385, null_frag, GR64, 8>; 503} 504 505// Register stores. 506let SimpleBDXStore = 1, mayStore = 1 in { 507 // Expands to ST, STY or STFH, depending on the choice of register. 508 def STMux : StoreRXYPseudo<store, GRX32, 4>, 509 Requires<[FeatureHighWord]>; 510 defm ST : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>; 511 def STFH : StoreRXY<"stfh", 0xE3CB, store, GRH32, 4>, 512 Requires<[FeatureHighWord]>; 513 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>; 514 515 // These instructions are split after register allocation, so we don't 516 // want a custom inserter. 517 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in { 518 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst), 519 [(store GR128:$src, bdxaddr20only128:$dst)]>; 520 } 521} 522def STRL : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>; 523def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>; 524 525// 8-bit immediate stores to 8-bit fields. 526defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>; 527 528// 16-bit immediate stores to 16-, 32- or 64-bit fields. 529def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>; 530def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>; 531def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>; 532 533// Memory-to-memory moves. 534let mayLoad = 1, mayStore = 1 in 535 defm MVC : MemorySS<"mvc", 0xD2, z_mvc>; 536let mayLoad = 1, mayStore = 1, Defs = [CC] in { 537 def MVCL : SideEffectBinaryMemMemRR<"mvcl", 0x0E, GR128, GR128>; 538 def MVCLE : SideEffectTernaryMemMemRS<"mvcle", 0xA8, GR128, GR128>; 539 def MVCLU : SideEffectTernaryMemMemRSY<"mvclu", 0xEB8E, GR128, GR128>; 540} 541 542// Memset[Length][Byte] pseudos. 543def MemsetImmImm : MemsetPseudo<imm64, imm32zx8trunc>; 544def MemsetImmReg : MemsetPseudo<imm64, GR32>; 545def MemsetRegImm : MemsetPseudo<ADDR64, imm32zx8trunc>; 546def MemsetRegReg : MemsetPseudo<ADDR64, GR32>; 547 548// Move right. 549let Predicates = [FeatureMiscellaneousExtensions3], 550 mayLoad = 1, mayStore = 1, Uses = [R0L] in 551 def MVCRL : SideEffectBinarySSE<"mvcrl", 0xE50A>; 552 553// String moves. 554let mayLoad = 1, mayStore = 1, Defs = [CC] in 555 defm MVST : StringRRE<"mvst", 0xB255, z_stpcpy>; 556 557//===----------------------------------------------------------------------===// 558// Conditional move instructions 559//===----------------------------------------------------------------------===// 560 561let Predicates = [FeatureMiscellaneousExtensions3], Uses = [CC] in { 562 // Select. 563 let isCommutable = 1 in { 564 // Expands to SELR or SELFHR or a branch-and-move sequence, 565 // depending on the choice of registers. 566 def SELRMux : CondBinaryRRFaPseudo<"MUXselr", GRX32, GRX32, GRX32>; 567 defm SELFHR : CondBinaryRRFaPair<"selfhr", 0xB9C0, GRH32, GRH32, GRH32>; 568 defm SELR : CondBinaryRRFaPair<"selr", 0xB9F0, GR32, GR32, GR32>; 569 defm SELGR : CondBinaryRRFaPair<"selgr", 0xB9E3, GR64, GR64, GR64>; 570 } 571 572 // Define AsmParser extended mnemonics for each general condition-code mask. 573 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 574 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 575 def SELRAsm#V : FixedCondBinaryRRFa<CV<V>, "selr", 0xB9F0, 576 GR32, GR32, GR32>; 577 def SELFHRAsm#V : FixedCondBinaryRRFa<CV<V>, "selfhr", 0xB9C0, 578 GRH32, GRH32, GRH32>; 579 def SELGRAsm#V : FixedCondBinaryRRFa<CV<V>, "selgr", 0xB9E3, 580 GR64, GR64, GR64>; 581 } 582} 583 584let Predicates = [FeatureLoadStoreOnCond2], Uses = [CC] in { 585 // Load immediate on condition. Matched via DAG pattern and created 586 // by the PeepholeOptimizer via FoldImmediate. 587 588 // Expands to LOCHI or LOCHHI, depending on the choice of register. 589 def LOCHIMux : CondBinaryRIEPseudo<GRX32, imm32sx16>; 590 defm LOCHHI : CondBinaryRIEPair<"lochhi", 0xEC4E, GRH32, imm32sx16>; 591 defm LOCHI : CondBinaryRIEPair<"lochi", 0xEC42, GR32, imm32sx16>; 592 defm LOCGHI : CondBinaryRIEPair<"locghi", 0xEC46, GR64, imm64sx16>; 593 594 // Move register on condition. Matched via DAG pattern and 595 // created by early if-conversion. 596 let isCommutable = 1 in { 597 // Expands to LOCR or LOCFHR or a branch-and-move sequence, 598 // depending on the choice of registers. 599 def LOCRMux : CondBinaryRRFPseudo<"MUXlocr", GRX32, GRX32>; 600 defm LOCFHR : CondBinaryRRFPair<"locfhr", 0xB9E0, GRH32, GRH32>; 601 } 602 603 // Load on condition. Matched via DAG pattern. 604 // Expands to LOC or LOCFH, depending on the choice of register. 605 defm LOCMux : CondUnaryRSYPseudoAndMemFold<"MUXloc", simple_load, GRX32, 4>; 606 defm LOCFH : CondUnaryRSYPair<"locfh", 0xEBE0, simple_load, GRH32, 4>; 607 608 // Store on condition. Expanded from CondStore* pseudos. 609 // Expands to STOC or STOCFH, depending on the choice of register. 610 def STOCMux : CondStoreRSYPseudo<GRX32, 4>; 611 defm STOCFH : CondStoreRSYPair<"stocfh", 0xEBE1, GRH32, 4>; 612 613 // Define AsmParser extended mnemonics for each general condition-code mask. 614 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 615 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 616 def LOCHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochi", 0xEC42, GR32, 617 imm32sx16>; 618 def LOCGHIAsm#V : FixedCondBinaryRIE<CV<V>, "locghi", 0xEC46, GR64, 619 imm64sx16>; 620 def LOCHHIAsm#V : FixedCondBinaryRIE<CV<V>, "lochhi", 0xEC4E, GRH32, 621 imm32sx16>; 622 def LOCFHRAsm#V : FixedCondBinaryRRF<CV<V>, "locfhr", 0xB9E0, GRH32, GRH32>; 623 def LOCFHAsm#V : FixedCondUnaryRSY<CV<V>, "locfh", 0xEBE0, GRH32, 4>; 624 def STOCFHAsm#V : FixedCondStoreRSY<CV<V>, "stocfh", 0xEBE1, GRH32, 4>; 625 } 626} 627 628let Predicates = [FeatureLoadStoreOnCond], Uses = [CC] in { 629 // Move register on condition. Matched via DAG pattern and 630 // created by early if-conversion. 631 let isCommutable = 1 in { 632 defm LOCR : CondBinaryRRFPair<"locr", 0xB9F2, GR32, GR32>; 633 defm LOCGR : CondBinaryRRFPair<"locgr", 0xB9E2, GR64, GR64>; 634 } 635 636 // Load on condition. Matched via DAG pattern. 637 defm LOC : CondUnaryRSYPair<"loc", 0xEBF2, simple_load, GR32, 4>; 638 defm LOCG : CondUnaryRSYPairAndMemFold<"locg", 0xEBE2, simple_load, GR64, 8>; 639 640 // Store on condition. Expanded from CondStore* pseudos. 641 defm STOC : CondStoreRSYPair<"stoc", 0xEBF3, GR32, 4>; 642 defm STOCG : CondStoreRSYPair<"stocg", 0xEBE3, GR64, 8>; 643 644 // Define AsmParser extended mnemonics for each general condition-code mask. 645 foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 646 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 647 def LOCRAsm#V : FixedCondBinaryRRF<CV<V>, "locr", 0xB9F2, GR32, GR32>; 648 def LOCGRAsm#V : FixedCondBinaryRRF<CV<V>, "locgr", 0xB9E2, GR64, GR64>; 649 def LOCAsm#V : FixedCondUnaryRSY<CV<V>, "loc", 0xEBF2, GR32, 4>; 650 def LOCGAsm#V : FixedCondUnaryRSY<CV<V>, "locg", 0xEBE2, GR64, 8>; 651 def STOCAsm#V : FixedCondStoreRSY<CV<V>, "stoc", 0xEBF3, GR32, 4>; 652 def STOCGAsm#V : FixedCondStoreRSY<CV<V>, "stocg", 0xEBE3, GR64, 8>; 653 } 654} 655//===----------------------------------------------------------------------===// 656// Sign extensions 657//===----------------------------------------------------------------------===// 658// 659// Note that putting these before zero extensions mean that we will prefer 660// them for anyextload*. There's not really much to choose between the two 661// either way, but signed-extending loads have a short LH and a long LHY, 662// while zero-extending loads have only the long LLH. 663// 664//===----------------------------------------------------------------------===// 665 666// 32-bit extensions from registers. 667def LBR : UnaryRRE<"lbr", 0xB926, sext8, GR32, GR32>; 668def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>; 669 670// 64-bit extensions from registers. 671def LGBR : UnaryRRE<"lgbr", 0xB906, sext8, GR64, GR64>; 672def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>; 673def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>; 674 675let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 676 def LTGFR : UnaryRRE<"ltgfr", 0xB912, null_frag, GR64, GR32>; 677 678// Match 32-to-64-bit sign extensions in which the source is already 679// in a 64-bit register. 680def : Pat<(sext_inreg GR64:$src, i32), 681 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 682 683// 32-bit extensions from 8-bit memory. LBMux expands to LB or LBH, 684// depending on the choice of register. 685def LBMux : UnaryRXYPseudo<"lb", z_asextloadi8, GRX32, 1>, 686 Requires<[FeatureHighWord]>; 687def LB : UnaryRXY<"lb", 0xE376, z_asextloadi8, GR32, 1>; 688def LBH : UnaryRXY<"lbh", 0xE3C0, z_asextloadi8, GRH32, 1>, 689 Requires<[FeatureHighWord]>; 690 691// 32-bit extensions from 16-bit memory. LHMux expands to LH or LHH, 692// depending on the choice of register. 693def LHMux : UnaryRXYPseudo<"lh", z_asextloadi16, GRX32, 2>, 694 Requires<[FeatureHighWord]>; 695defm LH : UnaryRXPair<"lh", 0x48, 0xE378, z_asextloadi16, GR32, 2>; 696def LHH : UnaryRXY<"lhh", 0xE3C4, z_asextloadi16, GRH32, 2>, 697 Requires<[FeatureHighWord]>; 698def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_z_asextloadi16, GR32>; 699 700// 64-bit extensions from memory. 701def LGB : UnaryRXY<"lgb", 0xE377, z_asextloadi8, GR64, 1>; 702def LGH : UnaryRXY<"lgh", 0xE315, z_asextloadi16, GR64, 2>; 703def LGF : UnaryRXY<"lgf", 0xE314, z_asextloadi32, GR64, 4>; 704def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_z_asextloadi16, GR64>; 705def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_z_asextloadi32, GR64>; 706let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in 707 def LTGF : UnaryRXY<"ltgf", 0xE332, z_asextloadi32, GR64, 4>; 708 709//===----------------------------------------------------------------------===// 710// Zero extensions 711//===----------------------------------------------------------------------===// 712 713// 32-bit extensions from registers. 714 715// Expands to LLCR or RISB[LH]G, depending on the choice of registers. 716def LLCRMux : UnaryRRPseudo<"llcr", zext8, GRX32, GRX32>, 717 Requires<[FeatureHighWord]>; 718def LLCR : UnaryRRE<"llcr", 0xB994, zext8, GR32, GR32>; 719// Expands to LLHR or RISB[LH]G, depending on the choice of registers. 720def LLHRMux : UnaryRRPseudo<"llhr", zext16, GRX32, GRX32>, 721 Requires<[FeatureHighWord]>; 722def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>; 723 724// 64-bit extensions from registers. 725def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8, GR64, GR64>; 726def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>; 727def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>; 728 729// Match 32-to-64-bit zero extensions in which the source is already 730// in a 64-bit register. 731def : Pat<(and GR64:$src, 0xffffffff), 732 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_l32))>; 733 734// 32-bit extensions from 8-bit memory. LLCMux expands to LLC or LLCH, 735// depending on the choice of register. 736def LLCMux : UnaryRXYPseudo<"llc", z_azextloadi8, GRX32, 1>, 737 Requires<[FeatureHighWord]>; 738def LLC : UnaryRXY<"llc", 0xE394, z_azextloadi8, GR32, 1>; 739def LLCH : UnaryRXY<"llch", 0xE3C2, z_azextloadi8, GRH32, 1>, 740 Requires<[FeatureHighWord]>; 741 742// 32-bit extensions from 16-bit memory. LLHMux expands to LLH or LLHH, 743// depending on the choice of register. 744def LLHMux : UnaryRXYPseudo<"llh", z_azextloadi16, GRX32, 2>, 745 Requires<[FeatureHighWord]>; 746def LLH : UnaryRXY<"llh", 0xE395, z_azextloadi16, GR32, 2>; 747def LLHH : UnaryRXY<"llhh", 0xE3C6, z_azextloadi16, GRH32, 2>, 748 Requires<[FeatureHighWord]>; 749def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_z_azextloadi16, GR32>; 750 751// 64-bit extensions from memory. 752def LLGC : UnaryRXY<"llgc", 0xE390, z_azextloadi8, GR64, 1>; 753def LLGH : UnaryRXY<"llgh", 0xE391, z_azextloadi16, GR64, 2>; 754def LLGF : UnaryRXY<"llgf", 0xE316, z_azextloadi32, GR64, 4>; 755def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_z_azextloadi16, GR64>; 756def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_z_azextloadi32, GR64>; 757 758// 31-to-64-bit zero extensions. 759def LLGTR : UnaryRRE<"llgtr", 0xB917, null_frag, GR64, GR64>; 760def LLGT : UnaryRXY<"llgt", 0xE317, null_frag, GR64, 4>; 761def : Pat<(and GR64:$src, 0x7fffffff), 762 (LLGTR GR64:$src)>; 763def : Pat<(and (i64 (z_azextloadi32 bdxaddr20only:$src)), 0x7fffffff), 764 (LLGT bdxaddr20only:$src)>; 765 766// Load and zero rightmost byte. 767let Predicates = [FeatureLoadAndZeroRightmostByte] in { 768 def LLZRGF : UnaryRXY<"llzrgf", 0xE33A, null_frag, GR64, 4>; 769 def : Pat<(and (i64 (z_azextloadi32 bdxaddr20only:$src)), 0xffffff00), 770 (LLZRGF bdxaddr20only:$src)>; 771} 772 773// Load and trap. 774let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in { 775 def LLGFAT : UnaryRXY<"llgfat", 0xE39D, null_frag, GR64, 4>; 776 def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>; 777} 778 779// Extend GR64s to GR128s. 780let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 781 def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 782 783//===----------------------------------------------------------------------===// 784// "Any" extensions 785//===----------------------------------------------------------------------===// 786 787// Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext. 788def : Pat<(i64 (anyext GR32:$src)), 789 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>; 790 791// Extend GR64s to GR128s. 792let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in 793 def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>; 794 795//===----------------------------------------------------------------------===// 796// Truncations 797//===----------------------------------------------------------------------===// 798 799// Truncations of 64-bit registers to 32-bit registers. 800def : Pat<(i32 (trunc GR64:$src)), 801 (EXTRACT_SUBREG GR64:$src, subreg_l32)>; 802 803// Truncations of 32-bit registers to 8-bit memory. STCMux expands to 804// STC, STCY or STCH, depending on the choice of register. 805def STCMux : StoreRXYPseudo<truncstorei8, GRX32, 1>, 806 Requires<[FeatureHighWord]>; 807defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>; 808def STCH : StoreRXY<"stch", 0xE3C3, truncstorei8, GRH32, 1>, 809 Requires<[FeatureHighWord]>; 810 811// Truncations of 32-bit registers to 16-bit memory. STHMux expands to 812// STH, STHY or STHH, depending on the choice of register. 813def STHMux : StoreRXYPseudo<truncstorei16, GRX32, 1>, 814 Requires<[FeatureHighWord]>; 815defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>; 816def STHH : StoreRXY<"sthh", 0xE3C7, truncstorei16, GRH32, 2>, 817 Requires<[FeatureHighWord]>; 818def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>; 819 820// Truncations of 64-bit registers to memory. 821defm : StoreGR64Pair<STC, STCY, truncstorei8>; 822defm : StoreGR64Pair<STH, STHY, truncstorei16>; 823def : StoreGR64PC<STHRL, aligned_truncstorei16>; 824defm : StoreGR64Pair<ST, STY, truncstorei32>; 825def : StoreGR64PC<STRL, aligned_truncstorei32>; 826 827// Store characters under mask -- not (yet) used for codegen. 828defm STCM : StoreBinaryRSPair<"stcm", 0xBE, 0xEB2D, GR32, 0>; 829def STCMH : StoreBinaryRSY<"stcmh", 0xEB2C, GRH32, 0>; 830 831//===----------------------------------------------------------------------===// 832// Multi-register moves 833//===----------------------------------------------------------------------===// 834 835// Multi-register loads. 836defm LM : LoadMultipleRSPair<"lm", 0x98, 0xEB98, GR32>; 837def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>; 838def LMH : LoadMultipleRSY<"lmh", 0xEB96, GRH32>; 839def LMD : LoadMultipleSSe<"lmd", 0xEF, GR64>; 840 841// Multi-register stores. 842defm STM : StoreMultipleRSPair<"stm", 0x90, 0xEB90, GR32>; 843def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>; 844def STMH : StoreMultipleRSY<"stmh", 0xEB26, GRH32>; 845 846//===----------------------------------------------------------------------===// 847// Byte swaps 848//===----------------------------------------------------------------------===// 849 850// Byte-swapping register moves. 851def LRVR : UnaryRRE<"lrvr", 0xB91F, bswap, GR32, GR32>; 852def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>; 853 854// Byte-swapping loads. 855def LRVH : UnaryRXY<"lrvh", 0xE31F, z_loadbswap16, GR32, 2>; 856def LRV : UnaryRXY<"lrv", 0xE31E, z_loadbswap32, GR32, 4>; 857def LRVG : UnaryRXY<"lrvg", 0xE30F, z_loadbswap64, GR64, 8>; 858 859// Byte-swapping stores. 860def STRVH : StoreRXY<"strvh", 0xE33F, z_storebswap16, GR32, 2>; 861def STRV : StoreRXY<"strv", 0xE33E, z_storebswap32, GR32, 4>; 862def STRVG : StoreRXY<"strvg", 0xE32F, z_storebswap64, GR64, 8>; 863 864// Byte-swapping memory-to-memory moves. 865let mayLoad = 1, mayStore = 1 in 866 def MVCIN : SideEffectBinarySSa<"mvcin", 0xE8>; 867 868//===----------------------------------------------------------------------===// 869// Load address instructions 870//===----------------------------------------------------------------------===// 871 872// Load BDX-style addresses. 873let isAsCheapAsAMove = 1, isReMaterializable = 1 in 874 defm LA : LoadAddressRXPair<"la", 0x41, 0xE371, bitconvert>; 875 876// Load a PC-relative address. There's no version of this instruction 877// with a 16-bit offset, so there's no relaxation. 878let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in 879 def LARL : LoadAddressRIL<"larl", 0xC00, bitconvert>; 880 881// Load the Global Offset Table address. This will be lowered into a 882// larl $R1, _GLOBAL_OFFSET_TABLE_ 883// instruction. 884def GOT : Alias<6, (outs GR64:$R1), (ins), 885 [(set GR64:$R1, (global_offset_table))]>; 886 887// Load (logical) indexed address. 888let Predicates = [FeatureMiscellaneousExtensions4] in { 889 defm LXAB : LoadIndexedAddressRXY<"lxab", 0xE360, sext32>; 890 defm LXAH : LoadIndexedAddressRXY<"lxah", 0xE362, sext32, shl1>; 891 defm LXAF : LoadIndexedAddressRXY<"lxaf", 0xE364, sext32, shl2>; 892 defm LXAG : LoadIndexedAddressRXY<"lxag", 0xE366, sext32, shl3>; 893 defm LXAQ : LoadIndexedAddressRXY<"lxaq", 0xE368, sext32, shl4>; 894 defm LLXAB : LoadIndexedAddressRXY<"llxab", 0xE361, zext32>; 895 defm LLXAH : LoadIndexedAddressRXY<"llxah", 0xE363, zext32, shl1>; 896 defm LLXAF : LoadIndexedAddressRXY<"llxaf", 0xE365, zext32, shl2>; 897 defm LLXAG : LoadIndexedAddressRXY<"llxag", 0xE367, zext32, shl3>; 898 defm LLXAQ : LoadIndexedAddressRXY<"llxaq", 0xE369, zext32, shl4>; 899 900 // Peepholes to use load (logical) indexed address to implement 901 // add + shift of an already extended value. 902 def : Pat<(add ADDR64:$base, (shl1 (assertsext32 ADDR64:$index))), 903 (LXAH ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>; 904 def : Pat<(add ADDR64:$base, (shl2 (assertsext32 ADDR64:$index))), 905 (LXAF ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>; 906 def : Pat<(add ADDR64:$base, (shl3 (assertsext32 ADDR64:$index))), 907 (LXAG ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>; 908 def : Pat<(add ADDR64:$base, (shl4 (assertsext32 ADDR64:$index))), 909 (LXAQ ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>; 910 def : Pat<(add ADDR64:$base, (shl1 (assertzext32 ADDR64:$index))), 911 (LLXAH ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>; 912 def : Pat<(add ADDR64:$base, (shl2 (assertzext32 ADDR64:$index))), 913 (LLXAF ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>; 914 def : Pat<(add ADDR64:$base, (shl3 (assertzext32 ADDR64:$index))), 915 (LLXAG ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>; 916 def : Pat<(add ADDR64:$base, (shl4 (assertzext32 ADDR64:$index))), 917 (LLXAQ ADDR64:$base, 0, (EXTRACT_SUBREG ADDR64:$index, subreg_l32))>; 918} 919 920//===----------------------------------------------------------------------===// 921// Absolute and Negation 922//===----------------------------------------------------------------------===// 923 924let Defs = [CC] in { 925 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 926 def LPR : UnaryRR <"lpr", 0x10, abs, GR32, GR32>; 927 def LPGR : UnaryRRE<"lpgr", 0xB900, abs, GR64, GR64>; 928 } 929 let CCValues = 0xE, CompareZeroCCMask = 0xE in 930 def LPGFR : UnaryRRE<"lpgfr", 0xB910, null_frag, GR64, GR32>; 931} 932defm : SXU<abs, LPGFR>; 933 934let Defs = [CC] in { 935 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 936 def LNR : UnaryRR <"lnr", 0x11, z_inegabs, GR32, GR32>; 937 def LNGR : UnaryRRE<"lngr", 0xB901, z_inegabs, GR64, GR64>; 938 } 939 let CCValues = 0xE, CompareZeroCCMask = 0xE in 940 def LNGFR : UnaryRRE<"lngfr", 0xB911, null_frag, GR64, GR32>; 941} 942defm : SXU<z_inegabs, LNGFR>; 943 944let Defs = [CC] in { 945 let CCValues = 0xF, CompareZeroCCMask = 0x8 in { 946 def LCR : UnaryRR <"lcr", 0x13, ineg, GR32, GR32>; 947 def LCGR : UnaryRRE<"lcgr", 0xB903, ineg, GR64, GR64>; 948 } 949 let CCValues = 0xE, CompareZeroCCMask = 0xE in 950 def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>; 951} 952defm : SXU<ineg, LCGFR>; 953 954//===----------------------------------------------------------------------===// 955// Insertion 956//===----------------------------------------------------------------------===// 957 958let isCodeGenOnly = 1 in 959 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, z_azextloadi8, 1>; 960defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, z_azextloadi8, 1>; 961 962defm : InsertMem<"inserti8", IC32, GR32, z_azextloadi8, bdxaddr12pair>; 963defm : InsertMem<"inserti8", IC32Y, GR32, z_azextloadi8, bdxaddr20pair>; 964 965defm : InsertMem<"inserti8", IC, GR64, z_azextloadi8, bdxaddr12pair>; 966defm : InsertMem<"inserti8", ICY, GR64, z_azextloadi8, bdxaddr20pair>; 967 968// Insert characters under mask -- not (yet) used for codegen. 969let Defs = [CC] in { 970 defm ICM : TernaryRSPair<"icm", 0xBF, 0xEB81, GR32, 0>; 971 def ICMH : TernaryRSY<"icmh", 0xEB80, GRH32, 0>; 972} 973 974// Insertions of a 16-bit immediate, leaving other bits unaffected. 975// We don't have or_as_insert equivalents of these operations because 976// OI is available instead. 977// 978// IIxMux expands to II[LH]x, depending on the choice of register. 979def IILMux : BinaryRIPseudo<insertll, GRX32, imm32ll16>, 980 Requires<[FeatureHighWord]>; 981def IIHMux : BinaryRIPseudo<insertlh, GRX32, imm32lh16>, 982 Requires<[FeatureHighWord]>; 983def IILL : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>; 984def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>; 985def IIHL : BinaryRI<"iihl", 0xA51, insertll, GRH32, imm32ll16>; 986def IIHH : BinaryRI<"iihh", 0xA50, insertlh, GRH32, imm32lh16>; 987def IILL64 : BinaryAliasRI<insertll64, GR64, imm64ll16>; 988def IILH64 : BinaryAliasRI<insertlh64, GR64, imm64lh16>; 989def IIHL64 : BinaryAliasRI<inserthl64, GR64, imm64hl16>; 990def IIHH64 : BinaryAliasRI<inserthh64, GR64, imm64hh16>; 991 992// ...likewise for 32-bit immediates. For GR32s this is a general 993// full-width move. (We use IILF rather than something like LLILF 994// for 32-bit moves because IILF leaves the upper 32 bits of the 995// GR64 unchanged.) 996let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in { 997 def IIFMux : UnaryRIPseudo<bitconvert, GRX32, uimm32>, 998 Requires<[FeatureHighWord]>; 999 def IILF : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>; 1000 def IIHF : UnaryRIL<"iihf", 0xC08, bitconvert, GRH32, uimm32>; 1001} 1002def LFI : InstAlias<"lfi\t$R1, $RI1", (IILF GR32:$R1, uimm32:$RI1)>; 1003def IILF64 : BinaryAliasRIL<insertlf, GR64, imm64lf32>; 1004def IIHF64 : BinaryAliasRIL<inserthf, GR64, imm64hf32>; 1005 1006// An alternative model of inserthf, with the first operand being 1007// a zero-extended value. 1008def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm), 1009 (IIHF64 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 1010 imm64hf32:$imm)>; 1011 1012//===----------------------------------------------------------------------===// 1013// Addition 1014//===----------------------------------------------------------------------===// 1015 1016// Addition producing a signed overflow flag. 1017let Defs = [CC], CCValues = 0xF, CCIfNoSignedWrap = 1 in { 1018 // Addition of a register. 1019 let isCommutable = 1 in { 1020 defm AR : BinaryRRAndK<"ar", 0x1A, 0xB9F8, z_sadd, GR32, GR32>; 1021 defm AGR : BinaryRREAndK<"agr", 0xB908, 0xB9E8, z_sadd, GR64, GR64>; 1022 } 1023 def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>; 1024 1025 // Addition to a high register. 1026 def AHHHR : BinaryRRFa<"ahhhr", 0xB9C8, null_frag, GRH32, GRH32, GRH32>, 1027 Requires<[FeatureHighWord]>; 1028 def AHHLR : BinaryRRFa<"ahhlr", 0xB9D8, null_frag, GRH32, GRH32, GR32>, 1029 Requires<[FeatureHighWord]>; 1030 1031 // Addition of signed 16-bit immediates. 1032 defm AHIMux : BinaryRIAndKPseudo<"ahimux", z_sadd, GRX32, imm32sx16>; 1033 defm AHI : BinaryRIAndK<"ahi", 0xA7A, 0xECD8, z_sadd, GR32, imm32sx16>; 1034 defm AGHI : BinaryRIAndK<"aghi", 0xA7B, 0xECD9, z_sadd, GR64, imm64sx16>; 1035 1036 // Addition of signed 32-bit immediates. 1037 def AFIMux : BinaryRIPseudo<z_sadd, GRX32, simm32>, 1038 Requires<[FeatureHighWord]>; 1039 def AFI : BinaryRIL<"afi", 0xC29, z_sadd, GR32, simm32>; 1040 def AIH : BinaryRIL<"aih", 0xCC8, z_sadd, GRH32, simm32>, 1041 Requires<[FeatureHighWord]>; 1042 def AGFI : BinaryRIL<"agfi", 0xC28, z_sadd, GR64, imm64sx32>; 1043 1044 // Addition of memory. 1045 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, z_sadd, GR32, z_asextloadi16, 2>; 1046 defm A : BinaryRXPairAndPseudo<"a", 0x5A, 0xE35A, z_sadd, GR32, z_load, 4>; 1047 def AGH : BinaryRXY<"agh", 0xE338, z_sadd, GR64, z_asextloadi16, 2>, 1048 Requires<[FeatureMiscellaneousExtensions2]>; 1049 def AGF : BinaryRXY<"agf", 0xE318, z_sadd, GR64, z_asextloadi32, 4>; 1050 defm AG : BinaryRXYAndPseudo<"ag", 0xE308, z_sadd, GR64, z_load, 8>; 1051 1052 // Addition to memory. 1053 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>; 1054 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>; 1055} 1056defm : SXB<z_sadd, GR64, AGFR>; 1057 1058// Addition producing a carry. 1059let Defs = [CC], CCValues = 0xF, IsLogical = 1 in { 1060 // Addition of a register. 1061 let isCommutable = 1 in { 1062 defm ALR : BinaryRRAndK<"alr", 0x1E, 0xB9FA, z_uadd, GR32, GR32>; 1063 defm ALGR : BinaryRREAndK<"algr", 0xB90A, 0xB9EA, z_uadd, GR64, GR64>; 1064 } 1065 def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>; 1066 1067 // Addition to a high register. 1068 def ALHHHR : BinaryRRFa<"alhhhr", 0xB9CA, null_frag, GRH32, GRH32, GRH32>, 1069 Requires<[FeatureHighWord]>; 1070 def ALHHLR : BinaryRRFa<"alhhlr", 0xB9DA, null_frag, GRH32, GRH32, GR32>, 1071 Requires<[FeatureHighWord]>; 1072 1073 // Addition of signed 16-bit immediates. 1074 def ALHSIK : BinaryRIE<"alhsik", 0xECDA, z_uadd, GR32, imm32sx16>, 1075 Requires<[FeatureDistinctOps]>; 1076 def ALGHSIK : BinaryRIE<"alghsik", 0xECDB, z_uadd, GR64, imm64sx16>, 1077 Requires<[FeatureDistinctOps]>; 1078 1079 // Addition of unsigned 32-bit immediates. 1080 def ALFI : BinaryRIL<"alfi", 0xC2B, z_uadd, GR32, uimm32>; 1081 def ALGFI : BinaryRIL<"algfi", 0xC2A, z_uadd, GR64, imm64zx32>; 1082 1083 // Addition of signed 32-bit immediates. 1084 def ALSIH : BinaryRIL<"alsih", 0xCCA, null_frag, GRH32, simm32>, 1085 Requires<[FeatureHighWord]>; 1086 1087 // Addition of memory. 1088 defm AL : BinaryRXPairAndPseudo<"al", 0x5E, 0xE35E, z_uadd, GR32, z_load, 4>; 1089 def ALGF : BinaryRXY<"algf", 0xE31A, z_uadd, GR64, z_azextloadi32, 4>; 1090 defm ALG : BinaryRXYAndPseudo<"alg", 0xE30A, z_uadd, GR64, z_load, 8>; 1091 1092 // Addition to memory. 1093 def ALSI : BinarySIY<"alsi", 0xEB6E, null_frag, imm32sx8>; 1094 def ALGSI : BinarySIY<"algsi", 0xEB7E, null_frag, imm64sx8>; 1095} 1096defm : ZXB<z_uadd, GR64, ALGFR>; 1097 1098// Addition producing and using a carry. 1099let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1100 // Addition of a register. 1101 def ALCR : BinaryRRE<"alcr", 0xB998, z_addcarry, GR32, GR32>; 1102 def ALCGR : BinaryRRE<"alcgr", 0xB988, z_addcarry, GR64, GR64>; 1103 1104 // Addition of memory. 1105 def ALC : BinaryRXY<"alc", 0xE398, z_addcarry, GR32, z_load, 4>; 1106 def ALCG : BinaryRXY<"alcg", 0xE388, z_addcarry, GR64, z_load, 8>; 1107} 1108 1109// Addition that does not modify the condition code. 1110def ALSIHN : BinaryRIL<"alsihn", 0xCCB, null_frag, GRH32, simm32>, 1111 Requires<[FeatureHighWord]>; 1112 1113 1114//===----------------------------------------------------------------------===// 1115// Subtraction 1116//===----------------------------------------------------------------------===// 1117 1118// Subtraction producing a signed overflow flag. 1119let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8, 1120 CCIfNoSignedWrap = 1 in { 1121 // Subtraction of a register. 1122 defm SR : BinaryRRAndK<"sr", 0x1B, 0xB9F9, z_ssub, GR32, GR32>; 1123 def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>; 1124 defm SGR : BinaryRREAndK<"sgr", 0xB909, 0xB9E9, z_ssub, GR64, GR64>; 1125 1126 // Subtraction from a high register. 1127 def SHHHR : BinaryRRFa<"shhhr", 0xB9C9, null_frag, GRH32, GRH32, GRH32>, 1128 Requires<[FeatureHighWord]>; 1129 def SHHLR : BinaryRRFa<"shhlr", 0xB9D9, null_frag, GRH32, GRH32, GR32>, 1130 Requires<[FeatureHighWord]>; 1131 1132 // Subtraction of memory. 1133 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, z_ssub, GR32, z_asextloadi16, 2>; 1134 defm S : BinaryRXPairAndPseudo<"s", 0x5B, 0xE35B, z_ssub, GR32, z_load, 4>; 1135 def SGH : BinaryRXY<"sgh", 0xE339, z_ssub, GR64, z_asextloadi16, 2>, 1136 Requires<[FeatureMiscellaneousExtensions2]>; 1137 def SGF : BinaryRXY<"sgf", 0xE319, z_ssub, GR64, z_asextloadi32, 4>; 1138 defm SG : BinaryRXYAndPseudo<"sg", 0xE309, z_ssub, GR64, z_load, 8>; 1139} 1140defm : SXB<z_ssub, GR64, SGFR>; 1141 1142// Subtracting an immediate is the same as adding the negated immediate. 1143let AddedComplexity = 1 in { 1144 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1145 (AHIMux GR32:$src1, imm32sx16n:$src2)>, 1146 Requires<[FeatureHighWord]>; 1147 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1148 (AFIMux GR32:$src1, simm32n:$src2)>, 1149 Requires<[FeatureHighWord]>; 1150 def : Pat<(z_ssub GR32:$src1, imm32sx16n:$src2), 1151 (AHI GR32:$src1, imm32sx16n:$src2)>; 1152 def : Pat<(z_ssub GR32:$src1, simm32n:$src2), 1153 (AFI GR32:$src1, simm32n:$src2)>; 1154 def : Pat<(z_ssub GR64:$src1, imm64sx16n:$src2), 1155 (AGHI GR64:$src1, imm64sx16n:$src2)>; 1156 def : Pat<(z_ssub GR64:$src1, imm64sx32n:$src2), 1157 (AGFI GR64:$src1, imm64sx32n:$src2)>; 1158} 1159 1160// And vice versa in one special case, where we need to load a 1161// constant into a register in any case, but the negated constant 1162// requires fewer instructions to load. 1163def : Pat<(z_saddo GR64:$src1, imm64lh16n:$src2), 1164 (SGR GR64:$src1, (LLILH imm64lh16n:$src2))>; 1165def : Pat<(z_saddo GR64:$src1, imm64lf32n:$src2), 1166 (SGR GR64:$src1, (LLILF imm64lf32n:$src2))>; 1167 1168// Subtraction producing a carry. 1169let Defs = [CC], CCValues = 0x7, IsLogical = 1 in { 1170 // Subtraction of a register. 1171 defm SLR : BinaryRRAndK<"slr", 0x1F, 0xB9FB, z_usub, GR32, GR32>; 1172 def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>; 1173 defm SLGR : BinaryRREAndK<"slgr", 0xB90B, 0xB9EB, z_usub, GR64, GR64>; 1174 1175 // Subtraction from a high register. 1176 def SLHHHR : BinaryRRFa<"slhhhr", 0xB9CB, null_frag, GRH32, GRH32, GRH32>, 1177 Requires<[FeatureHighWord]>; 1178 def SLHHLR : BinaryRRFa<"slhhlr", 0xB9DB, null_frag, GRH32, GRH32, GR32>, 1179 Requires<[FeatureHighWord]>; 1180 1181 // Subtraction of unsigned 32-bit immediates. 1182 def SLFI : BinaryRIL<"slfi", 0xC25, z_usub, GR32, uimm32>; 1183 def SLGFI : BinaryRIL<"slgfi", 0xC24, z_usub, GR64, imm64zx32>; 1184 1185 // Subtraction of memory. 1186 defm SL : BinaryRXPairAndPseudo<"sl", 0x5F, 0xE35F, z_usub, GR32, z_load, 4>; 1187 def SLGF : BinaryRXY<"slgf", 0xE31B, z_usub, GR64, z_azextloadi32, 4>; 1188 defm SLG : BinaryRXYAndPseudo<"slg", 0xE30B, z_usub, GR64, z_load, 8>; 1189} 1190defm : ZXB<z_usub, GR64, SLGFR>; 1191 1192// Subtracting an immediate is the same as adding the negated immediate. 1193let AddedComplexity = 1 in { 1194 def : Pat<(z_usub GR32:$src1, imm32sx16n:$src2), 1195 (ALHSIK GR32:$src1, imm32sx16n:$src2)>, 1196 Requires<[FeatureDistinctOps]>; 1197 def : Pat<(z_usub GR64:$src1, imm64sx16n:$src2), 1198 (ALGHSIK GR64:$src1, imm64sx16n:$src2)>, 1199 Requires<[FeatureDistinctOps]>; 1200} 1201 1202// And vice versa in one special case (but we prefer addition). 1203def : Pat<(add GR64:$src1, imm64zx32n:$src2), 1204 (SLGFI GR64:$src1, imm64zx32n:$src2)>; 1205 1206// Subtraction producing and using a carry. 1207let Defs = [CC], Uses = [CC], CCValues = 0xF, IsLogical = 1 in { 1208 // Subtraction of a register. 1209 def SLBR : BinaryRRE<"slbr", 0xB999, z_subcarry, GR32, GR32>; 1210 def SLBGR : BinaryRRE<"slbgr", 0xB989, z_subcarry, GR64, GR64>; 1211 1212 // Subtraction of memory. 1213 def SLB : BinaryRXY<"slb", 0xE399, z_subcarry, GR32, z_load, 4>; 1214 def SLBG : BinaryRXY<"slbg", 0xE389, z_subcarry, GR64, z_load, 8>; 1215} 1216 1217 1218//===----------------------------------------------------------------------===// 1219// AND 1220//===----------------------------------------------------------------------===// 1221 1222let Defs = [CC] in { 1223 // ANDs of a register. 1224 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1225 defm NR : BinaryRRAndK<"nr", 0x14, 0xB9F4, and, GR32, GR32>; 1226 defm NGR : BinaryRREAndK<"ngr", 0xB980, 0xB9E4, and, GR64, GR64>; 1227 } 1228 1229 let isConvertibleToThreeAddress = 1 in { 1230 // ANDs of a 16-bit immediate, leaving other bits unaffected. 1231 // The CC result only reflects the 16-bit field, not the full register. 1232 // 1233 // NIxMux expands to NI[LH]x, depending on the choice of register. 1234 def NILMux : BinaryRIPseudo<and, GRX32, imm32ll16c>, 1235 Requires<[FeatureHighWord]>; 1236 def NIHMux : BinaryRIPseudo<and, GRX32, imm32lh16c>, 1237 Requires<[FeatureHighWord]>; 1238 def NILL : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>; 1239 def NILH : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>; 1240 def NIHL : BinaryRI<"nihl", 0xA55, and, GRH32, imm32ll16c>; 1241 def NIHH : BinaryRI<"nihh", 0xA54, and, GRH32, imm32lh16c>; 1242 def NILL64 : BinaryAliasRI<and, GR64, imm64ll16c>; 1243 def NILH64 : BinaryAliasRI<and, GR64, imm64lh16c>; 1244 def NIHL64 : BinaryAliasRI<and, GR64, imm64hl16c>; 1245 def NIHH64 : BinaryAliasRI<and, GR64, imm64hh16c>; 1246 1247 // ANDs of a 32-bit immediate, leaving other bits unaffected. 1248 // The CC result only reflects the 32-bit field, which means we can 1249 // use it as a zero indicator for i32 operations but not otherwise. 1250 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1251 // Expands to NILF or NIHF, depending on the choice of register. 1252 def NIFMux : BinaryRIPseudo<and, GRX32, uimm32>, 1253 Requires<[FeatureHighWord]>; 1254 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>; 1255 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GRH32, uimm32>; 1256 } 1257 def NILF64 : BinaryAliasRIL<and, GR64, imm64lf32c>; 1258 def NIHF64 : BinaryAliasRIL<and, GR64, imm64hf32c>; 1259 } 1260 1261 // ANDs of memory. 1262 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1263 defm N : BinaryRXPairAndPseudo<"n", 0x54, 0xE354, and, GR32, z_load, 4>; 1264 defm NG : BinaryRXYAndPseudo<"ng", 0xE380, and, GR64, z_load, 8>; 1265 } 1266 1267 // AND to memory 1268 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, imm32zx8>; 1269 1270 // Block AND. 1271 let mayLoad = 1, mayStore = 1 in 1272 defm NC : MemorySS<"nc", 0xD4, z_nc>; 1273} 1274defm : RMWIByte<and, bdaddr12pair, NI>; 1275defm : RMWIByte<and, bdaddr20pair, NIY>; 1276 1277//===----------------------------------------------------------------------===// 1278// OR 1279//===----------------------------------------------------------------------===// 1280 1281let Defs = [CC] in { 1282 // ORs of a register. 1283 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1284 defm OR : BinaryRRAndK<"or", 0x16, 0xB9F6, or, GR32, GR32>; 1285 defm OGR : BinaryRREAndK<"ogr", 0xB981, 0xB9E6, or, GR64, GR64>; 1286 } 1287 1288 // ORs of a 16-bit immediate, leaving other bits unaffected. 1289 // The CC result only reflects the 16-bit field, not the full register. 1290 // 1291 // OIxMux expands to OI[LH]x, depending on the choice of register. 1292 def OILMux : BinaryRIPseudo<or, GRX32, imm32ll16>, 1293 Requires<[FeatureHighWord]>; 1294 def OIHMux : BinaryRIPseudo<or, GRX32, imm32lh16>, 1295 Requires<[FeatureHighWord]>; 1296 def OILL : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>; 1297 def OILH : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>; 1298 def OIHL : BinaryRI<"oihl", 0xA59, or, GRH32, imm32ll16>; 1299 def OIHH : BinaryRI<"oihh", 0xA58, or, GRH32, imm32lh16>; 1300 def OILL64 : BinaryAliasRI<or, GR64, imm64ll16>; 1301 def OILH64 : BinaryAliasRI<or, GR64, imm64lh16>; 1302 def OIHL64 : BinaryAliasRI<or, GR64, imm64hl16>; 1303 def OIHH64 : BinaryAliasRI<or, GR64, imm64hh16>; 1304 1305 // ORs of a 32-bit immediate, leaving other bits unaffected. 1306 // The CC result only reflects the 32-bit field, which means we can 1307 // use it as a zero indicator for i32 operations but not otherwise. 1308 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1309 // Expands to OILF or OIHF, depending on the choice of register. 1310 def OIFMux : BinaryRIPseudo<or, GRX32, uimm32>, 1311 Requires<[FeatureHighWord]>; 1312 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>; 1313 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GRH32, uimm32>; 1314 } 1315 def OILF64 : BinaryAliasRIL<or, GR64, imm64lf32>; 1316 def OIHF64 : BinaryAliasRIL<or, GR64, imm64hf32>; 1317 1318 // ORs of memory. 1319 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1320 defm O : BinaryRXPairAndPseudo<"o", 0x56, 0xE356, or, GR32, z_load, 4>; 1321 defm OG : BinaryRXYAndPseudo<"og", 0xE381, or, GR64, z_load, 8>; 1322 } 1323 1324 // OR to memory 1325 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, imm32zx8>; 1326 1327 // Block OR. 1328 let mayLoad = 1, mayStore = 1 in 1329 defm OC : MemorySS<"oc", 0xD6, z_oc>; 1330} 1331defm : RMWIByte<or, bdaddr12pair, OI>; 1332defm : RMWIByte<or, bdaddr20pair, OIY>; 1333 1334//===----------------------------------------------------------------------===// 1335// XOR 1336//===----------------------------------------------------------------------===// 1337 1338let Defs = [CC] in { 1339 // XORs of a register. 1340 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1341 defm XR : BinaryRRAndK<"xr", 0x17, 0xB9F7, xor, GR32, GR32>; 1342 defm XGR : BinaryRREAndK<"xgr", 0xB982, 0xB9E7, xor, GR64, GR64>; 1343 } 1344 1345 // XORs of a 32-bit immediate, leaving other bits unaffected. 1346 // The CC result only reflects the 32-bit field, which means we can 1347 // use it as a zero indicator for i32 operations but not otherwise. 1348 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1349 // Expands to XILF or XIHF, depending on the choice of register. 1350 def XIFMux : BinaryRIPseudo<xor, GRX32, uimm32>, 1351 Requires<[FeatureHighWord]>; 1352 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>; 1353 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GRH32, uimm32>; 1354 } 1355 def XILF64 : BinaryAliasRIL<xor, GR64, imm64lf32>; 1356 def XIHF64 : BinaryAliasRIL<xor, GR64, imm64hf32>; 1357 1358 // XORs of memory. 1359 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1360 defm X : BinaryRXPairAndPseudo<"x",0x57, 0xE357, xor, GR32, z_load, 4>; 1361 defm XG : BinaryRXYAndPseudo<"xg", 0xE382, xor, GR64, z_load, 8>; 1362 } 1363 1364 // XOR to memory 1365 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, imm32zx8>; 1366 1367 // Block XOR. 1368 let mayLoad = 1, mayStore = 1 in 1369 defm XC : MemorySS<"xc", 0xD7, z_xc>; 1370} 1371defm : RMWIByte<xor, bdaddr12pair, XI>; 1372defm : RMWIByte<xor, bdaddr20pair, XIY>; 1373 1374//===----------------------------------------------------------------------===// 1375// Combined logical operations 1376//===----------------------------------------------------------------------===// 1377 1378let Predicates = [FeatureMiscellaneousExtensions3], 1379 Defs = [CC] in { 1380 // AND with complement. 1381 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1382 def NCRK : BinaryRRFa<"ncrk", 0xB9F5, andc, GR32, GR32, GR32>; 1383 def NCGRK : BinaryRRFa<"ncgrk", 0xB9E5, andc, GR64, GR64, GR64>; 1384 } 1385 1386 // OR with complement. 1387 let CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1388 def OCRK : BinaryRRFa<"ocrk", 0xB975, orc, GR32, GR32, GR32>; 1389 def OCGRK : BinaryRRFa<"ocgrk", 0xB965, orc, GR64, GR64, GR64>; 1390 } 1391 1392 // NAND. 1393 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1394 def NNRK : BinaryRRFa<"nnrk", 0xB974, nand, GR32, GR32, GR32>; 1395 def NNGRK : BinaryRRFa<"nngrk", 0xB964, nand, GR64, GR64, GR64>; 1396 } 1397 1398 // NOR. 1399 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1400 def NORK : BinaryRRFa<"nork", 0xB976, nor, GR32, GR32, GR32>; 1401 def NOGRK : BinaryRRFa<"nogrk", 0xB966, nor, GR64, GR64, GR64>; 1402 let isAsmParserOnly = 1 in { 1403 def NOTR : UnaryRRFa<"notr", 0xB976, nor, GR32, GR32>; 1404 def NOTGR : UnaryRRFa<"notgr", 0xB966, nor, GR64, GR64>; 1405 } 1406 } 1407 1408 // NXOR. 1409 let isCommutable = 1, CCValues = 0xC, CompareZeroCCMask = 0x8 in { 1410 def NXRK : BinaryRRFa<"nxrk", 0xB977, nxor, GR32, GR32, GR32>; 1411 def NXGRK : BinaryRRFa<"nxgrk", 0xB967, nxor, GR64, GR64, GR64>; 1412 } 1413} 1414 1415//===----------------------------------------------------------------------===// 1416// Multiplication 1417//===----------------------------------------------------------------------===// 1418 1419// Multiplication of a register, setting the condition code. We prefer these 1420// over MS(G)R if available, even though we cannot use the condition code, 1421// since they are three-operand instructions. 1422let Predicates = [FeatureMiscellaneousExtensions2], 1423 Defs = [CC], isCommutable = 1 in { 1424 def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>; 1425 def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>; 1426} 1427 1428// Multiplication of a register. 1429let isCommutable = 1 in { 1430 def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; 1431 def MSGR : BinaryRRE<"msgr", 0xB90C, mul, GR64, GR64>; 1432} 1433def MSGFR : BinaryRRE<"msgfr", 0xB91C, null_frag, GR64, GR32>; 1434defm : SXB<mul, GR64, MSGFR>; 1435 1436// Multiplication of a signed 16-bit immediate. 1437def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>; 1438def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>; 1439 1440// Multiplication of a signed 32-bit immediate. 1441def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>; 1442def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; 1443 1444// Multiplication of memory. 1445defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, z_asextloadi16, 2>; 1446defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, z_load, 4>; 1447def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, z_asextloadi16, 2>, 1448 Requires<[FeatureMiscellaneousExtensions2]>; 1449def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, z_asextloadi32, 4>; 1450def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, z_load, 8>; 1451 1452// Multiplication of memory, setting the condition code. 1453let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { 1454 defm MSC : BinaryRXYAndPseudo<"msc", 0xE353, null_frag, GR32, z_load, 4>; 1455 defm MSGC : BinaryRXYAndPseudo<"msgc", 0xE383, null_frag, GR64, z_load, 8>; 1456} 1457 1458// Multiplication of a register, producing two results. 1459def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; 1460def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>, 1461 Requires<[FeatureMiscellaneousExtensions2]>; 1462def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; 1463def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>; 1464 1465def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2), 1466 (MGRK GR64:$src1, GR64:$src2)>; 1467def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2), 1468 (MLGR (AEXT128 GR64:$src1), GR64:$src2)>; 1469 1470// Multiplication of memory, producing two results. 1471def M : BinaryRX <"m", 0x5C, null_frag, GR128, z_load, 4>; 1472def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, z_load, 4>; 1473def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, z_load, 8>, 1474 Requires<[FeatureMiscellaneousExtensions2]>; 1475def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, z_load, 4>; 1476def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, z_load, 8>; 1477 1478def : Pat<(z_smul_lohi GR64:$src1, (i64 (z_load bdxaddr20only:$src2))), 1479 (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1480def : Pat<(z_umul_lohi GR64:$src1, (i64 (z_load bdxaddr20only:$src2))), 1481 (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1482 1483//===----------------------------------------------------------------------===// 1484// Division and remainder 1485//===----------------------------------------------------------------------===// 1486 1487let hasSideEffects = 1 in { // Do not speculatively execute. 1488 // Division and remainder, from registers. 1489 def DR : BinaryRR <"dr", 0x1D, null_frag, GR128, GR32>; 1490 def DSGFR : BinaryRRE<"dsgfr", 0xB91D, null_frag, GR128, GR32>; 1491 def DSGR : BinaryRRE<"dsgr", 0xB90D, null_frag, GR128, GR64>; 1492 def DLR : BinaryRRE<"dlr", 0xB997, null_frag, GR128, GR32>; 1493 def DLGR : BinaryRRE<"dlgr", 0xB987, null_frag, GR128, GR64>; 1494 1495 // Division and remainder, from memory. 1496 def D : BinaryRX <"d", 0x5D, null_frag, GR128, z_load, 4>; 1497 def DSGF : BinaryRXY<"dsgf", 0xE31D, null_frag, GR128, z_load, 4>; 1498 def DSG : BinaryRXY<"dsg", 0xE30D, null_frag, GR128, z_load, 8>; 1499 def DL : BinaryRXY<"dl", 0xE397, null_frag, GR128, z_load, 4>; 1500 def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, z_load, 8>; 1501} 1502def : Pat<(z_sdivrem GR64:$src1, GR32:$src2), 1503 (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>; 1504def : Pat<(z_sdivrem GR64:$src1, (i32 (z_load bdxaddr20only:$src2))), 1505 (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1506def : Pat<(z_sdivrem GR64:$src1, GR64:$src2), 1507 (DSGR (AEXT128 GR64:$src1), GR64:$src2)>; 1508def : Pat<(z_sdivrem GR64:$src1, (i64 (z_load bdxaddr20only:$src2))), 1509 (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1510 1511def : Pat<(z_udivrem GR32:$src1, GR32:$src2), 1512 (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1513 subreg_l32)), GR32:$src2)>; 1514def : Pat<(z_udivrem GR32:$src1, (i32 (z_load bdxaddr20only:$src2))), 1515 (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1, 1516 subreg_l32)), bdxaddr20only:$src2)>; 1517def : Pat<(z_udivrem GR64:$src1, GR64:$src2), 1518 (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>; 1519def : Pat<(z_udivrem GR64:$src1, (i64 (z_load bdxaddr20only:$src2))), 1520 (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>; 1521 1522//===----------------------------------------------------------------------===// 1523// Shifts 1524//===----------------------------------------------------------------------===// 1525 1526// Logical shift left. 1527defm SLL : BinaryRSAndK<"sll", 0x89, 0xEBDF, shiftop<shl>, GR32>; 1528def SLLG : BinaryRSY<"sllg", 0xEB0D, shiftop<shl>, GR64>; 1529def SLDL : BinaryRS<"sldl", 0x8D, null_frag, GR128>; 1530 1531// Arithmetic shift left. 1532let Defs = [CC] in { 1533 defm SLA : BinaryRSAndK<"sla", 0x8B, 0xEBDD, null_frag, GR32>; 1534 def SLAG : BinaryRSY<"slag", 0xEB0B, null_frag, GR64>; 1535 def SLDA : BinaryRS<"slda", 0x8F, null_frag, GR128>; 1536} 1537 1538// Logical shift right. 1539defm SRL : BinaryRSAndK<"srl", 0x88, 0xEBDE, shiftop<srl>, GR32>; 1540def SRLG : BinaryRSY<"srlg", 0xEB0C, shiftop<srl>, GR64>; 1541def SRDL : BinaryRS<"srdl", 0x8C, null_frag, GR128>; 1542 1543// Arithmetic shift right. 1544let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in { 1545 defm SRA : BinaryRSAndK<"sra", 0x8A, 0xEBDC, shiftop<sra>, GR32>; 1546 def SRAG : BinaryRSY<"srag", 0xEB0A, shiftop<sra>, GR64>; 1547 def SRDA : BinaryRS<"srda", 0x8E, null_frag, GR128>; 1548} 1549 1550// Rotate left. 1551def RLL : BinaryRSY<"rll", 0xEB1D, shiftop<rotl>, GR32>; 1552def RLLG : BinaryRSY<"rllg", 0xEB1C, shiftop<rotl>, GR64>; 1553 1554// Rotate second operand left and inserted selected bits into first operand. 1555// These can act like 32-bit operands provided that the constant start and 1556// end bits (operands 2 and 3) are in the range [32, 64). 1557let Defs = [CC] in { 1558 let isCodeGenOnly = 1 in 1559 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>; 1560 let CCValues = 0xE, CompareZeroCCMask = 0xE in { 1561 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>; 1562 def RISBGZ : RotateSelectRIEf<"risbgz", 0xEC55, GR64, GR64, 0, 128>; 1563 } 1564} 1565 1566// On zEC12 we have a variant of RISBG that does not set CC. 1567let Predicates = [FeatureMiscellaneousExtensions] in { 1568 def RISBGN : RotateSelectRIEf<"risbgn", 0xEC59, GR64, GR64>; 1569 def RISBGNZ : RotateSelectRIEf<"risbgnz", 0xEC59, GR64, GR64, 0, 128>; 1570} 1571 1572// Forms of RISBG that only affect one word of the destination register. 1573// They do not set CC. 1574let Predicates = [FeatureHighWord] in { 1575 def RISBMux : RotateSelectRIEfPseudo<GRX32, GRX32>; 1576 def RISBLL : RotateSelectAliasRIEf<GR32, GR32>; 1577 def RISBLH : RotateSelectAliasRIEf<GR32, GRH32>; 1578 def RISBHL : RotateSelectAliasRIEf<GRH32, GR32>; 1579 def RISBHH : RotateSelectAliasRIEf<GRH32, GRH32>; 1580 def RISBLG : RotateSelectRIEf<"risblg", 0xEC51, GR32, GR64>; 1581 def RISBHG : RotateSelectRIEf<"risbhg", 0xEC5D, GRH32, GR64>; 1582} 1583 1584// Rotate second operand left and perform a logical operation with selected 1585// bits of the first operand. The CC result only describes the selected bits, 1586// so isn't useful for a full comparison against zero. 1587let Defs = [CC] in { 1588 def RNSBG : RotateSelectRIEf<"rnsbg", 0xEC54, GR64, GR64>; 1589 def ROSBG : RotateSelectRIEf<"rosbg", 0xEC56, GR64, GR64>; 1590 def RXSBG : RotateSelectRIEf<"rxsbg", 0xEC57, GR64, GR64>; 1591} 1592 1593//===----------------------------------------------------------------------===// 1594// Comparison 1595//===----------------------------------------------------------------------===// 1596 1597// Signed comparisons. We put these before the unsigned comparisons because 1598// some of the signed forms have COMPARE AND BRANCH equivalents whereas none 1599// of the unsigned forms do. 1600let Defs = [CC], CCValues = 0xE in { 1601 // Comparison with a register. 1602 def CR : CompareRR <"cr", 0x19, z_scmp, GR32, GR32>; 1603 def CGFR : CompareRRE<"cgfr", 0xB930, null_frag, GR64, GR32>; 1604 def CGR : CompareRRE<"cgr", 0xB920, z_scmp, GR64, GR64>; 1605 1606 // Comparison with a high register. 1607 def CHHR : CompareRRE<"chhr", 0xB9CD, null_frag, GRH32, GRH32>, 1608 Requires<[FeatureHighWord]>; 1609 def CHLR : CompareRRE<"chlr", 0xB9DD, null_frag, GRH32, GR32>, 1610 Requires<[FeatureHighWord]>; 1611 1612 // Comparison with a signed 16-bit immediate. CHIMux expands to CHI or CIH, 1613 // depending on the choice of register. 1614 def CHIMux : CompareRIPseudo<z_scmp, GRX32, imm32sx16>, 1615 Requires<[FeatureHighWord]>; 1616 def CHI : CompareRI<"chi", 0xA7E, z_scmp, GR32, imm32sx16>; 1617 def CGHI : CompareRI<"cghi", 0xA7F, z_scmp, GR64, imm64sx16>; 1618 1619 // Comparison with a signed 32-bit immediate. CFIMux expands to CFI or CIH, 1620 // depending on the choice of register. 1621 def CFIMux : CompareRIPseudo<z_scmp, GRX32, simm32>, 1622 Requires<[FeatureHighWord]>; 1623 def CFI : CompareRIL<"cfi", 0xC2D, z_scmp, GR32, simm32>; 1624 def CIH : CompareRIL<"cih", 0xCCD, z_scmp, GRH32, simm32>, 1625 Requires<[FeatureHighWord]>; 1626 def CGFI : CompareRIL<"cgfi", 0xC2C, z_scmp, GR64, imm64sx32>; 1627 1628 // Comparison with memory. 1629 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_scmp, GR32, z_asextloadi16, 2>; 1630 def CMux : CompareRXYPseudo<z_scmp, GRX32, z_load, 4>, 1631 Requires<[FeatureHighWord]>; 1632 defm C : CompareRXPair<"c", 0x59, 0xE359, z_scmp, GR32, z_load, 4>; 1633 def CHF : CompareRXY<"chf", 0xE3CD, z_scmp, GRH32, z_load, 4>, 1634 Requires<[FeatureHighWord]>; 1635 def CGH : CompareRXY<"cgh", 0xE334, z_scmp, GR64, z_asextloadi16, 2>; 1636 def CGF : CompareRXY<"cgf", 0xE330, z_scmp, GR64, z_asextloadi32, 4>; 1637 def CG : CompareRXY<"cg", 0xE320, z_scmp, GR64, z_load, 8>; 1638 def CHRL : CompareRILPC<"chrl", 0xC65, z_scmp, GR32, aligned_z_asextloadi16>; 1639 def CRL : CompareRILPC<"crl", 0xC6D, z_scmp, GR32, aligned_z_load>; 1640 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_scmp, GR64, aligned_z_asextloadi16>; 1641 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_scmp, GR64, aligned_z_asextloadi32>; 1642 def CGRL : CompareRILPC<"cgrl", 0xC68, z_scmp, GR64, aligned_z_load>; 1643 1644 // Comparison between memory and a signed 16-bit immediate. 1645 def CHHSI : CompareSIL<"chhsi", 0xE554, z_scmp, z_asextloadi16, imm32sx16>; 1646 def CHSI : CompareSIL<"chsi", 0xE55C, z_scmp, z_load, imm32sx16>; 1647 def CGHSI : CompareSIL<"cghsi", 0xE558, z_scmp, z_load, imm64sx16>; 1648} 1649defm : SXB<z_scmp, GR64, CGFR>; 1650 1651// Unsigned comparisons. 1652let Defs = [CC], CCValues = 0xE, IsLogical = 1 in { 1653 // Comparison with a register. 1654 def CLR : CompareRR <"clr", 0x15, z_ucmp, GR32, GR32>; 1655 def CLGFR : CompareRRE<"clgfr", 0xB931, null_frag, GR64, GR32>; 1656 def CLGR : CompareRRE<"clgr", 0xB921, z_ucmp, GR64, GR64>; 1657 1658 // Comparison with a high register. 1659 def CLHHR : CompareRRE<"clhhr", 0xB9CF, null_frag, GRH32, GRH32>, 1660 Requires<[FeatureHighWord]>; 1661 def CLHLR : CompareRRE<"clhlr", 0xB9DF, null_frag, GRH32, GR32>, 1662 Requires<[FeatureHighWord]>; 1663 1664 // Comparison with an unsigned 32-bit immediate. CLFIMux expands to CLFI 1665 // or CLIH, depending on the choice of register. 1666 def CLFIMux : CompareRIPseudo<z_ucmp, GRX32, uimm32>, 1667 Requires<[FeatureHighWord]>; 1668 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>; 1669 def CLIH : CompareRIL<"clih", 0xCCF, z_ucmp, GRH32, uimm32>, 1670 Requires<[FeatureHighWord]>; 1671 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>; 1672 1673 // Comparison with memory. 1674 def CLMux : CompareRXYPseudo<z_ucmp, GRX32, z_load, 4>, 1675 Requires<[FeatureHighWord]>; 1676 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, z_load, 4>; 1677 def CLHF : CompareRXY<"clhf", 0xE3CF, z_ucmp, GRH32, z_load, 4>, 1678 Requires<[FeatureHighWord]>; 1679 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, z_azextloadi32, 4>; 1680 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, z_load, 8>; 1681 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32, 1682 aligned_z_azextloadi16>; 1683 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32, 1684 aligned_z_load>; 1685 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64, 1686 aligned_z_azextloadi16>; 1687 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64, 1688 aligned_z_azextloadi32>; 1689 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64, 1690 aligned_z_load>; 1691 1692 // Comparison between memory and an unsigned 8-bit immediate. 1693 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, z_azextloadi8, imm32zx8>; 1694 1695 // Comparison between memory and an unsigned 16-bit immediate. 1696 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, z_azextloadi16, imm32zx16>; 1697 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, z_load, imm32zx16>; 1698 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, z_load, imm64zx16>; 1699} 1700defm : ZXB<z_ucmp, GR64, CLGFR>; 1701 1702// Memory-to-memory comparison. 1703let mayLoad = 1, Defs = [CC] in { 1704 defm CLC : CompareMemorySS<"clc", 0xD5, z_clc>; 1705 def CLCL : SideEffectBinaryMemMemRR<"clcl", 0x0F, GR128, GR128>; 1706 def CLCLE : SideEffectTernaryMemMemRS<"clcle", 0xA9, GR128, GR128>; 1707 def CLCLU : SideEffectTernaryMemMemRSY<"clclu", 0xEB8F, GR128, GR128>; 1708} 1709 1710// String comparison. 1711let mayLoad = 1, Defs = [CC] in 1712 defm CLST : StringRRE<"clst", 0xB25D, z_strcmp>; 1713 1714// Test under mask. 1715let Defs = [CC] in { 1716 // TMxMux expands to TM[LH]x, depending on the choice of register. 1717 def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, 1718 Requires<[FeatureHighWord]>; 1719 def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, 1720 Requires<[FeatureHighWord]>; 1721 def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; 1722 def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; 1723 def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; 1724 def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; 1725 1726 def TMLL64 : CompareAliasRI<z_tm_reg, GR64, imm64ll16>; 1727 def TMLH64 : CompareAliasRI<z_tm_reg, GR64, imm64lh16>; 1728 def TMHL64 : CompareAliasRI<z_tm_reg, GR64, imm64hl16>; 1729 def TMHH64 : CompareAliasRI<z_tm_reg, GR64, imm64hh16>; 1730 1731 defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, z_anyextloadi8, imm32zx8>; 1732} 1733 1734def TML : InstAlias<"tml\t$R, $I", (TMLL GR32:$R, imm32ll16:$I), 0>; 1735def TMH : InstAlias<"tmh\t$R, $I", (TMLH GR32:$R, imm32lh16:$I), 0>; 1736 1737// Compare logical characters under mask -- not (yet) used for codegen. 1738let Defs = [CC] in { 1739 defm CLM : CompareRSPair<"clm", 0xBD, 0xEB21, GR32, 0>; 1740 def CLMH : CompareRSY<"clmh", 0xEB20, GRH32, 0>; 1741} 1742 1743//===----------------------------------------------------------------------===// 1744// Prefetch and execution hint 1745//===----------------------------------------------------------------------===// 1746 1747let mayLoad = 1, mayStore = 1 in { 1748 def PFD : PrefetchRXY<"pfd", 0xE336, z_prefetch>; 1749 def PFDRL : PrefetchRILPC<"pfdrl", 0xC62, z_prefetch>; 1750} 1751 1752let Predicates = [FeatureExecutionHint], hasSideEffects = 1 in { 1753 // Branch Prediction Preload 1754 def BPP : BranchPreloadSMI<"bpp", 0xC7>; 1755 def BPRP : BranchPreloadMII<"bprp", 0xC5>; 1756 1757 // Next Instruction Access Intent 1758 def NIAI : SideEffectBinaryIE<"niai", 0xB2FA, imm32zx4, imm32zx4>; 1759} 1760 1761//===----------------------------------------------------------------------===// 1762// Atomic operations 1763//===----------------------------------------------------------------------===// 1764 1765// A serialization instruction that acts as a barrier for all memory 1766// accesses, which expands to "bcr 14, 0". 1767let hasSideEffects = 1 in 1768def Serialize : Alias<2, (outs), (ins), []>; 1769 1770let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1771 def LAA : LoadAndOpRSY<"laa", 0xEBF8, atomic_load_add_i32, GR32>; 1772 def LAAG : LoadAndOpRSY<"laag", 0xEBE8, atomic_load_add_i64, GR64>; 1773 def LAAL : LoadAndOpRSY<"laal", 0xEBFA, null_frag, GR32>; 1774 def LAALG : LoadAndOpRSY<"laalg", 0xEBEA, null_frag, GR64>; 1775 def LAN : LoadAndOpRSY<"lan", 0xEBF4, atomic_load_and_i32, GR32>; 1776 def LANG : LoadAndOpRSY<"lang", 0xEBE4, atomic_load_and_i64, GR64>; 1777 def LAO : LoadAndOpRSY<"lao", 0xEBF6, atomic_load_or_i32, GR32>; 1778 def LAOG : LoadAndOpRSY<"laog", 0xEBE6, atomic_load_or_i64, GR64>; 1779 def LAX : LoadAndOpRSY<"lax", 0xEBF7, atomic_load_xor_i32, GR32>; 1780 def LAXG : LoadAndOpRSY<"laxg", 0xEBE7, atomic_load_xor_i64, GR64>; 1781} 1782 1783def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>; 1784 1785def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>; 1786def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>; 1787 1788def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>; 1789 1790def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>; 1791def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>; 1792 1793def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>; 1794def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>; 1795 1796def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>; 1797def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>; 1798 1799def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>; 1800def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand, 1801 imm32lh16c>; 1802 1803def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>; 1804def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>; 1805def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>; 1806def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>; 1807 1808def ATOMIC_CMP_SWAPW 1809 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1810 ADDR32:$bitshift, ADDR32:$negbitshift, 1811 uimm32:$bitsize), 1812 [(set GR32:$dst, 1813 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap, 1814 ADDR32:$bitshift, ADDR32:$negbitshift, 1815 uimm32:$bitsize))]> { 1816 let Defs = [CC]; 1817 let mayLoad = 1; 1818 let mayStore = 1; 1819 let usesCustomInserter = 1; 1820 let hasNoSchedulingInfo = 1; 1821} 1822 1823// Test and set. 1824let mayLoad = 1, Defs = [CC] in 1825 def TS : StoreInherentS<"ts", 0x9300, null_frag, 1>; 1826 1827// Compare and swap. 1828let Defs = [CC] in { 1829 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, z_atomic_cmp_swap, GR32>; 1830 def CSG : CmpSwapRSY<"csg", 0xEB30, z_atomic_cmp_swap, GR64>; 1831} 1832 1833// Compare double and swap. 1834let Defs = [CC] in { 1835 defm CDS : CmpSwapRSPair<"cds", 0xBB, 0xEB31, null_frag, GR128>; 1836 def CDSG : CmpSwapRSY<"cdsg", 0xEB3E, z_atomic_cmp_swap_128, GR128>; 1837} 1838 1839// Compare and swap and store. 1840let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad = 1 in 1841 def CSST : SideEffectTernarySSF<"csst", 0xC82, GR64>; 1842 1843// Perform locked operation. 1844let Uses = [R0L, R1D], Defs = [CC], mayStore = 1, mayLoad =1 in 1845 def PLO : SideEffectQuaternarySSe<"plo", 0xEE, GR64>; 1846 1847// Load/store pair from/to quadword. 1848def LPQ : UnaryRXY<"lpq", 0xE38F, z_atomic_load_128, GR128, 16>; 1849def STPQ : StoreRXY<"stpq", 0xE38E, z_atomic_store_128, GR128, 16>; 1850 1851// Load pair disjoint. 1852let Predicates = [FeatureInterlockedAccess1], Defs = [CC] in { 1853 def LPD : BinarySSF<"lpd", 0xC84, GR128>; 1854 def LPDG : BinarySSF<"lpdg", 0xC85, GR128>; 1855} 1856 1857// Compare and load. 1858let Predicates = [FeatureConcurrentFunctions], Defs = [CC] in { 1859 def CAL : BinarySSF<"cal", 0xC86, GR32>; 1860 def CALGF : BinarySSF<"calgf", 0xC8F, GR64>; 1861 def CALG : BinarySSF<"calg", 0xC87, GR64>; 1862} 1863 1864// Perform function with concurrent results. 1865let Predicates = [FeatureConcurrentFunctions], Uses = [R0D], Defs = [CC], 1866 mayLoad = 1, mayStore = 1, hasSideEffects = 1 in { 1867 def PFCR : BinaryRSY<"pfcr", 0xEB16, null_frag, GR64>; 1868} 1869 1870//===----------------------------------------------------------------------===// 1871// Translate and convert 1872//===----------------------------------------------------------------------===// 1873 1874let mayLoad = 1, mayStore = 1 in 1875 def TR : SideEffectBinarySSa<"tr", 0xDC>; 1876 1877let mayLoad = 1, Defs = [CC, R0L, R1D] in { 1878 def TRT : SideEffectBinarySSa<"trt", 0xDD>; 1879 def TRTR : SideEffectBinarySSa<"trtr", 0xD0>; 1880} 1881 1882let mayLoad = 1, mayStore = 1, Uses = [R0L] in 1883 def TRE : SideEffectBinaryMemMemRRE<"tre", 0xB2A5, GR128, GR64>; 1884 1885let mayLoad = 1, Uses = [R1D], Defs = [CC] in { 1886 defm TRTE : BinaryMemRRFcOpt<"trte", 0xB9BF, GR128, GR64>; 1887 defm TRTRE : BinaryMemRRFcOpt<"trtre", 0xB9BD, GR128, GR64>; 1888} 1889 1890let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1891 defm TROO : SideEffectTernaryMemMemRRFcOpt<"troo", 0xB993, GR128, GR64>; 1892 defm TROT : SideEffectTernaryMemMemRRFcOpt<"trot", 0xB992, GR128, GR64>; 1893 defm TRTO : SideEffectTernaryMemMemRRFcOpt<"trto", 0xB991, GR128, GR64>; 1894 defm TRTT : SideEffectTernaryMemMemRRFcOpt<"trtt", 0xB990, GR128, GR64>; 1895} 1896 1897let mayLoad = 1, mayStore = 1, Defs = [CC] in { 1898 defm CU12 : SideEffectTernaryMemMemRRFcOpt<"cu12", 0xB2A7, GR128, GR128>; 1899 defm CU14 : SideEffectTernaryMemMemRRFcOpt<"cu14", 0xB9B0, GR128, GR128>; 1900 defm CU21 : SideEffectTernaryMemMemRRFcOpt<"cu21", 0xB2A6, GR128, GR128>; 1901 defm CU24 : SideEffectTernaryMemMemRRFcOpt<"cu24", 0xB9B1, GR128, GR128>; 1902 def CU41 : SideEffectBinaryMemMemRRE<"cu41", 0xB9B2, GR128, GR128>; 1903 def CU42 : SideEffectBinaryMemMemRRE<"cu42", 0xB9B3, GR128, GR128>; 1904 1905 let isAsmParserOnly = 1 in { 1906 defm CUUTF : SideEffectTernaryMemMemRRFcOpt<"cuutf", 0xB2A6, GR128, GR128>; 1907 defm CUTFU : SideEffectTernaryMemMemRRFcOpt<"cutfu", 0xB2A7, GR128, GR128>; 1908 } 1909} 1910 1911//-------------------------------------------------------------------------- 1912// Setjmp/Longjmp. 1913//-------------------------------------------------------------------------- 1914let isBarrier = 1, hasNoSchedulingInfo = 1 in { 1915 let hasSideEffects = 1, usesCustomInserter = 1 in { 1916 def EH_SjLj_SetJmp : Pseudo<(outs GR32:$dst), (ins ADDR64:$R2), 1917 [(set GR32:$dst, (z_eh_sjlj_setjmp ADDR64:$R2))]>; 1918 let isTerminator = 1 in { 1919 def EH_SjLj_LongJmp : Pseudo<(outs), (ins ADDR64:$R2), 1920 [(z_eh_sjlj_longjmp ADDR64:$R2)]>; 1921 } 1922 } 1923 let isTerminator = 1, isCodeGenOnly = 1, Size = 0 in { 1924 def EH_SjLj_Setup : Pseudo<(outs), (ins brtarget32:$dst), []>; 1925 } 1926} 1927 1928//===----------------------------------------------------------------------===// 1929// Message-security assist 1930//===----------------------------------------------------------------------===// 1931 1932let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { 1933 def KM : SideEffectBinaryMemMemRRE<"km", 0xB92E, GR128, GR128>; 1934 def KMC : SideEffectBinaryMemMemRRE<"kmc", 0xB92F, GR128, GR128>; 1935 1936 def KIMD : SideEffectBinaryMemRRE<"kimd", 0xB93E, GR64, GR128>; 1937 def KLMD : SideEffectBinaryMemRRE<"klmd", 0xB93F, GR64, GR128>; 1938 def KMAC : SideEffectBinaryMemRRE<"kmac", 0xB91E, GR64, GR128>; 1939 1940 let Predicates = [FeatureMessageSecurityAssist4] in { 1941 def KMF : SideEffectBinaryMemMemRRE<"kmf", 0xB92A, GR128, GR128>; 1942 def KMO : SideEffectBinaryMemMemRRE<"kmo", 0xB92B, GR128, GR128>; 1943 def KMCTR : SideEffectTernaryMemMemMemRRFb<"kmctr", 0xB92D, 1944 GR128, GR128, GR128>; 1945 def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; 1946 } 1947 1948 let Predicates = [FeatureMessageSecurityAssist5] in 1949 def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; 1950 let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in 1951 def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>; 1952 1953 let Predicates = [FeatureMessageSecurityAssist8] in 1954 def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929, 1955 GR128, GR128, GR128>; 1956 1957 let Predicates = [FeatureMessageSecurityAssist9] in 1958 def KDSA : SideEffectBinaryMemRRE<"kdsa", 0xB93A, GR64, GR128>; 1959 1960 let Predicates = [FeatureMessageSecurityAssist12] in { 1961 def KIMDOpt : SideEffectTernaryMemMemRRFc<"kimd", 0xB93E, GR64, GR128, imm32zx4>; 1962 def KLMDOpt : SideEffectTernaryMemMemRRFc<"klmd", 0xB93F, GR64, GR128, imm32zx4>; 1963 } 1964} 1965 1966//===----------------------------------------------------------------------===// 1967// Guarded storage 1968//===----------------------------------------------------------------------===// 1969 1970// These instructions use and/or modify the guarded storage control 1971// registers, which we do not otherwise model, so they should have 1972// hasSideEffects. 1973let Predicates = [FeatureGuardedStorage], hasSideEffects = 1 in { 1974 def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>; 1975 def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>; 1976 1977 let mayLoad = 1 in 1978 def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>; 1979 let mayStore = 1 in 1980 def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>; 1981} 1982 1983//===----------------------------------------------------------------------===// 1984// Decimal arithmetic 1985//===----------------------------------------------------------------------===// 1986 1987defm CVB : BinaryRXPair<"cvb",0x4F, 0xE306, null_frag, GR32, z_load, 4>; 1988def CVBG : BinaryRXY<"cvbg", 0xE30E, null_frag, GR64, z_load, 8>; 1989 1990defm CVD : StoreRXPair<"cvd", 0x4E, 0xE326, null_frag, GR32, 4>; 1991def CVDG : StoreRXY<"cvdg", 0xE32E, null_frag, GR64, 8>; 1992 1993let mayLoad = 1, mayStore = 1 in { 1994 def MVN : SideEffectBinarySSa<"mvn", 0xD1>; 1995 def MVZ : SideEffectBinarySSa<"mvz", 0xD3>; 1996 def MVO : SideEffectBinarySSb<"mvo", 0xF1>; 1997 1998 def PACK : SideEffectBinarySSb<"pack", 0xF2>; 1999 def PKA : SideEffectBinarySSf<"pka", 0xE9>; 2000 def PKU : SideEffectBinarySSf<"pku", 0xE1>; 2001 def UNPK : SideEffectBinarySSb<"unpk", 0xF3>; 2002 let Defs = [CC] in { 2003 def UNPKA : SideEffectBinarySSa<"unpka", 0xEA>; 2004 def UNPKU : SideEffectBinarySSa<"unpku", 0xE2>; 2005 } 2006} 2007 2008let mayLoad = 1, mayStore = 1 in { 2009 let Defs = [CC] in { 2010 def AP : SideEffectBinarySSb<"ap", 0xFA>; 2011 def SP : SideEffectBinarySSb<"sp", 0xFB>; 2012 def ZAP : SideEffectBinarySSb<"zap", 0xF8>; 2013 def SRP : SideEffectTernarySSc<"srp", 0xF0>; 2014 } 2015 def MP : SideEffectBinarySSb<"mp", 0xFC>; 2016 def DP : SideEffectBinarySSb<"dp", 0xFD>; 2017 let Defs = [CC] in { 2018 def ED : SideEffectBinarySSa<"ed", 0xDE>; 2019 def EDMK : SideEffectBinarySSa<"edmk", 0xDF>; 2020 } 2021} 2022 2023let Defs = [CC] in { 2024 def CP : CompareSSb<"cp", 0xF9>; 2025 def TP : TestRSL<"tp", 0xEBC0>; 2026} 2027 2028//===----------------------------------------------------------------------===// 2029// Access registers 2030//===----------------------------------------------------------------------===// 2031 2032// Read a 32-bit access register into a GR32. As with all GR32 operations, 2033// the upper 32 bits of the enclosing GR64 remain unchanged, which is useful 2034// when a 64-bit address is stored in a pair of access registers. 2035def EAR : UnaryRRE<"ear", 0xB24F, null_frag, GR32, AR32>; 2036 2037// Set access register. 2038def SAR : UnaryRRE<"sar", 0xB24E, null_frag, AR32, GR32>; 2039 2040// Copy access register. 2041def CPYA : UnaryRRE<"cpya", 0xB24D, null_frag, AR32, AR32>; 2042 2043// Load address extended. 2044defm LAE : LoadAddressRXPair<"lae", 0x51, 0xE375, null_frag>; 2045 2046// Load access multiple. 2047defm LAM : LoadMultipleRSPair<"lam", 0x9A, 0xEB9A, AR32>; 2048 2049// Store access multiple. 2050defm STAM : StoreMultipleRSPair<"stam", 0x9B, 0xEB9B, AR32>; 2051 2052//===----------------------------------------------------------------------===// 2053// Program mask and addressing mode 2054//===----------------------------------------------------------------------===// 2055 2056// Extract CC and program mask into a register. CC ends up in bits 29 and 28. 2057let Uses = [CC] in 2058 def IPM : InherentRRE<"ipm", 0xB222, GR32, z_ipm>; 2059 2060// Set CC and program mask from a register. 2061let hasSideEffects = 1, Defs = [CC] in 2062 def SPM : SideEffectUnaryRR<"spm", 0x04, GR32>; 2063 2064// Branch and link - like BAS, but also extracts CC and program mask. 2065let isCall = 1, Uses = [CC], Defs = [CC] in { 2066 def BAL : CallRX<"bal", 0x45>; 2067 def BALR : CallRR<"balr", 0x05>; 2068} 2069 2070// Test addressing mode. 2071let Defs = [CC] in 2072 def TAM : SideEffectInherentE<"tam", 0x010B>; 2073 2074// Set addressing mode. 2075let hasSideEffects = 1 in { 2076 def SAM24 : SideEffectInherentE<"sam24", 0x010C>; 2077 def SAM31 : SideEffectInherentE<"sam31", 0x010D>; 2078 def SAM64 : SideEffectInherentE<"sam64", 0x010E>; 2079} 2080 2081// Branch and set mode. Not really a call, but also sets an output register. 2082let isBranch = 1, isTerminator = 1, isBarrier = 1 in 2083 def BSM : CallRR<"bsm", 0x0B>; 2084 2085// Branch and save and set mode. 2086let isCall = 1, Defs = [CC] in 2087 def BASSM : CallRR<"bassm", 0x0C>; 2088 2089//===----------------------------------------------------------------------===// 2090// Transactional execution 2091//===----------------------------------------------------------------------===// 2092 2093let hasSideEffects = 1, Predicates = [FeatureTransactionalExecution] in { 2094 // Transaction Begin 2095 let mayStore = 1, usesCustomInserter = 1, Defs = [CC] in { 2096 def TBEGIN : TestBinarySIL<"tbegin", 0xE560, z_tbegin, imm32zx16>; 2097 let hasNoSchedulingInfo = 1 in 2098 def TBEGIN_nofloat : TestBinarySILPseudo<z_tbegin_nofloat, imm32zx16>; 2099 def TBEGINC : SideEffectBinarySIL<"tbeginc", 0xE561, 2100 int_s390_tbeginc, imm32zx16>; 2101 } 2102 2103 // Transaction End 2104 let Defs = [CC] in 2105 def TEND : TestInherentS<"tend", 0xB2F8, z_tend>; 2106 2107 // Transaction Abort 2108 let isTerminator = 1, isBarrier = 1, mayStore = 1, 2109 hasSideEffects = 1 in 2110 def TABORT : SideEffectAddressS<"tabort", 0xB2FC, int_s390_tabort>; 2111 2112 // Nontransactional Store 2113 def NTSTG : StoreRXY<"ntstg", 0xE325, int_s390_ntstg, GR64, 8>; 2114 2115 // Extract Transaction Nesting Depth 2116 def ETND : InherentRRE<"etnd", 0xB2EC, GR32, int_s390_etnd>; 2117} 2118 2119//===----------------------------------------------------------------------===// 2120// Processor assist 2121//===----------------------------------------------------------------------===// 2122 2123let Predicates = [FeatureProcessorAssist] in { 2124 let hasSideEffects = 1 in 2125 def PPA : SideEffectTernaryRRFc<"ppa", 0xB2E8, GR64, GR64, imm32zx4>; 2126 def : Pat<(int_s390_ppa_txassist GR32:$src), 2127 (PPA (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32), 2128 zero_reg, 1)>; 2129} 2130 2131//===----------------------------------------------------------------------===// 2132// Miscellaneous Instructions. 2133//===----------------------------------------------------------------------===// 2134 2135// Count leading/trailing zeros. 2136let Predicates = [FeatureMiscellaneousExtensions4] in { 2137 def CLZG : UnaryRRE<"clzg", 0xB968, ctlz, GR64, GR64>; 2138 def CTZG : UnaryRRE<"ctzg", 0xB969, cttz, GR64, GR64>; 2139} 2140 2141// Find leftmost one, AKA count leading zeros. The instruction actually 2142// returns a pair of GR64s, the first giving the number of leading zeros 2143// and the second giving a copy of the source with the leftmost one bit 2144// cleared. We only use the first result here. 2145let Defs = [CC] in 2146 def FLOGR : UnaryRRE<"flogr", 0xB983, null_frag, GR128, GR64>; 2147def : Pat<(i64 (ctlz GR64:$src)), 2148 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_h64)>; 2149 2150// Population count. Counts bits set per byte or doubleword. 2151let Predicates = [FeatureMiscellaneousExtensions3] in { 2152 let Defs = [CC] in 2153 def POPCNTOpt : BinaryRRFc<"popcnt", 0xB9E1, GR64, GR64>; 2154 def : Pat<(ctpop GR64:$src), (POPCNTOpt GR64:$src, 8)>; 2155} 2156let Predicates = [FeaturePopulationCount], Defs = [CC] in 2157 def POPCNT : UnaryRRE<"popcnt", 0xB9E1, z_popcnt, GR64, GR64>; 2158 2159// Bit deposit and bit extract. 2160let Predicates = [FeatureMiscellaneousExtensions4] in { 2161 def BDEPG : BinaryRRFa<"bdepg", 0xB96D, int_s390_bdepg, GR64, GR64, GR64>; 2162 def BEXTG : BinaryRRFa<"bextg", 0xB96C, int_s390_bextg, GR64, GR64, GR64>; 2163} 2164 2165// Search a block of memory for a character. 2166let mayLoad = 1, Defs = [CC] in 2167 defm SRST : StringRRE<"srst", 0xB25E, z_search_string>; 2168let mayLoad = 1, Defs = [CC], Uses = [R0L] in 2169 def SRSTU : SideEffectBinaryMemMemRRE<"srstu", 0xB9BE, GR64, GR64>; 2170 2171// Compare until substring equal. 2172let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in 2173 def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>; 2174 2175// Compare and form codeword. 2176let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in 2177 def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>; 2178 2179// Update tree. 2180let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D], 2181 Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in 2182 def UPT : SideEffectInherentE<"upt", 0x0102>; 2183 2184// Checksum. 2185let mayLoad = 1, Defs = [CC] in 2186 def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>; 2187 2188// Compression call. 2189let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in 2190 def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>; 2191 2192// Sort lists. 2193let Predicates = [FeatureEnhancedSort], 2194 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2195 def SORTL : SideEffectBinaryMemMemRRE<"sortl", 0xB938, GR128, GR128>; 2196 2197// Deflate conversion call. 2198let Predicates = [FeatureDeflateConversion], 2199 mayLoad = 1, mayStore = 1, Defs = [CC], Uses = [R0L, R1D] in 2200 def DFLTCC : SideEffectTernaryMemMemRRFa<"dfltcc", 0xB939, 2201 GR128, GR128, GR64>; 2202 2203// NNPA. 2204let Predicates = [FeatureNNPAssist], 2205 mayLoad = 1, mayStore = 1, Defs = [R0D, CC], Uses = [R0D, R1D] in 2206 def NNPA : SideEffectInherentRRE<"nnpa", 0xB93B>; 2207 2208// Execute. 2209let hasSideEffects = 1 in { 2210 def EX : SideEffectBinaryRX<"ex", 0x44, ADDR64>; 2211 def EXRL : SideEffectBinaryRILPC<"exrl", 0xC60, ADDR64>; 2212 let hasNoSchedulingInfo = 1 in 2213 def EXRL_Pseudo : Alias<6, (outs), (ins i64imm:$TargetOpc, ADDR64:$lenMinus1, 2214 bdaddr12only:$bdl1, bdaddr12only:$bd2), 2215 []>; 2216} 2217 2218//===----------------------------------------------------------------------===// 2219// .insn directive instructions 2220//===----------------------------------------------------------------------===// 2221 2222let isCodeGenOnly = 1, hasSideEffects = 1 in { 2223 def InsnE : DirectiveInsnE<(outs), (ins imm64zx16:$enc), ".insn e,$enc", []>; 2224 def InsnRI : DirectiveInsnRI<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2225 imm32sx16:$I2), 2226 ".insn ri,$enc,$R1,$I2", []>; 2227 def InsnRIE : DirectiveInsnRIE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2228 AnyReg:$R3, brtarget16:$I2), 2229 ".insn rie,$enc,$R1,$R3,$I2", []>; 2230 def InsnRIL : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2231 brtarget32:$I2), 2232 ".insn ril,$enc,$R1,$I2", []>; 2233 def InsnRILU : DirectiveInsnRIL<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2234 uimm32:$I2), 2235 ".insn rilu,$enc,$R1,$I2", []>; 2236 def InsnRIS : DirectiveInsnRIS<(outs), 2237 (ins imm64zx48:$enc, AnyReg:$R1, 2238 imm32sx8:$I2, imm32zx4:$M3, 2239 (bdaddr12only $B4, $D4):$BD4), 2240 ".insn ris,$enc,$R1,$I2,$M3,$BD4", []>; 2241 def InsnRR : DirectiveInsnRR<(outs), 2242 (ins imm64zx16:$enc, AnyReg:$R1, AnyReg:$R2), 2243 ".insn rr,$enc,$R1,$R2", []>; 2244 def InsnRRE : DirectiveInsnRRE<(outs), (ins imm64zx32:$enc, 2245 AnyReg:$R1, AnyReg:$R2), 2246 ".insn rre,$enc,$R1,$R2", []>; 2247 def InsnRRF : DirectiveInsnRRF<(outs), 2248 (ins imm64zx32:$enc, AnyReg:$R1, AnyReg:$R2, 2249 AnyReg:$R3, imm32zx4:$M4), 2250 ".insn rrf,$enc,$R1,$R2,$R3,$M4", []>; 2251 def InsnRRS : DirectiveInsnRRS<(outs), 2252 (ins imm64zx48:$enc, AnyReg:$R1, 2253 AnyReg:$R2, imm32zx4:$M3, 2254 (bdaddr12only $B4, $D4):$BD4), 2255 ".insn rrs,$enc,$R1,$R2,$M3,$BD4", []>; 2256 def InsnRS : DirectiveInsnRS<(outs), 2257 (ins imm64zx32:$enc, AnyReg:$R1, 2258 AnyReg:$R3, (bdaddr12only $B2, $D2):$BD2), 2259 ".insn rs,$enc,$R1,$R3,$BD2", []>; 2260 def InsnRSE : DirectiveInsnRSE<(outs), 2261 (ins imm64zx48:$enc, AnyReg:$R1, 2262 AnyReg:$R3, (bdaddr12only $B2, $D2):$BD2), 2263 ".insn rse,$enc,$R1,$R3,$BD2", []>; 2264 def InsnRSI : DirectiveInsnRSI<(outs), 2265 (ins imm64zx48:$enc, AnyReg:$R1, 2266 AnyReg:$R3, brtarget16:$RI2), 2267 ".insn rsi,$enc,$R1,$R3,$RI2", []>; 2268 def InsnRSY : DirectiveInsnRSY<(outs), 2269 (ins imm64zx48:$enc, AnyReg:$R1, 2270 AnyReg:$R3, (bdaddr20only $B2, $D2):$BD2), 2271 ".insn rsy,$enc,$R1,$R3,$BD2", []>; 2272 def InsnRX : DirectiveInsnRX<(outs), (ins imm64zx32:$enc, AnyReg:$R1, 2273 (bdxaddr12only $B2, $D2, $X2):$XBD2), 2274 ".insn rx,$enc,$R1,$XBD2", []>; 2275 def InsnRXE : DirectiveInsnRXE<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2276 (bdxaddr12only $B2, $D2, $X2):$XBD2), 2277 ".insn rxe,$enc,$R1,$XBD2", []>; 2278 def InsnRXF : DirectiveInsnRXF<(outs), 2279 (ins imm64zx48:$enc, AnyReg:$R1, 2280 AnyReg:$R3, (bdxaddr12only $B2, $D2, $X2):$XBD2), 2281 ".insn rxf,$enc,$R1,$R3,$XBD2", []>; 2282 def InsnRXY : DirectiveInsnRXY<(outs), (ins imm64zx48:$enc, AnyReg:$R1, 2283 (bdxaddr20only $B2, $D2, $X2):$XBD2), 2284 ".insn rxy,$enc,$R1,$XBD2", []>; 2285 def InsnS : DirectiveInsnS<(outs), 2286 (ins imm64zx32:$enc, (bdaddr12only $B2, $D2):$BD2), 2287 ".insn s,$enc,$BD2", []>; 2288 def InsnSI : DirectiveInsnSI<(outs), 2289 (ins imm64zx32:$enc, (bdaddr12only $B1, $D1):$BD1, 2290 imm32sx8:$I2), 2291 ".insn si,$enc,$BD1,$I2", []>; 2292 def InsnSIY : DirectiveInsnSIY<(outs), 2293 (ins imm64zx48:$enc, 2294 (bdaddr20only $B1, $D1):$BD1, imm32zx8:$I2), 2295 ".insn siy,$enc,$BD1,$I2", []>; 2296 def InsnSIL : DirectiveInsnSIL<(outs), 2297 (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1, 2298 imm32zx16:$I2), 2299 ".insn sil,$enc,$BD1,$I2", []>; 2300 def InsnSS : DirectiveInsnSS<(outs), 2301 (ins imm64zx48:$enc, (bdraddr12only $B1, $D1, $R1):$RBD1, 2302 (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3), 2303 ".insn ss,$enc,$RBD1,$BD2,$R3", []>; 2304 def InsnSSE : DirectiveInsnSSE<(outs), 2305 (ins imm64zx48:$enc, 2306 (bdaddr12only $B1, $D1):$BD1,(bdaddr12only $B2, $D2):$BD2), 2307 ".insn sse,$enc,$BD1,$BD2", []>; 2308 def InsnSSF : DirectiveInsnSSF<(outs), 2309 (ins imm64zx48:$enc, (bdaddr12only $B1, $D1):$BD1, 2310 (bdaddr12only $B2, $D2):$BD2, AnyReg:$R3), 2311 ".insn ssf,$enc,$BD1,$BD2,$R3", []>; 2312 def InsnVRI : DirectiveInsnVRI<(outs), 2313 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2314 imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5), 2315 ".insn vri,$enc,$V1,$V2,$I3,$M4,$M5", []>; 2316 def InsnVRR : DirectiveInsnVRR<(outs), 2317 (ins imm64zx48:$enc, VR128:$V1, VR128:$V2, 2318 VR128:$V3, imm32zx4:$M4, imm32zx4:$M5, 2319 imm32zx4:$M6), 2320 ".insn vrr,$enc,$V1,$V2,$V3,$M4,$M5,$M6", []>; 2321 def InsnVRS : DirectiveInsnVRS<(outs), 2322 (ins imm64zx48:$enc, AnyReg:$R1, VR128:$V3, 2323 (bdaddr12only $B2, $D2):$BD2, imm32zx4:$M4), 2324 ".insn vrs,$enc,$BD2,$M4", []>; 2325 def InsnVRV : DirectiveInsnVRV<(outs), 2326 (ins imm64zx48:$enc, VR128:$V1, 2327 (bdvaddr12only $B2, $D2, $V2):$VBD2, imm32zx4:$M3), 2328 ".insn vrv,$enc,$V1,$VBD2,$M3", []>; 2329 def InsnVRX : DirectiveInsnVRX<(outs), 2330 (ins imm64zx48:$enc, VR128:$V1, 2331 (bdxaddr12only $B2, $D2, $X2):$XBD2, imm32zx4:$M3), 2332 ".insn vrx,$enc,$V1,$XBD2,$M3", []>; 2333 def InsnVSI : DirectiveInsnVSI<(outs), 2334 (ins imm64zx48:$enc, VR128:$V1, 2335 (bdaddr12only $B2, $D2):$BD2, imm32zx8:$I3), 2336 ".insn vsi,$enc,$V1,$BD2,$I3", []>; 2337} 2338 2339//===----------------------------------------------------------------------===// 2340// Peepholes. 2341//===----------------------------------------------------------------------===// 2342 2343// Avoid generating 2 XOR instructions. (xor (and x, y), y) is 2344// equivalent to (and (xor x, -1), y) 2345def : Pat<(and (xor GR64:$x, (i64 -1)), GR64:$y), 2346 (XGR GR64:$y, (NGR GR64:$y, GR64:$x))>; 2347 2348// Use LCGR/AGHI for i64 xor with -1. 2349def : Pat<(xor GR64:$x, (i64 -1)), 2350 (AGHI (LCGR GR64:$x), (i64 -1))>; 2351 2352// Shift/rotate instructions only use the last 6 bits of the second operand 2353// register, so we can safely use NILL (16 fewer bits than NILF) to only AND the 2354// last 16 bits. 2355// Complexity is added so that we match this before we match NILF on the AND 2356// operation alone. 2357let AddedComplexity = 4 in { 2358 def : Pat<(shl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2359 (SLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2360 2361 def : Pat<(sra GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2362 (SRA GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2363 2364 def : Pat<(srl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2365 (SRL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2366 2367 def : Pat<(shl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2368 (SLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2369 2370 def : Pat<(sra GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2371 (SRAG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2372 2373 def : Pat<(srl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2374 (SRLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2375 2376 def : Pat<(rotl GR32:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2377 (RLL GR32:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2378 2379 def : Pat<(rotl GR64:$val, (and GR32:$shift, imm32zx16trunc:$imm)), 2380 (RLLG GR64:$val, (NILL GR32:$shift, imm32zx16trunc:$imm), 0)>; 2381} 2382 2383// Substitute (x*64-s) with (-s), since shift/rotate instructions only 2384// use the last 6 bits of the second operand register (making it modulo 64). 2385let AddedComplexity = 4 in { 2386 def : Pat<(shl GR64:$val, (sub imm32mod64, GR32:$shift)), 2387 (SLLG GR64:$val, (LCR GR32:$shift), 0)>; 2388 2389 def : Pat<(sra GR64:$val, (sub imm32mod64, GR32:$shift)), 2390 (SRAG GR64:$val, (LCR GR32:$shift), 0)>; 2391 2392 def : Pat<(srl GR64:$val, (sub imm32mod64, GR32:$shift)), 2393 (SRLG GR64:$val, (LCR GR32:$shift), 0)>; 2394 2395 def : Pat<(rotl GR64:$val, (sub imm32mod64, GR32:$shift)), 2396 (RLLG GR64:$val, (LCR GR32:$shift), 0)>; 2397} 2398 2399// Peepholes for turning scalar operations into block operations. The length 2400// is given as one less for these pseudos. 2401defm : BlockLoadStore<anyextloadi8, i32, MVCImm, NCImm, OCImm, XCImm, 0>; 2402defm : BlockLoadStore<anyextloadi16, i32, MVCImm, NCImm, OCImm, XCImm, 1>; 2403defm : BlockLoadStore<load, i32, MVCImm, NCImm, OCImm, XCImm, 3>; 2404defm : BlockLoadStore<anyextloadi8, i64, MVCImm, NCImm, OCImm, XCImm, 0>; 2405defm : BlockLoadStore<anyextloadi16, i64, MVCImm, NCImm, OCImm, XCImm, 1>; 2406defm : BlockLoadStore<anyextloadi32, i64, MVCImm, NCImm, OCImm, XCImm, 3>; 2407defm : BlockLoadStore<load, i64, MVCImm, NCImm, OCImm, XCImm, 7>; 2408 2409//===----------------------------------------------------------------------===// 2410// Mnemonic Aliases 2411//===----------------------------------------------------------------------===// 2412 2413def JCT : MnemonicAlias<"jct", "brct">; 2414def JCTG : MnemonicAlias<"jctg", "brctg">; 2415def JC : MnemonicAlias<"jc", "brc">; 2416def JCTH : MnemonicAlias<"jcth", "brcth">; 2417def JAS : MnemonicAlias<"jas", "bras">; 2418def JASL : MnemonicAlias<"jasl", "brasl">; 2419def JXH : MnemonicAlias<"jxh", "brxh">; 2420def JXLE : MnemonicAlias<"jxle", "brxle">; 2421def JXHG : MnemonicAlias<"jxhg", "brxhg">; 2422def JXLEG : MnemonicAlias<"jxleg", "brxlg">; 2423 2424def BRU : MnemonicAlias<"bru", "j">; 2425def BRUL : MnemonicAlias<"brul", "jg", "gnu">; 2426def BRUL_HLASM : MnemonicAlias<"brul", "jlu", "hlasm">; 2427 2428foreach V = [ "E", "NE", "H", "NH", "L", "NL", "HE", "NHE", "LE", "NLE", 2429 "Z", "NZ", "P", "NP", "M", "NM", "LH", "NLH", "O", "NO" ] in { 2430 defm BRUAsm#V : MnemonicCondBranchAlias <CV<V>, "br#", "j#">; 2431 defm BRULAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jg#", "gnu">; 2432 defm BRUL_HLASMAsm#V : MnemonicCondBranchAlias <CV<V>, "br#l", "jl#", "hlasm">; 2433} 2434