xref: /llvm-project/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp (revision f9496060f665d9d5420fb5a93cee0c9d446f13d7) 
1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/ADT/STLExtras.h"
12 #include "llvm/MC/MCContext.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCStreamer.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCTargetAsmParser.h"
19 #include "llvm/Support/TargetRegistry.h"
20 
21 using namespace llvm;
22 
23 // Return true if Expr is in the range [MinValue, MaxValue].
24 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
25   if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) {
26     int64_t Value = CE->getValue();
27     return Value >= MinValue && Value <= MaxValue;
28   }
29   return false;
30 }
31 
32 namespace {
33 enum RegisterKind {
34   GR32Reg,
35   GRH32Reg,
36   GR64Reg,
37   GR128Reg,
38   ADDR32Reg,
39   ADDR64Reg,
40   FP32Reg,
41   FP64Reg,
42   FP128Reg
43 };
44 
45 enum MemoryKind {
46   BDMem,
47   BDXMem,
48   BDLMem
49 };
50 
51 class SystemZOperand : public MCParsedAsmOperand {
52 public:
53 private:
54   enum OperandKind {
55     KindInvalid,
56     KindToken,
57     KindReg,
58     KindAccessReg,
59     KindImm,
60     KindMem
61   };
62 
63   OperandKind Kind;
64   SMLoc StartLoc, EndLoc;
65 
66   // A string of length Length, starting at Data.
67   struct TokenOp {
68     const char *Data;
69     unsigned Length;
70   };
71 
72   // LLVM register Num, which has kind Kind.  In some ways it might be
73   // easier for this class to have a register bank (general, floating-point
74   // or access) and a raw register number (0-15).  This would postpone the
75   // interpretation of the operand to the add*() methods and avoid the need
76   // for context-dependent parsing.  However, we do things the current way
77   // because of the virtual getReg() method, which needs to distinguish
78   // between (say) %r0 used as a single register and %r0 used as a pair.
79   // Context-dependent parsing can also give us slightly better error
80   // messages when invalid pairs like %r1 are used.
81   struct RegOp {
82     RegisterKind Kind;
83     unsigned Num;
84   };
85 
86   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
87   // RegKind says what type the registers have (ADDR32Reg or ADDR64Reg).
88   // Length is the operand length for D(L,B)-style operands, otherwise
89   // it is null.
90   struct MemOp {
91     unsigned Base : 8;
92     unsigned Index : 8;
93     unsigned RegKind : 8;
94     unsigned Unused : 8;
95     const MCExpr *Disp;
96     const MCExpr *Length;
97   };
98 
99   union {
100     TokenOp Token;
101     RegOp Reg;
102     unsigned AccessReg;
103     const MCExpr *Imm;
104     MemOp Mem;
105   };
106 
107   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
108     : Kind(kind), StartLoc(startLoc), EndLoc(endLoc)
109   {}
110 
111   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
112     // Add as immediates when possible.  Null MCExpr = 0.
113     if (Expr == 0)
114       Inst.addOperand(MCOperand::CreateImm(0));
115     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
116       Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
117     else
118       Inst.addOperand(MCOperand::CreateExpr(Expr));
119   }
120 
121 public:
122   // Create particular kinds of operand.
123   static SystemZOperand *createInvalid(SMLoc StartLoc, SMLoc EndLoc) {
124     return new SystemZOperand(KindInvalid, StartLoc, EndLoc);
125   }
126   static SystemZOperand *createToken(StringRef Str, SMLoc Loc) {
127     SystemZOperand *Op = new SystemZOperand(KindToken, Loc, Loc);
128     Op->Token.Data = Str.data();
129     Op->Token.Length = Str.size();
130     return Op;
131   }
132   static SystemZOperand *createReg(RegisterKind Kind, unsigned Num,
133                                    SMLoc StartLoc, SMLoc EndLoc) {
134     SystemZOperand *Op = new SystemZOperand(KindReg, StartLoc, EndLoc);
135     Op->Reg.Kind = Kind;
136     Op->Reg.Num = Num;
137     return Op;
138   }
139   static SystemZOperand *createAccessReg(unsigned Num, SMLoc StartLoc,
140                                          SMLoc EndLoc) {
141     SystemZOperand *Op = new SystemZOperand(KindAccessReg, StartLoc, EndLoc);
142     Op->AccessReg = Num;
143     return Op;
144   }
145   static SystemZOperand *createImm(const MCExpr *Expr, SMLoc StartLoc,
146                                    SMLoc EndLoc) {
147     SystemZOperand *Op = new SystemZOperand(KindImm, StartLoc, EndLoc);
148     Op->Imm = Expr;
149     return Op;
150   }
151   static SystemZOperand *createMem(RegisterKind RegKind, unsigned Base,
152                                    const MCExpr *Disp, unsigned Index,
153                                    const MCExpr *Length, SMLoc StartLoc,
154                                    SMLoc EndLoc) {
155     SystemZOperand *Op = new SystemZOperand(KindMem, StartLoc, EndLoc);
156     Op->Mem.RegKind = RegKind;
157     Op->Mem.Base = Base;
158     Op->Mem.Index = Index;
159     Op->Mem.Disp = Disp;
160     Op->Mem.Length = Length;
161     return Op;
162   }
163 
164   // Token operands
165   virtual bool isToken() const LLVM_OVERRIDE {
166     return Kind == KindToken;
167   }
168   StringRef getToken() const {
169     assert(Kind == KindToken && "Not a token");
170     return StringRef(Token.Data, Token.Length);
171   }
172 
173   // Register operands.
174   virtual bool isReg() const LLVM_OVERRIDE {
175     return Kind == KindReg;
176   }
177   bool isReg(RegisterKind RegKind) const {
178     return Kind == KindReg && Reg.Kind == RegKind;
179   }
180   virtual unsigned getReg() const LLVM_OVERRIDE {
181     assert(Kind == KindReg && "Not a register");
182     return Reg.Num;
183   }
184 
185   // Access register operands.  Access registers aren't exposed to LLVM
186   // as registers.
187   bool isAccessReg() const {
188     return Kind == KindAccessReg;
189   }
190 
191   // Immediate operands.
192   virtual bool isImm() const LLVM_OVERRIDE {
193     return Kind == KindImm;
194   }
195   bool isImm(int64_t MinValue, int64_t MaxValue) const {
196     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
197   }
198   const MCExpr *getImm() const {
199     assert(Kind == KindImm && "Not an immediate");
200     return Imm;
201   }
202 
203   // Memory operands.
204   virtual bool isMem() const LLVM_OVERRIDE {
205     return Kind == KindMem;
206   }
207   bool isMem(RegisterKind RegKind, MemoryKind MemKind) const {
208     return (Kind == KindMem &&
209             Mem.RegKind == RegKind &&
210             (MemKind == BDXMem || !Mem.Index) &&
211             (MemKind == BDLMem) == (Mem.Length != 0));
212   }
213   bool isMemDisp12(RegisterKind RegKind, MemoryKind MemKind) const {
214     return isMem(RegKind, MemKind) && inRange(Mem.Disp, 0, 0xfff);
215   }
216   bool isMemDisp20(RegisterKind RegKind, MemoryKind MemKind) const {
217     return isMem(RegKind, MemKind) && inRange(Mem.Disp, -524288, 524287);
218   }
219   bool isMemDisp12Len8(RegisterKind RegKind) const {
220     return isMemDisp12(RegKind, BDLMem) && inRange(Mem.Length, 1, 0x100);
221   }
222 
223   // Override MCParsedAsmOperand.
224   virtual SMLoc getStartLoc() const LLVM_OVERRIDE { return StartLoc; }
225   virtual SMLoc getEndLoc() const LLVM_OVERRIDE { return EndLoc; }
226   virtual void print(raw_ostream &OS) const LLVM_OVERRIDE;
227 
228   // Used by the TableGen code to add particular types of operand
229   // to an instruction.
230   void addRegOperands(MCInst &Inst, unsigned N) const {
231     assert(N == 1 && "Invalid number of operands");
232     Inst.addOperand(MCOperand::CreateReg(getReg()));
233   }
234   void addAccessRegOperands(MCInst &Inst, unsigned N) const {
235     assert(N == 1 && "Invalid number of operands");
236     assert(Kind == KindAccessReg && "Invalid operand type");
237     Inst.addOperand(MCOperand::CreateImm(AccessReg));
238   }
239   void addImmOperands(MCInst &Inst, unsigned N) const {
240     assert(N == 1 && "Invalid number of operands");
241     addExpr(Inst, getImm());
242   }
243   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
244     assert(N == 2 && "Invalid number of operands");
245     assert(Kind == KindMem && Mem.Index == 0 && "Invalid operand type");
246     Inst.addOperand(MCOperand::CreateReg(Mem.Base));
247     addExpr(Inst, Mem.Disp);
248   }
249   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
250     assert(N == 3 && "Invalid number of operands");
251     assert(Kind == KindMem && "Invalid operand type");
252     Inst.addOperand(MCOperand::CreateReg(Mem.Base));
253     addExpr(Inst, Mem.Disp);
254     Inst.addOperand(MCOperand::CreateReg(Mem.Index));
255   }
256   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
257     assert(N == 3 && "Invalid number of operands");
258     assert(Kind == KindMem && "Invalid operand type");
259     Inst.addOperand(MCOperand::CreateReg(Mem.Base));
260     addExpr(Inst, Mem.Disp);
261     addExpr(Inst, Mem.Length);
262   }
263 
264   // Used by the TableGen code to check for particular operand types.
265   bool isGR32() const { return isReg(GR32Reg); }
266   bool isGRH32() const { return isReg(GRH32Reg); }
267   bool isGR64() const { return isReg(GR64Reg); }
268   bool isGR128() const { return isReg(GR128Reg); }
269   bool isADDR32() const { return isReg(ADDR32Reg); }
270   bool isADDR64() const { return isReg(ADDR64Reg); }
271   bool isADDR128() const { return false; }
272   bool isFP32() const { return isReg(FP32Reg); }
273   bool isFP64() const { return isReg(FP64Reg); }
274   bool isFP128() const { return isReg(FP128Reg); }
275   bool isBDAddr32Disp12() const { return isMemDisp12(ADDR32Reg, BDMem); }
276   bool isBDAddr32Disp20() const { return isMemDisp20(ADDR32Reg, BDMem); }
277   bool isBDAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDMem); }
278   bool isBDAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDMem); }
279   bool isBDXAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDXMem); }
280   bool isBDXAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDXMem); }
281   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
282   bool isU4Imm() const { return isImm(0, 15); }
283   bool isU6Imm() const { return isImm(0, 63); }
284   bool isU8Imm() const { return isImm(0, 255); }
285   bool isS8Imm() const { return isImm(-128, 127); }
286   bool isU16Imm() const { return isImm(0, 65535); }
287   bool isS16Imm() const { return isImm(-32768, 32767); }
288   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
289   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
290 };
291 
292 class SystemZAsmParser : public MCTargetAsmParser {
293 #define GET_ASSEMBLER_HEADER
294 #include "SystemZGenAsmMatcher.inc"
295 
296 private:
297   MCSubtargetInfo &STI;
298   MCAsmParser &Parser;
299   enum RegisterGroup {
300     RegGR,
301     RegFP,
302     RegAccess
303   };
304   struct Register {
305     RegisterGroup Group;
306     unsigned Num;
307     SMLoc StartLoc, EndLoc;
308   };
309 
310   bool parseRegister(Register &Reg);
311 
312   bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
313                      bool IsAddress = false);
314 
315   OperandMatchResultTy
316   parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
317                 RegisterGroup Group, const unsigned *Regs, RegisterKind Kind);
318 
319   bool parseAddress(unsigned &Base, const MCExpr *&Disp,
320                     unsigned &Index, const MCExpr *&Length,
321                     const unsigned *Regs, RegisterKind RegKind);
322 
323   OperandMatchResultTy
324   parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
325                const unsigned *Regs, RegisterKind RegKind,
326                MemoryKind MemKind);
327 
328   bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
329                     StringRef Mnemonic);
330 
331 public:
332   SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
333                    const MCInstrInfo &MII)
334       : MCTargetAsmParser(), STI(sti), Parser(parser) {
335     MCAsmParserExtension::Initialize(Parser);
336 
337     // Initialize the set of available features.
338     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
339   }
340 
341   // Override MCTargetAsmParser.
342   virtual bool ParseDirective(AsmToken DirectiveID) LLVM_OVERRIDE;
343   virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
344                              SMLoc &EndLoc) LLVM_OVERRIDE;
345   virtual bool ParseInstruction(ParseInstructionInfo &Info,
346                                 StringRef Name, SMLoc NameLoc,
347                                 SmallVectorImpl<MCParsedAsmOperand*> &Operands)
348     LLVM_OVERRIDE;
349   virtual bool
350     MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
351                             SmallVectorImpl<MCParsedAsmOperand*> &Operands,
352                             MCStreamer &Out, unsigned &ErrorInfo,
353                             bool MatchingInlineAsm) LLVM_OVERRIDE;
354 
355   // Used by the TableGen code to parse particular operand types.
356   OperandMatchResultTy
357   parseGR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
358     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
359   }
360   OperandMatchResultTy
361   parseGRH32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
362     return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
363   }
364   OperandMatchResultTy
365   parseGR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
366     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
367   }
368   OperandMatchResultTy
369   parseGR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
370     return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
371   }
372   OperandMatchResultTy
373   parseADDR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
374     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
375   }
376   OperandMatchResultTy
377   parseADDR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
378     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
379   }
380   OperandMatchResultTy
381   parseADDR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
382     llvm_unreachable("Shouldn't be used as an operand");
383   }
384   OperandMatchResultTy
385   parseFP32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
386     return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
387   }
388   OperandMatchResultTy
389   parseFP64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
390     return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
391   }
392   OperandMatchResultTy
393   parseFP128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
394     return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
395   }
396   OperandMatchResultTy
397   parseBDAddr32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
398     return parseAddress(Operands, SystemZMC::GR32Regs, ADDR32Reg, BDMem);
399   }
400   OperandMatchResultTy
401   parseBDAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
402     return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDMem);
403   }
404   OperandMatchResultTy
405   parseBDXAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
406     return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDXMem);
407   }
408   OperandMatchResultTy
409   parseBDLAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
410     return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDLMem);
411   }
412   OperandMatchResultTy
413   parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
414   OperandMatchResultTy
415   parsePCRel(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
416              int64_t MinVal, int64_t MaxVal);
417   OperandMatchResultTy
418   parsePCRel16(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
419     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1);
420   }
421   OperandMatchResultTy
422   parsePCRel32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
423     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1);
424   }
425 };
426 }
427 
428 #define GET_REGISTER_MATCHER
429 #define GET_SUBTARGET_FEATURE_NAME
430 #define GET_MATCHER_IMPLEMENTATION
431 #include "SystemZGenAsmMatcher.inc"
432 
433 void SystemZOperand::print(raw_ostream &OS) const {
434   llvm_unreachable("Not implemented");
435 }
436 
437 // Parse one register of the form %<prefix><number>.
438 bool SystemZAsmParser::parseRegister(Register &Reg) {
439   Reg.StartLoc = Parser.getTok().getLoc();
440 
441   // Eat the % prefix.
442   if (Parser.getTok().isNot(AsmToken::Percent))
443     return Error(Parser.getTok().getLoc(), "register expected");
444   Parser.Lex();
445 
446   // Expect a register name.
447   if (Parser.getTok().isNot(AsmToken::Identifier))
448     return Error(Reg.StartLoc, "invalid register");
449 
450   // Check that there's a prefix.
451   StringRef Name = Parser.getTok().getString();
452   if (Name.size() < 2)
453     return Error(Reg.StartLoc, "invalid register");
454   char Prefix = Name[0];
455 
456   // Treat the rest of the register name as a register number.
457   if (Name.substr(1).getAsInteger(10, Reg.Num))
458     return Error(Reg.StartLoc, "invalid register");
459 
460   // Look for valid combinations of prefix and number.
461   if (Prefix == 'r' && Reg.Num < 16)
462     Reg.Group = RegGR;
463   else if (Prefix == 'f' && Reg.Num < 16)
464     Reg.Group = RegFP;
465   else if (Prefix == 'a' && Reg.Num < 16)
466     Reg.Group = RegAccess;
467   else
468     return Error(Reg.StartLoc, "invalid register");
469 
470   Reg.EndLoc = Parser.getTok().getLoc();
471   Parser.Lex();
472   return false;
473 }
474 
475 // Parse a register of group Group.  If Regs is nonnull, use it to map
476 // the raw register number to LLVM numbering, with zero entries indicating
477 // an invalid register.  IsAddress says whether the register appears in an
478 // address context.
479 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
480                                      const unsigned *Regs, bool IsAddress) {
481   if (parseRegister(Reg))
482     return true;
483   if (Reg.Group != Group)
484     return Error(Reg.StartLoc, "invalid operand for instruction");
485   if (Regs && Regs[Reg.Num] == 0)
486     return Error(Reg.StartLoc, "invalid register pair");
487   if (Reg.Num == 0 && IsAddress)
488     return Error(Reg.StartLoc, "%r0 used in an address");
489   if (Regs)
490     Reg.Num = Regs[Reg.Num];
491   return false;
492 }
493 
494 // Parse a register and add it to Operands.  The other arguments are as above.
495 SystemZAsmParser::OperandMatchResultTy
496 SystemZAsmParser::parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
497                                 RegisterGroup Group, const unsigned *Regs,
498                                 RegisterKind Kind) {
499   if (Parser.getTok().isNot(AsmToken::Percent))
500     return MatchOperand_NoMatch;
501 
502   Register Reg;
503   bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
504   if (parseRegister(Reg, Group, Regs, IsAddress))
505     return MatchOperand_ParseFail;
506 
507   Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
508                                                Reg.StartLoc, Reg.EndLoc));
509   return MatchOperand_Success;
510 }
511 
512 // Parse a memory operand into Base, Disp, Index and Length.
513 // Regs maps asm register numbers to LLVM register numbers and RegKind
514 // says what kind of address register we're using (ADDR32Reg or ADDR64Reg).
515 bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
516                                     unsigned &Index, const MCExpr *&Length,
517                                     const unsigned *Regs,
518                                     RegisterKind RegKind) {
519   // Parse the displacement, which must always be present.
520   if (getParser().parseExpression(Disp))
521     return true;
522 
523   // Parse the optional base and index.
524   Index = 0;
525   Base = 0;
526   Length = 0;
527   if (getLexer().is(AsmToken::LParen)) {
528     Parser.Lex();
529 
530     if (getLexer().is(AsmToken::Percent)) {
531       // Parse the first register and decide whether it's a base or an index.
532       Register Reg;
533       if (parseRegister(Reg, RegGR, Regs, RegKind))
534         return true;
535       if (getLexer().is(AsmToken::Comma))
536         Index = Reg.Num;
537       else
538         Base = Reg.Num;
539     } else {
540       // Parse the length.
541       if (getParser().parseExpression(Length))
542         return true;
543     }
544 
545     // Check whether there's a second register.  It's the base if so.
546     if (getLexer().is(AsmToken::Comma)) {
547       Parser.Lex();
548       Register Reg;
549       if (parseRegister(Reg, RegGR, Regs, RegKind))
550         return true;
551       Base = Reg.Num;
552     }
553 
554     // Consume the closing bracket.
555     if (getLexer().isNot(AsmToken::RParen))
556       return Error(Parser.getTok().getLoc(), "unexpected token in address");
557     Parser.Lex();
558   }
559   return false;
560 }
561 
562 // Parse a memory operand and add it to Operands.  The other arguments
563 // are as above.
564 SystemZAsmParser::OperandMatchResultTy
565 SystemZAsmParser::parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
566                                const unsigned *Regs, RegisterKind RegKind,
567                                MemoryKind MemKind) {
568   SMLoc StartLoc = Parser.getTok().getLoc();
569   unsigned Base, Index;
570   const MCExpr *Disp;
571   const MCExpr *Length;
572   if (parseAddress(Base, Disp, Index, Length, Regs, RegKind))
573     return MatchOperand_ParseFail;
574 
575   if (Index && MemKind != BDXMem)
576     {
577       Error(StartLoc, "invalid use of indexed addressing");
578       return MatchOperand_ParseFail;
579     }
580 
581   if (Length && MemKind != BDLMem)
582     {
583       Error(StartLoc, "invalid use of length addressing");
584       return MatchOperand_ParseFail;
585     }
586 
587   if (!Length && MemKind == BDLMem)
588     {
589       Error(StartLoc, "missing length in address");
590       return MatchOperand_ParseFail;
591     }
592 
593   SMLoc EndLoc =
594     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
595   Operands.push_back(SystemZOperand::createMem(RegKind, Base, Disp, Index,
596                                                Length, StartLoc, EndLoc));
597   return MatchOperand_Success;
598 }
599 
600 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
601   return true;
602 }
603 
604 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
605                                      SMLoc &EndLoc) {
606   Register Reg;
607   if (parseRegister(Reg))
608     return true;
609   if (Reg.Group == RegGR)
610     RegNo = SystemZMC::GR64Regs[Reg.Num];
611   else if (Reg.Group == RegFP)
612     RegNo = SystemZMC::FP64Regs[Reg.Num];
613   else
614     // FIXME: Access registers aren't modelled as LLVM registers yet.
615     return Error(Reg.StartLoc, "invalid operand for instruction");
616   StartLoc = Reg.StartLoc;
617   EndLoc = Reg.EndLoc;
618   return false;
619 }
620 
621 bool SystemZAsmParser::
622 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
623                  SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
624   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
625 
626   // Read the remaining operands.
627   if (getLexer().isNot(AsmToken::EndOfStatement)) {
628     // Read the first operand.
629     if (parseOperand(Operands, Name)) {
630       Parser.eatToEndOfStatement();
631       return true;
632     }
633 
634     // Read any subsequent operands.
635     while (getLexer().is(AsmToken::Comma)) {
636       Parser.Lex();
637       if (parseOperand(Operands, Name)) {
638         Parser.eatToEndOfStatement();
639         return true;
640       }
641     }
642     if (getLexer().isNot(AsmToken::EndOfStatement)) {
643       SMLoc Loc = getLexer().getLoc();
644       Parser.eatToEndOfStatement();
645       return Error(Loc, "unexpected token in argument list");
646     }
647   }
648 
649   // Consume the EndOfStatement.
650   Parser.Lex();
651   return false;
652 }
653 
654 bool SystemZAsmParser::
655 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
656              StringRef Mnemonic) {
657   // Check if the current operand has a custom associated parser, if so, try to
658   // custom parse the operand, or fallback to the general approach.
659   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
660   if (ResTy == MatchOperand_Success)
661     return false;
662 
663   // If there wasn't a custom match, try the generic matcher below. Otherwise,
664   // there was a match, but an error occurred, in which case, just return that
665   // the operand parsing failed.
666   if (ResTy == MatchOperand_ParseFail)
667     return true;
668 
669   // Check for a register.  All real register operands should have used
670   // a context-dependent parse routine, which gives the required register
671   // class.  The code is here to mop up other cases, like those where
672   // the instruction isn't recognized.
673   if (Parser.getTok().is(AsmToken::Percent)) {
674     Register Reg;
675     if (parseRegister(Reg))
676       return true;
677     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
678     return false;
679   }
680 
681   // The only other type of operand is an immediate or address.  As above,
682   // real address operands should have used a context-dependent parse routine,
683   // so we treat any plain expression as an immediate.
684   SMLoc StartLoc = Parser.getTok().getLoc();
685   unsigned Base, Index;
686   const MCExpr *Expr, *Length;
687   if (parseAddress(Base, Expr, Index, Length, SystemZMC::GR64Regs, ADDR64Reg))
688     return true;
689 
690   SMLoc EndLoc =
691     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
692   if (Base || Index || Length)
693     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
694   else
695     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
696   return false;
697 }
698 
699 bool SystemZAsmParser::
700 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
701                         SmallVectorImpl<MCParsedAsmOperand*> &Operands,
702                         MCStreamer &Out, unsigned &ErrorInfo,
703                         bool MatchingInlineAsm) {
704   MCInst Inst;
705   unsigned MatchResult;
706 
707   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
708                                      MatchingInlineAsm);
709   switch (MatchResult) {
710   default: break;
711   case Match_Success:
712     Inst.setLoc(IDLoc);
713     Out.EmitInstruction(Inst);
714     return false;
715 
716   case Match_MissingFeature: {
717     assert(ErrorInfo && "Unknown missing feature!");
718     // Special case the error message for the very common case where only
719     // a single subtarget feature is missing
720     std::string Msg = "instruction requires:";
721     unsigned Mask = 1;
722     for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
723       if (ErrorInfo & Mask) {
724         Msg += " ";
725         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
726       }
727       Mask <<= 1;
728     }
729     return Error(IDLoc, Msg);
730   }
731 
732   case Match_InvalidOperand: {
733     SMLoc ErrorLoc = IDLoc;
734     if (ErrorInfo != ~0U) {
735       if (ErrorInfo >= Operands.size())
736         return Error(IDLoc, "too few operands for instruction");
737 
738       ErrorLoc = ((SystemZOperand*)Operands[ErrorInfo])->getStartLoc();
739       if (ErrorLoc == SMLoc())
740         ErrorLoc = IDLoc;
741     }
742     return Error(ErrorLoc, "invalid operand for instruction");
743   }
744 
745   case Match_MnemonicFail:
746     return Error(IDLoc, "invalid instruction");
747   }
748 
749   llvm_unreachable("Unexpected match type");
750 }
751 
752 SystemZAsmParser::OperandMatchResultTy SystemZAsmParser::
753 parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
754   if (Parser.getTok().isNot(AsmToken::Percent))
755     return MatchOperand_NoMatch;
756 
757   Register Reg;
758   if (parseRegister(Reg, RegAccess, 0))
759     return MatchOperand_ParseFail;
760 
761   Operands.push_back(SystemZOperand::createAccessReg(Reg.Num,
762                                                      Reg.StartLoc,
763                                                      Reg.EndLoc));
764   return MatchOperand_Success;
765 }
766 
767 SystemZAsmParser::OperandMatchResultTy SystemZAsmParser::
768 parsePCRel(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
769            int64_t MinVal, int64_t MaxVal) {
770   MCContext &Ctx = getContext();
771   MCStreamer &Out = getStreamer();
772   const MCExpr *Expr;
773   SMLoc StartLoc = Parser.getTok().getLoc();
774   if (getParser().parseExpression(Expr))
775     return MatchOperand_NoMatch;
776 
777   // For consistency with the GNU assembler, treat immediates as offsets
778   // from ".".
779   if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) {
780     int64_t Value = CE->getValue();
781     if ((Value & 1) || Value < MinVal || Value > MaxVal) {
782       Error(StartLoc, "offset out of range");
783       return MatchOperand_ParseFail;
784     }
785     MCSymbol *Sym = Ctx.CreateTempSymbol();
786     Out.EmitLabel(Sym);
787     const MCExpr *Base = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
788                                                  Ctx);
789     Expr = Value == 0 ? Base : MCBinaryExpr::CreateAdd(Base, Expr, Ctx);
790   }
791 
792   SMLoc EndLoc =
793     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
794   Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
795   return MatchOperand_Success;
796 }
797 
798 // Force static initialization.
799 extern "C" void LLVMInitializeSystemZAsmParser() {
800   RegisterMCAsmParser<SystemZAsmParser> X(TheSystemZTarget);
801 }
802