xref: /llvm-project/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp (revision e6c13e4abd944f7d1ae85816063aca468a3bfcb8) 
1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/ADT/STLExtras.h"
12 #include "llvm/MC/MCContext.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCStreamer.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCTargetAsmParser.h"
19 #include "llvm/Support/TargetRegistry.h"
20 
21 using namespace llvm;
22 
23 // Return true if Expr is in the range [MinValue, MaxValue].
24 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
25   if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) {
26     int64_t Value = CE->getValue();
27     return Value >= MinValue && Value <= MaxValue;
28   }
29   return false;
30 }
31 
32 namespace {
33 enum RegisterKind {
34   GR32Reg,
35   GRH32Reg,
36   GR64Reg,
37   GR128Reg,
38   ADDR32Reg,
39   ADDR64Reg,
40   FP32Reg,
41   FP64Reg,
42   FP128Reg
43 };
44 
45 enum MemoryKind {
46   BDMem,
47   BDXMem,
48   BDLMem
49 };
50 
51 class SystemZOperand : public MCParsedAsmOperand {
52 public:
53 private:
54   enum OperandKind {
55     KindInvalid,
56     KindToken,
57     KindReg,
58     KindAccessReg,
59     KindImm,
60     KindMem
61   };
62 
63   OperandKind Kind;
64   SMLoc StartLoc, EndLoc;
65 
66   // A string of length Length, starting at Data.
67   struct TokenOp {
68     const char *Data;
69     unsigned Length;
70   };
71 
72   // LLVM register Num, which has kind Kind.  In some ways it might be
73   // easier for this class to have a register bank (general, floating-point
74   // or access) and a raw register number (0-15).  This would postpone the
75   // interpretation of the operand to the add*() methods and avoid the need
76   // for context-dependent parsing.  However, we do things the current way
77   // because of the virtual getReg() method, which needs to distinguish
78   // between (say) %r0 used as a single register and %r0 used as a pair.
79   // Context-dependent parsing can also give us slightly better error
80   // messages when invalid pairs like %r1 are used.
81   struct RegOp {
82     RegisterKind Kind;
83     unsigned Num;
84   };
85 
86   // Base + Disp + Index, where Base and Index are LLVM registers or 0.
87   // RegKind says what type the registers have (ADDR32Reg or ADDR64Reg).
88   // Length is the operand length for D(L,B)-style operands, otherwise
89   // it is null.
90   struct MemOp {
91     unsigned Base : 8;
92     unsigned Index : 8;
93     unsigned RegKind : 8;
94     unsigned Unused : 8;
95     const MCExpr *Disp;
96     const MCExpr *Length;
97   };
98 
99   union {
100     TokenOp Token;
101     RegOp Reg;
102     unsigned AccessReg;
103     const MCExpr *Imm;
104     MemOp Mem;
105   };
106 
107   SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
108     : Kind(kind), StartLoc(startLoc), EndLoc(endLoc)
109   {}
110 
111   void addExpr(MCInst &Inst, const MCExpr *Expr) const {
112     // Add as immediates when possible.  Null MCExpr = 0.
113     if (Expr == 0)
114       Inst.addOperand(MCOperand::CreateImm(0));
115     else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
116       Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
117     else
118       Inst.addOperand(MCOperand::CreateExpr(Expr));
119   }
120 
121 public:
122   // Create particular kinds of operand.
123   static SystemZOperand *createInvalid(SMLoc StartLoc, SMLoc EndLoc) {
124     return new SystemZOperand(KindInvalid, StartLoc, EndLoc);
125   }
126   static SystemZOperand *createToken(StringRef Str, SMLoc Loc) {
127     SystemZOperand *Op = new SystemZOperand(KindToken, Loc, Loc);
128     Op->Token.Data = Str.data();
129     Op->Token.Length = Str.size();
130     return Op;
131   }
132   static SystemZOperand *createReg(RegisterKind Kind, unsigned Num,
133                                    SMLoc StartLoc, SMLoc EndLoc) {
134     SystemZOperand *Op = new SystemZOperand(KindReg, StartLoc, EndLoc);
135     Op->Reg.Kind = Kind;
136     Op->Reg.Num = Num;
137     return Op;
138   }
139   static SystemZOperand *createAccessReg(unsigned Num, SMLoc StartLoc,
140                                          SMLoc EndLoc) {
141     SystemZOperand *Op = new SystemZOperand(KindAccessReg, StartLoc, EndLoc);
142     Op->AccessReg = Num;
143     return Op;
144   }
145   static SystemZOperand *createImm(const MCExpr *Expr, SMLoc StartLoc,
146                                    SMLoc EndLoc) {
147     SystemZOperand *Op = new SystemZOperand(KindImm, StartLoc, EndLoc);
148     Op->Imm = Expr;
149     return Op;
150   }
151   static SystemZOperand *createMem(RegisterKind RegKind, unsigned Base,
152                                    const MCExpr *Disp, unsigned Index,
153                                    const MCExpr *Length, SMLoc StartLoc,
154                                    SMLoc EndLoc) {
155     SystemZOperand *Op = new SystemZOperand(KindMem, StartLoc, EndLoc);
156     Op->Mem.RegKind = RegKind;
157     Op->Mem.Base = Base;
158     Op->Mem.Index = Index;
159     Op->Mem.Disp = Disp;
160     Op->Mem.Length = Length;
161     return Op;
162   }
163 
164   // Token operands
165   virtual bool isToken() const LLVM_OVERRIDE {
166     return Kind == KindToken;
167   }
168   StringRef getToken() const {
169     assert(Kind == KindToken && "Not a token");
170     return StringRef(Token.Data, Token.Length);
171   }
172 
173   // Register operands.
174   virtual bool isReg() const LLVM_OVERRIDE {
175     return Kind == KindReg;
176   }
177   bool isReg(RegisterKind RegKind) const {
178     return Kind == KindReg && Reg.Kind == RegKind;
179   }
180   virtual unsigned getReg() const LLVM_OVERRIDE {
181     assert(Kind == KindReg && "Not a register");
182     return Reg.Num;
183   }
184 
185   // Access register operands.  Access registers aren't exposed to LLVM
186   // as registers.
187   bool isAccessReg() const {
188     return Kind == KindAccessReg;
189   }
190 
191   // Immediate operands.
192   virtual bool isImm() const LLVM_OVERRIDE {
193     return Kind == KindImm;
194   }
195   bool isImm(int64_t MinValue, int64_t MaxValue) const {
196     return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
197   }
198   const MCExpr *getImm() const {
199     assert(Kind == KindImm && "Not an immediate");
200     return Imm;
201   }
202 
203   // Memory operands.
204   virtual bool isMem() const LLVM_OVERRIDE {
205     return Kind == KindMem;
206   }
207   bool isMem(RegisterKind RegKind, MemoryKind MemKind) const {
208     return (Kind == KindMem &&
209             Mem.RegKind == RegKind &&
210             (MemKind == BDXMem || !Mem.Index) &&
211             (MemKind == BDLMem) == (Mem.Length != 0));
212   }
213   bool isMemDisp12(RegisterKind RegKind, MemoryKind MemKind) const {
214     return isMem(RegKind, MemKind) && inRange(Mem.Disp, 0, 0xfff);
215   }
216   bool isMemDisp20(RegisterKind RegKind, MemoryKind MemKind) const {
217     return isMem(RegKind, MemKind) && inRange(Mem.Disp, -524288, 524287);
218   }
219   bool isMemDisp12Len8(RegisterKind RegKind) const {
220     return isMemDisp12(RegKind, BDLMem) && inRange(Mem.Length, 1, 0x100);
221   }
222 
223   // Override MCParsedAsmOperand.
224   virtual SMLoc getStartLoc() const LLVM_OVERRIDE { return StartLoc; }
225   virtual SMLoc getEndLoc() const LLVM_OVERRIDE { return EndLoc; }
226   virtual void print(raw_ostream &OS) const LLVM_OVERRIDE;
227 
228   // Used by the TableGen code to add particular types of operand
229   // to an instruction.
230   void addRegOperands(MCInst &Inst, unsigned N) const {
231     assert(N == 1 && "Invalid number of operands");
232     Inst.addOperand(MCOperand::CreateReg(getReg()));
233   }
234   void addAccessRegOperands(MCInst &Inst, unsigned N) const {
235     assert(N == 1 && "Invalid number of operands");
236     assert(Kind == KindAccessReg && "Invalid operand type");
237     Inst.addOperand(MCOperand::CreateImm(AccessReg));
238   }
239   void addImmOperands(MCInst &Inst, unsigned N) const {
240     assert(N == 1 && "Invalid number of operands");
241     addExpr(Inst, getImm());
242   }
243   void addBDAddrOperands(MCInst &Inst, unsigned N) const {
244     assert(N == 2 && "Invalid number of operands");
245     assert(Kind == KindMem && Mem.Index == 0 && "Invalid operand type");
246     Inst.addOperand(MCOperand::CreateReg(Mem.Base));
247     addExpr(Inst, Mem.Disp);
248   }
249   void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
250     assert(N == 3 && "Invalid number of operands");
251     assert(Kind == KindMem && "Invalid operand type");
252     Inst.addOperand(MCOperand::CreateReg(Mem.Base));
253     addExpr(Inst, Mem.Disp);
254     Inst.addOperand(MCOperand::CreateReg(Mem.Index));
255   }
256   void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
257     assert(N == 3 && "Invalid number of operands");
258     assert(Kind == KindMem && "Invalid operand type");
259     Inst.addOperand(MCOperand::CreateReg(Mem.Base));
260     addExpr(Inst, Mem.Disp);
261     addExpr(Inst, Mem.Length);
262   }
263 
264   // Used by the TableGen code to check for particular operand types.
265   bool isGR32() const { return isReg(GR32Reg); }
266   bool isGRH32() const { return isReg(GRH32Reg); }
267   bool isGRX32() const { return false; }
268   bool isGR64() const { return isReg(GR64Reg); }
269   bool isGR128() const { return isReg(GR128Reg); }
270   bool isADDR32() const { return isReg(ADDR32Reg); }
271   bool isADDR64() const { return isReg(ADDR64Reg); }
272   bool isADDR128() const { return false; }
273   bool isFP32() const { return isReg(FP32Reg); }
274   bool isFP64() const { return isReg(FP64Reg); }
275   bool isFP128() const { return isReg(FP128Reg); }
276   bool isBDAddr32Disp12() const { return isMemDisp12(ADDR32Reg, BDMem); }
277   bool isBDAddr32Disp20() const { return isMemDisp20(ADDR32Reg, BDMem); }
278   bool isBDAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDMem); }
279   bool isBDAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDMem); }
280   bool isBDXAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDXMem); }
281   bool isBDXAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDXMem); }
282   bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
283   bool isU4Imm() const { return isImm(0, 15); }
284   bool isU6Imm() const { return isImm(0, 63); }
285   bool isU8Imm() const { return isImm(0, 255); }
286   bool isS8Imm() const { return isImm(-128, 127); }
287   bool isU16Imm() const { return isImm(0, 65535); }
288   bool isS16Imm() const { return isImm(-32768, 32767); }
289   bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
290   bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
291 };
292 
293 class SystemZAsmParser : public MCTargetAsmParser {
294 #define GET_ASSEMBLER_HEADER
295 #include "SystemZGenAsmMatcher.inc"
296 
297 private:
298   MCSubtargetInfo &STI;
299   MCAsmParser &Parser;
300   enum RegisterGroup {
301     RegGR,
302     RegFP,
303     RegAccess
304   };
305   struct Register {
306     RegisterGroup Group;
307     unsigned Num;
308     SMLoc StartLoc, EndLoc;
309   };
310 
311   bool parseRegister(Register &Reg);
312 
313   bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
314                      bool IsAddress = false);
315 
316   OperandMatchResultTy
317   parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
318                 RegisterGroup Group, const unsigned *Regs, RegisterKind Kind);
319 
320   bool parseAddress(unsigned &Base, const MCExpr *&Disp,
321                     unsigned &Index, const MCExpr *&Length,
322                     const unsigned *Regs, RegisterKind RegKind);
323 
324   OperandMatchResultTy
325   parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
326                const unsigned *Regs, RegisterKind RegKind,
327                MemoryKind MemKind);
328 
329   bool parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
330                     StringRef Mnemonic);
331 
332 public:
333   SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
334                    const MCInstrInfo &MII)
335       : MCTargetAsmParser(), STI(sti), Parser(parser) {
336     MCAsmParserExtension::Initialize(Parser);
337 
338     // Initialize the set of available features.
339     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
340   }
341 
342   // Override MCTargetAsmParser.
343   virtual bool ParseDirective(AsmToken DirectiveID) LLVM_OVERRIDE;
344   virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
345                              SMLoc &EndLoc) LLVM_OVERRIDE;
346   virtual bool ParseInstruction(ParseInstructionInfo &Info,
347                                 StringRef Name, SMLoc NameLoc,
348                                 SmallVectorImpl<MCParsedAsmOperand*> &Operands)
349     LLVM_OVERRIDE;
350   virtual bool
351     MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
352                             SmallVectorImpl<MCParsedAsmOperand*> &Operands,
353                             MCStreamer &Out, unsigned &ErrorInfo,
354                             bool MatchingInlineAsm) LLVM_OVERRIDE;
355 
356   // Used by the TableGen code to parse particular operand types.
357   OperandMatchResultTy
358   parseGR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
359     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
360   }
361   OperandMatchResultTy
362   parseGRH32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
363     return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
364   }
365   OperandMatchResultTy
366   parseGRX32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
367     llvm_unreachable("GRX32 should only be used for pseudo instructions");
368   }
369   OperandMatchResultTy
370   parseGR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
371     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
372   }
373   OperandMatchResultTy
374   parseGR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
375     return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
376   }
377   OperandMatchResultTy
378   parseADDR32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
379     return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
380   }
381   OperandMatchResultTy
382   parseADDR64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
383     return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
384   }
385   OperandMatchResultTy
386   parseADDR128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
387     llvm_unreachable("Shouldn't be used as an operand");
388   }
389   OperandMatchResultTy
390   parseFP32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
391     return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
392   }
393   OperandMatchResultTy
394   parseFP64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
395     return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
396   }
397   OperandMatchResultTy
398   parseFP128(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
399     return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
400   }
401   OperandMatchResultTy
402   parseBDAddr32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
403     return parseAddress(Operands, SystemZMC::GR32Regs, ADDR32Reg, BDMem);
404   }
405   OperandMatchResultTy
406   parseBDAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
407     return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDMem);
408   }
409   OperandMatchResultTy
410   parseBDXAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
411     return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDXMem);
412   }
413   OperandMatchResultTy
414   parseBDLAddr64(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
415     return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDLMem);
416   }
417   OperandMatchResultTy
418   parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
419   OperandMatchResultTy
420   parsePCRel(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
421              int64_t MinVal, int64_t MaxVal);
422   OperandMatchResultTy
423   parsePCRel16(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
424     return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1);
425   }
426   OperandMatchResultTy
427   parsePCRel32(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
428     return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1);
429   }
430 };
431 }
432 
433 #define GET_REGISTER_MATCHER
434 #define GET_SUBTARGET_FEATURE_NAME
435 #define GET_MATCHER_IMPLEMENTATION
436 #include "SystemZGenAsmMatcher.inc"
437 
438 void SystemZOperand::print(raw_ostream &OS) const {
439   llvm_unreachable("Not implemented");
440 }
441 
442 // Parse one register of the form %<prefix><number>.
443 bool SystemZAsmParser::parseRegister(Register &Reg) {
444   Reg.StartLoc = Parser.getTok().getLoc();
445 
446   // Eat the % prefix.
447   if (Parser.getTok().isNot(AsmToken::Percent))
448     return Error(Parser.getTok().getLoc(), "register expected");
449   Parser.Lex();
450 
451   // Expect a register name.
452   if (Parser.getTok().isNot(AsmToken::Identifier))
453     return Error(Reg.StartLoc, "invalid register");
454 
455   // Check that there's a prefix.
456   StringRef Name = Parser.getTok().getString();
457   if (Name.size() < 2)
458     return Error(Reg.StartLoc, "invalid register");
459   char Prefix = Name[0];
460 
461   // Treat the rest of the register name as a register number.
462   if (Name.substr(1).getAsInteger(10, Reg.Num))
463     return Error(Reg.StartLoc, "invalid register");
464 
465   // Look for valid combinations of prefix and number.
466   if (Prefix == 'r' && Reg.Num < 16)
467     Reg.Group = RegGR;
468   else if (Prefix == 'f' && Reg.Num < 16)
469     Reg.Group = RegFP;
470   else if (Prefix == 'a' && Reg.Num < 16)
471     Reg.Group = RegAccess;
472   else
473     return Error(Reg.StartLoc, "invalid register");
474 
475   Reg.EndLoc = Parser.getTok().getLoc();
476   Parser.Lex();
477   return false;
478 }
479 
480 // Parse a register of group Group.  If Regs is nonnull, use it to map
481 // the raw register number to LLVM numbering, with zero entries indicating
482 // an invalid register.  IsAddress says whether the register appears in an
483 // address context.
484 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
485                                      const unsigned *Regs, bool IsAddress) {
486   if (parseRegister(Reg))
487     return true;
488   if (Reg.Group != Group)
489     return Error(Reg.StartLoc, "invalid operand for instruction");
490   if (Regs && Regs[Reg.Num] == 0)
491     return Error(Reg.StartLoc, "invalid register pair");
492   if (Reg.Num == 0 && IsAddress)
493     return Error(Reg.StartLoc, "%r0 used in an address");
494   if (Regs)
495     Reg.Num = Regs[Reg.Num];
496   return false;
497 }
498 
499 // Parse a register and add it to Operands.  The other arguments are as above.
500 SystemZAsmParser::OperandMatchResultTy
501 SystemZAsmParser::parseRegister(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
502                                 RegisterGroup Group, const unsigned *Regs,
503                                 RegisterKind Kind) {
504   if (Parser.getTok().isNot(AsmToken::Percent))
505     return MatchOperand_NoMatch;
506 
507   Register Reg;
508   bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
509   if (parseRegister(Reg, Group, Regs, IsAddress))
510     return MatchOperand_ParseFail;
511 
512   Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
513                                                Reg.StartLoc, Reg.EndLoc));
514   return MatchOperand_Success;
515 }
516 
517 // Parse a memory operand into Base, Disp, Index and Length.
518 // Regs maps asm register numbers to LLVM register numbers and RegKind
519 // says what kind of address register we're using (ADDR32Reg or ADDR64Reg).
520 bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
521                                     unsigned &Index, const MCExpr *&Length,
522                                     const unsigned *Regs,
523                                     RegisterKind RegKind) {
524   // Parse the displacement, which must always be present.
525   if (getParser().parseExpression(Disp))
526     return true;
527 
528   // Parse the optional base and index.
529   Index = 0;
530   Base = 0;
531   Length = 0;
532   if (getLexer().is(AsmToken::LParen)) {
533     Parser.Lex();
534 
535     if (getLexer().is(AsmToken::Percent)) {
536       // Parse the first register and decide whether it's a base or an index.
537       Register Reg;
538       if (parseRegister(Reg, RegGR, Regs, RegKind))
539         return true;
540       if (getLexer().is(AsmToken::Comma))
541         Index = Reg.Num;
542       else
543         Base = Reg.Num;
544     } else {
545       // Parse the length.
546       if (getParser().parseExpression(Length))
547         return true;
548     }
549 
550     // Check whether there's a second register.  It's the base if so.
551     if (getLexer().is(AsmToken::Comma)) {
552       Parser.Lex();
553       Register Reg;
554       if (parseRegister(Reg, RegGR, Regs, RegKind))
555         return true;
556       Base = Reg.Num;
557     }
558 
559     // Consume the closing bracket.
560     if (getLexer().isNot(AsmToken::RParen))
561       return Error(Parser.getTok().getLoc(), "unexpected token in address");
562     Parser.Lex();
563   }
564   return false;
565 }
566 
567 // Parse a memory operand and add it to Operands.  The other arguments
568 // are as above.
569 SystemZAsmParser::OperandMatchResultTy
570 SystemZAsmParser::parseAddress(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
571                                const unsigned *Regs, RegisterKind RegKind,
572                                MemoryKind MemKind) {
573   SMLoc StartLoc = Parser.getTok().getLoc();
574   unsigned Base, Index;
575   const MCExpr *Disp;
576   const MCExpr *Length;
577   if (parseAddress(Base, Disp, Index, Length, Regs, RegKind))
578     return MatchOperand_ParseFail;
579 
580   if (Index && MemKind != BDXMem)
581     {
582       Error(StartLoc, "invalid use of indexed addressing");
583       return MatchOperand_ParseFail;
584     }
585 
586   if (Length && MemKind != BDLMem)
587     {
588       Error(StartLoc, "invalid use of length addressing");
589       return MatchOperand_ParseFail;
590     }
591 
592   if (!Length && MemKind == BDLMem)
593     {
594       Error(StartLoc, "missing length in address");
595       return MatchOperand_ParseFail;
596     }
597 
598   SMLoc EndLoc =
599     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
600   Operands.push_back(SystemZOperand::createMem(RegKind, Base, Disp, Index,
601                                                Length, StartLoc, EndLoc));
602   return MatchOperand_Success;
603 }
604 
605 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
606   return true;
607 }
608 
609 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
610                                      SMLoc &EndLoc) {
611   Register Reg;
612   if (parseRegister(Reg))
613     return true;
614   if (Reg.Group == RegGR)
615     RegNo = SystemZMC::GR64Regs[Reg.Num];
616   else if (Reg.Group == RegFP)
617     RegNo = SystemZMC::FP64Regs[Reg.Num];
618   else
619     // FIXME: Access registers aren't modelled as LLVM registers yet.
620     return Error(Reg.StartLoc, "invalid operand for instruction");
621   StartLoc = Reg.StartLoc;
622   EndLoc = Reg.EndLoc;
623   return false;
624 }
625 
626 bool SystemZAsmParser::
627 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
628                  SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
629   Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
630 
631   // Read the remaining operands.
632   if (getLexer().isNot(AsmToken::EndOfStatement)) {
633     // Read the first operand.
634     if (parseOperand(Operands, Name)) {
635       Parser.eatToEndOfStatement();
636       return true;
637     }
638 
639     // Read any subsequent operands.
640     while (getLexer().is(AsmToken::Comma)) {
641       Parser.Lex();
642       if (parseOperand(Operands, Name)) {
643         Parser.eatToEndOfStatement();
644         return true;
645       }
646     }
647     if (getLexer().isNot(AsmToken::EndOfStatement)) {
648       SMLoc Loc = getLexer().getLoc();
649       Parser.eatToEndOfStatement();
650       return Error(Loc, "unexpected token in argument list");
651     }
652   }
653 
654   // Consume the EndOfStatement.
655   Parser.Lex();
656   return false;
657 }
658 
659 bool SystemZAsmParser::
660 parseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
661              StringRef Mnemonic) {
662   // Check if the current operand has a custom associated parser, if so, try to
663   // custom parse the operand, or fallback to the general approach.
664   OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
665   if (ResTy == MatchOperand_Success)
666     return false;
667 
668   // If there wasn't a custom match, try the generic matcher below. Otherwise,
669   // there was a match, but an error occurred, in which case, just return that
670   // the operand parsing failed.
671   if (ResTy == MatchOperand_ParseFail)
672     return true;
673 
674   // Check for a register.  All real register operands should have used
675   // a context-dependent parse routine, which gives the required register
676   // class.  The code is here to mop up other cases, like those where
677   // the instruction isn't recognized.
678   if (Parser.getTok().is(AsmToken::Percent)) {
679     Register Reg;
680     if (parseRegister(Reg))
681       return true;
682     Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
683     return false;
684   }
685 
686   // The only other type of operand is an immediate or address.  As above,
687   // real address operands should have used a context-dependent parse routine,
688   // so we treat any plain expression as an immediate.
689   SMLoc StartLoc = Parser.getTok().getLoc();
690   unsigned Base, Index;
691   const MCExpr *Expr, *Length;
692   if (parseAddress(Base, Expr, Index, Length, SystemZMC::GR64Regs, ADDR64Reg))
693     return true;
694 
695   SMLoc EndLoc =
696     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
697   if (Base || Index || Length)
698     Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
699   else
700     Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
701   return false;
702 }
703 
704 bool SystemZAsmParser::
705 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
706                         SmallVectorImpl<MCParsedAsmOperand*> &Operands,
707                         MCStreamer &Out, unsigned &ErrorInfo,
708                         bool MatchingInlineAsm) {
709   MCInst Inst;
710   unsigned MatchResult;
711 
712   MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
713                                      MatchingInlineAsm);
714   switch (MatchResult) {
715   default: break;
716   case Match_Success:
717     Inst.setLoc(IDLoc);
718     Out.EmitInstruction(Inst, STI);
719     return false;
720 
721   case Match_MissingFeature: {
722     assert(ErrorInfo && "Unknown missing feature!");
723     // Special case the error message for the very common case where only
724     // a single subtarget feature is missing
725     std::string Msg = "instruction requires:";
726     unsigned Mask = 1;
727     for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
728       if (ErrorInfo & Mask) {
729         Msg += " ";
730         Msg += getSubtargetFeatureName(ErrorInfo & Mask);
731       }
732       Mask <<= 1;
733     }
734     return Error(IDLoc, Msg);
735   }
736 
737   case Match_InvalidOperand: {
738     SMLoc ErrorLoc = IDLoc;
739     if (ErrorInfo != ~0U) {
740       if (ErrorInfo >= Operands.size())
741         return Error(IDLoc, "too few operands for instruction");
742 
743       ErrorLoc = ((SystemZOperand*)Operands[ErrorInfo])->getStartLoc();
744       if (ErrorLoc == SMLoc())
745         ErrorLoc = IDLoc;
746     }
747     return Error(ErrorLoc, "invalid operand for instruction");
748   }
749 
750   case Match_MnemonicFail:
751     return Error(IDLoc, "invalid instruction");
752   }
753 
754   llvm_unreachable("Unexpected match type");
755 }
756 
757 SystemZAsmParser::OperandMatchResultTy SystemZAsmParser::
758 parseAccessReg(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
759   if (Parser.getTok().isNot(AsmToken::Percent))
760     return MatchOperand_NoMatch;
761 
762   Register Reg;
763   if (parseRegister(Reg, RegAccess, 0))
764     return MatchOperand_ParseFail;
765 
766   Operands.push_back(SystemZOperand::createAccessReg(Reg.Num,
767                                                      Reg.StartLoc,
768                                                      Reg.EndLoc));
769   return MatchOperand_Success;
770 }
771 
772 SystemZAsmParser::OperandMatchResultTy SystemZAsmParser::
773 parsePCRel(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
774            int64_t MinVal, int64_t MaxVal) {
775   MCContext &Ctx = getContext();
776   MCStreamer &Out = getStreamer();
777   const MCExpr *Expr;
778   SMLoc StartLoc = Parser.getTok().getLoc();
779   if (getParser().parseExpression(Expr))
780     return MatchOperand_NoMatch;
781 
782   // For consistency with the GNU assembler, treat immediates as offsets
783   // from ".".
784   if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr)) {
785     int64_t Value = CE->getValue();
786     if ((Value & 1) || Value < MinVal || Value > MaxVal) {
787       Error(StartLoc, "offset out of range");
788       return MatchOperand_ParseFail;
789     }
790     MCSymbol *Sym = Ctx.CreateTempSymbol();
791     Out.EmitLabel(Sym);
792     const MCExpr *Base = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
793                                                  Ctx);
794     Expr = Value == 0 ? Base : MCBinaryExpr::CreateAdd(Base, Expr, Ctx);
795   }
796 
797   SMLoc EndLoc =
798     SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
799   Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
800   return MatchOperand_Success;
801 }
802 
803 // Force static initialization.
804 extern "C" void LLVMInitializeSystemZAsmParser() {
805   RegisterMCAsmParser<SystemZAsmParser> X(TheSystemZTarget);
806 }
807