1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/SystemZInstPrinter.h" 10 #include "MCTargetDesc/SystemZMCTargetDesc.h" 11 #include "TargetInfo/SystemZTargetInfo.h" 12 #include "llvm/ADT/STLExtras.h" 13 #include "llvm/ADT/SmallVector.h" 14 #include "llvm/ADT/StringRef.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCExpr.h" 17 #include "llvm/MC/MCInst.h" 18 #include "llvm/MC/MCInstBuilder.h" 19 #include "llvm/MC/MCParser/MCAsmLexer.h" 20 #include "llvm/MC/MCParser/MCAsmParser.h" 21 #include "llvm/MC/MCParser/MCAsmParserExtension.h" 22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 23 #include "llvm/MC/MCParser/MCTargetAsmParser.h" 24 #include "llvm/MC/MCStreamer.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/Support/Casting.h" 27 #include "llvm/Support/ErrorHandling.h" 28 #include "llvm/Support/SMLoc.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include <algorithm> 31 #include <cassert> 32 #include <cstddef> 33 #include <cstdint> 34 #include <iterator> 35 #include <memory> 36 #include <string> 37 38 using namespace llvm; 39 40 // Return true if Expr is in the range [MinValue, MaxValue]. 41 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) { 42 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) { 43 int64_t Value = CE->getValue(); 44 return Value >= MinValue && Value <= MaxValue; 45 } 46 return false; 47 } 48 49 namespace { 50 51 enum RegisterKind { 52 GR32Reg, 53 GRH32Reg, 54 GR64Reg, 55 GR128Reg, 56 FP32Reg, 57 FP64Reg, 58 FP128Reg, 59 VR32Reg, 60 VR64Reg, 61 VR128Reg, 62 AR32Reg, 63 CR64Reg, 64 }; 65 66 enum MemoryKind { 67 BDMem, 68 BDXMem, 69 BDLMem, 70 BDRMem, 71 BDVMem 72 }; 73 74 class SystemZOperand : public MCParsedAsmOperand { 75 private: 76 enum OperandKind { 77 KindInvalid, 78 KindToken, 79 KindReg, 80 KindImm, 81 KindImmTLS, 82 KindMem 83 }; 84 85 OperandKind Kind; 86 SMLoc StartLoc, EndLoc; 87 88 // A string of length Length, starting at Data. 89 struct TokenOp { 90 const char *Data; 91 unsigned Length; 92 }; 93 94 // LLVM register Num, which has kind Kind. In some ways it might be 95 // easier for this class to have a register bank (general, floating-point 96 // or access) and a raw register number (0-15). This would postpone the 97 // interpretation of the operand to the add*() methods and avoid the need 98 // for context-dependent parsing. However, we do things the current way 99 // because of the virtual getReg() method, which needs to distinguish 100 // between (say) %r0 used as a single register and %r0 used as a pair. 101 // Context-dependent parsing can also give us slightly better error 102 // messages when invalid pairs like %r1 are used. 103 struct RegOp { 104 RegisterKind Kind; 105 unsigned Num; 106 }; 107 108 // Base + Disp + Index, where Base and Index are LLVM registers or 0. 109 // MemKind says what type of memory this is and RegKind says what type 110 // the base register has (GR32Reg or GR64Reg). Length is the operand 111 // length for D(L,B)-style operands, otherwise it is null. 112 struct MemOp { 113 unsigned Base : 12; 114 unsigned Index : 12; 115 unsigned MemKind : 4; 116 unsigned RegKind : 4; 117 const MCExpr *Disp; 118 union { 119 const MCExpr *Imm; 120 unsigned Reg; 121 } Length; 122 }; 123 124 // Imm is an immediate operand, and Sym is an optional TLS symbol 125 // for use with a __tls_get_offset marker relocation. 126 struct ImmTLSOp { 127 const MCExpr *Imm; 128 const MCExpr *Sym; 129 }; 130 131 union { 132 TokenOp Token; 133 RegOp Reg; 134 const MCExpr *Imm; 135 ImmTLSOp ImmTLS; 136 MemOp Mem; 137 }; 138 139 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 140 // Add as immediates when possible. Null MCExpr = 0. 141 if (!Expr) 142 Inst.addOperand(MCOperand::createImm(0)); 143 else if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) 144 Inst.addOperand(MCOperand::createImm(CE->getValue())); 145 else 146 Inst.addOperand(MCOperand::createExpr(Expr)); 147 } 148 149 public: 150 SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc) 151 : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {} 152 153 // Create particular kinds of operand. 154 static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc, 155 SMLoc EndLoc) { 156 return std::make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc); 157 } 158 159 static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) { 160 auto Op = std::make_unique<SystemZOperand>(KindToken, Loc, Loc); 161 Op->Token.Data = Str.data(); 162 Op->Token.Length = Str.size(); 163 return Op; 164 } 165 166 static std::unique_ptr<SystemZOperand> 167 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) { 168 auto Op = std::make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc); 169 Op->Reg.Kind = Kind; 170 Op->Reg.Num = Num; 171 return Op; 172 } 173 174 static std::unique_ptr<SystemZOperand> 175 createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) { 176 auto Op = std::make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc); 177 Op->Imm = Expr; 178 return Op; 179 } 180 181 static std::unique_ptr<SystemZOperand> 182 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base, 183 const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm, 184 unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) { 185 auto Op = std::make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc); 186 Op->Mem.MemKind = MemKind; 187 Op->Mem.RegKind = RegKind; 188 Op->Mem.Base = Base; 189 Op->Mem.Index = Index; 190 Op->Mem.Disp = Disp; 191 if (MemKind == BDLMem) 192 Op->Mem.Length.Imm = LengthImm; 193 if (MemKind == BDRMem) 194 Op->Mem.Length.Reg = LengthReg; 195 return Op; 196 } 197 198 static std::unique_ptr<SystemZOperand> 199 createImmTLS(const MCExpr *Imm, const MCExpr *Sym, 200 SMLoc StartLoc, SMLoc EndLoc) { 201 auto Op = std::make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc); 202 Op->ImmTLS.Imm = Imm; 203 Op->ImmTLS.Sym = Sym; 204 return Op; 205 } 206 207 // Token operands 208 bool isToken() const override { 209 return Kind == KindToken; 210 } 211 StringRef getToken() const { 212 assert(Kind == KindToken && "Not a token"); 213 return StringRef(Token.Data, Token.Length); 214 } 215 216 // Register operands. 217 bool isReg() const override { 218 return Kind == KindReg; 219 } 220 bool isReg(RegisterKind RegKind) const { 221 return Kind == KindReg && Reg.Kind == RegKind; 222 } 223 unsigned getReg() const override { 224 assert(Kind == KindReg && "Not a register"); 225 return Reg.Num; 226 } 227 228 // Immediate operands. 229 bool isImm() const override { 230 return Kind == KindImm; 231 } 232 bool isImm(int64_t MinValue, int64_t MaxValue) const { 233 return Kind == KindImm && inRange(Imm, MinValue, MaxValue); 234 } 235 const MCExpr *getImm() const { 236 assert(Kind == KindImm && "Not an immediate"); 237 return Imm; 238 } 239 240 // Immediate operands with optional TLS symbol. 241 bool isImmTLS() const { 242 return Kind == KindImmTLS; 243 } 244 245 const ImmTLSOp getImmTLS() const { 246 assert(Kind == KindImmTLS && "Not a TLS immediate"); 247 return ImmTLS; 248 } 249 250 // Memory operands. 251 bool isMem() const override { 252 return Kind == KindMem; 253 } 254 bool isMem(MemoryKind MemKind) const { 255 return (Kind == KindMem && 256 (Mem.MemKind == MemKind || 257 // A BDMem can be treated as a BDXMem in which the index 258 // register field is 0. 259 (Mem.MemKind == BDMem && MemKind == BDXMem))); 260 } 261 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { 262 return isMem(MemKind) && Mem.RegKind == RegKind; 263 } 264 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const { 265 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff); 266 } 267 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const { 268 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287); 269 } 270 bool isMemDisp12Len4(RegisterKind RegKind) const { 271 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10); 272 } 273 bool isMemDisp12Len8(RegisterKind RegKind) const { 274 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100); 275 } 276 277 const MemOp& getMem() const { 278 assert(Kind == KindMem && "Not a Mem operand"); 279 return Mem; 280 } 281 282 // Override MCParsedAsmOperand. 283 SMLoc getStartLoc() const override { return StartLoc; } 284 SMLoc getEndLoc() const override { return EndLoc; } 285 void print(raw_ostream &OS) const override; 286 287 /// getLocRange - Get the range between the first and last token of this 288 /// operand. 289 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 290 291 // Used by the TableGen code to add particular types of operand 292 // to an instruction. 293 void addRegOperands(MCInst &Inst, unsigned N) const { 294 assert(N == 1 && "Invalid number of operands"); 295 Inst.addOperand(MCOperand::createReg(getReg())); 296 } 297 void addImmOperands(MCInst &Inst, unsigned N) const { 298 assert(N == 1 && "Invalid number of operands"); 299 addExpr(Inst, getImm()); 300 } 301 void addBDAddrOperands(MCInst &Inst, unsigned N) const { 302 assert(N == 2 && "Invalid number of operands"); 303 assert(isMem(BDMem) && "Invalid operand type"); 304 Inst.addOperand(MCOperand::createReg(Mem.Base)); 305 addExpr(Inst, Mem.Disp); 306 } 307 void addBDXAddrOperands(MCInst &Inst, unsigned N) const { 308 assert(N == 3 && "Invalid number of operands"); 309 assert(isMem(BDXMem) && "Invalid operand type"); 310 Inst.addOperand(MCOperand::createReg(Mem.Base)); 311 addExpr(Inst, Mem.Disp); 312 Inst.addOperand(MCOperand::createReg(Mem.Index)); 313 } 314 void addBDLAddrOperands(MCInst &Inst, unsigned N) const { 315 assert(N == 3 && "Invalid number of operands"); 316 assert(isMem(BDLMem) && "Invalid operand type"); 317 Inst.addOperand(MCOperand::createReg(Mem.Base)); 318 addExpr(Inst, Mem.Disp); 319 addExpr(Inst, Mem.Length.Imm); 320 } 321 void addBDRAddrOperands(MCInst &Inst, unsigned N) const { 322 assert(N == 3 && "Invalid number of operands"); 323 assert(isMem(BDRMem) && "Invalid operand type"); 324 Inst.addOperand(MCOperand::createReg(Mem.Base)); 325 addExpr(Inst, Mem.Disp); 326 Inst.addOperand(MCOperand::createReg(Mem.Length.Reg)); 327 } 328 void addBDVAddrOperands(MCInst &Inst, unsigned N) const { 329 assert(N == 3 && "Invalid number of operands"); 330 assert(isMem(BDVMem) && "Invalid operand type"); 331 Inst.addOperand(MCOperand::createReg(Mem.Base)); 332 addExpr(Inst, Mem.Disp); 333 Inst.addOperand(MCOperand::createReg(Mem.Index)); 334 } 335 void addImmTLSOperands(MCInst &Inst, unsigned N) const { 336 assert(N == 2 && "Invalid number of operands"); 337 assert(Kind == KindImmTLS && "Invalid operand type"); 338 addExpr(Inst, ImmTLS.Imm); 339 if (ImmTLS.Sym) 340 addExpr(Inst, ImmTLS.Sym); 341 } 342 343 // Used by the TableGen code to check for particular operand types. 344 bool isGR32() const { return isReg(GR32Reg); } 345 bool isGRH32() const { return isReg(GRH32Reg); } 346 bool isGRX32() const { return false; } 347 bool isGR64() const { return isReg(GR64Reg); } 348 bool isGR128() const { return isReg(GR128Reg); } 349 bool isADDR32() const { return isReg(GR32Reg); } 350 bool isADDR64() const { return isReg(GR64Reg); } 351 bool isADDR128() const { return false; } 352 bool isFP32() const { return isReg(FP32Reg); } 353 bool isFP64() const { return isReg(FP64Reg); } 354 bool isFP128() const { return isReg(FP128Reg); } 355 bool isVR32() const { return isReg(VR32Reg); } 356 bool isVR64() const { return isReg(VR64Reg); } 357 bool isVF128() const { return false; } 358 bool isVR128() const { return isReg(VR128Reg); } 359 bool isAR32() const { return isReg(AR32Reg); } 360 bool isCR64() const { return isReg(CR64Reg); } 361 bool isAnyReg() const { return (isReg() || isImm(0, 15)); } 362 bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, GR32Reg); } 363 bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, GR32Reg); } 364 bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, GR64Reg); } 365 bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, GR64Reg); } 366 bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, GR64Reg); } 367 bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, GR64Reg); } 368 bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(GR64Reg); } 369 bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(GR64Reg); } 370 bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, GR64Reg); } 371 bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, GR64Reg); } 372 bool isU1Imm() const { return isImm(0, 1); } 373 bool isU2Imm() const { return isImm(0, 3); } 374 bool isU3Imm() const { return isImm(0, 7); } 375 bool isU4Imm() const { return isImm(0, 15); } 376 bool isU6Imm() const { return isImm(0, 63); } 377 bool isU8Imm() const { return isImm(0, 255); } 378 bool isS8Imm() const { return isImm(-128, 127); } 379 bool isU12Imm() const { return isImm(0, 4095); } 380 bool isU16Imm() const { return isImm(0, 65535); } 381 bool isS16Imm() const { return isImm(-32768, 32767); } 382 bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); } 383 bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); } 384 bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); } 385 }; 386 387 class SystemZAsmParser : public MCTargetAsmParser { 388 #define GET_ASSEMBLER_HEADER 389 #include "SystemZGenAsmMatcher.inc" 390 391 private: 392 MCAsmParser &Parser; 393 enum RegisterGroup { 394 RegGR, 395 RegFP, 396 RegV, 397 RegAR, 398 RegCR 399 }; 400 struct Register { 401 RegisterGroup Group; 402 unsigned Num; 403 SMLoc StartLoc, EndLoc; 404 }; 405 406 bool parseRegister(Register &Reg, bool RestoreOnFailure = false); 407 408 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs); 409 410 OperandMatchResultTy parseRegister(OperandVector &Operands, 411 RegisterGroup Group, const unsigned *Regs, 412 RegisterKind Kind); 413 414 OperandMatchResultTy parseAnyRegister(OperandVector &Operands); 415 416 bool parseAddress(bool &HaveReg1, Register &Reg1, 417 bool &HaveReg2, Register &Reg2, 418 const MCExpr *&Disp, const MCExpr *&Length); 419 bool parseAddressRegister(Register &Reg); 420 421 bool ParseDirectiveInsn(SMLoc L); 422 423 OperandMatchResultTy parseAddress(OperandVector &Operands, 424 MemoryKind MemKind, const unsigned *Regs, 425 RegisterKind RegKind); 426 427 OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal, 428 int64_t MaxVal, bool AllowTLS); 429 430 bool parseOperand(OperandVector &Operands, StringRef Mnemonic); 431 432 public: 433 SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser, 434 const MCInstrInfo &MII, 435 const MCTargetOptions &Options) 436 : MCTargetAsmParser(Options, sti, MII), Parser(parser) { 437 MCAsmParserExtension::Initialize(Parser); 438 439 // Alias the .word directive to .short. 440 parser.addAliasForDirective(".word", ".short"); 441 442 // Initialize the set of available features. 443 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); 444 } 445 446 // Override MCTargetAsmParser. 447 bool ParseDirective(AsmToken DirectiveID) override; 448 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 449 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc, 450 bool RestoreOnFailure); 451 OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, 452 SMLoc &EndLoc) override; 453 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 454 SMLoc NameLoc, OperandVector &Operands) override; 455 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 456 OperandVector &Operands, MCStreamer &Out, 457 uint64_t &ErrorInfo, 458 bool MatchingInlineAsm) override; 459 460 // Used by the TableGen code to parse particular operand types. 461 OperandMatchResultTy parseGR32(OperandVector &Operands) { 462 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg); 463 } 464 OperandMatchResultTy parseGRH32(OperandVector &Operands) { 465 return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg); 466 } 467 OperandMatchResultTy parseGRX32(OperandVector &Operands) { 468 llvm_unreachable("GRX32 should only be used for pseudo instructions"); 469 } 470 OperandMatchResultTy parseGR64(OperandVector &Operands) { 471 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg); 472 } 473 OperandMatchResultTy parseGR128(OperandVector &Operands) { 474 return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg); 475 } 476 OperandMatchResultTy parseADDR32(OperandVector &Operands) { 477 // For the AsmParser, we will accept %r0 for ADDR32 as well. 478 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg); 479 } 480 OperandMatchResultTy parseADDR64(OperandVector &Operands) { 481 // For the AsmParser, we will accept %r0 for ADDR64 as well. 482 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg); 483 } 484 OperandMatchResultTy parseADDR128(OperandVector &Operands) { 485 llvm_unreachable("Shouldn't be used as an operand"); 486 } 487 OperandMatchResultTy parseFP32(OperandVector &Operands) { 488 return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg); 489 } 490 OperandMatchResultTy parseFP64(OperandVector &Operands) { 491 return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg); 492 } 493 OperandMatchResultTy parseFP128(OperandVector &Operands) { 494 return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg); 495 } 496 OperandMatchResultTy parseVR32(OperandVector &Operands) { 497 return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg); 498 } 499 OperandMatchResultTy parseVR64(OperandVector &Operands) { 500 return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg); 501 } 502 OperandMatchResultTy parseVF128(OperandVector &Operands) { 503 llvm_unreachable("Shouldn't be used as an operand"); 504 } 505 OperandMatchResultTy parseVR128(OperandVector &Operands) { 506 return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg); 507 } 508 OperandMatchResultTy parseAR32(OperandVector &Operands) { 509 return parseRegister(Operands, RegAR, SystemZMC::AR32Regs, AR32Reg); 510 } 511 OperandMatchResultTy parseCR64(OperandVector &Operands) { 512 return parseRegister(Operands, RegCR, SystemZMC::CR64Regs, CR64Reg); 513 } 514 OperandMatchResultTy parseAnyReg(OperandVector &Operands) { 515 return parseAnyRegister(Operands); 516 } 517 OperandMatchResultTy parseBDAddr32(OperandVector &Operands) { 518 return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, GR32Reg); 519 } 520 OperandMatchResultTy parseBDAddr64(OperandVector &Operands) { 521 return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, GR64Reg); 522 } 523 OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) { 524 return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, GR64Reg); 525 } 526 OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) { 527 return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, GR64Reg); 528 } 529 OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) { 530 return parseAddress(Operands, BDRMem, SystemZMC::GR64Regs, GR64Reg); 531 } 532 OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) { 533 return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, GR64Reg); 534 } 535 OperandMatchResultTy parsePCRel12(OperandVector &Operands) { 536 return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false); 537 } 538 OperandMatchResultTy parsePCRel16(OperandVector &Operands) { 539 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false); 540 } 541 OperandMatchResultTy parsePCRel24(OperandVector &Operands) { 542 return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false); 543 } 544 OperandMatchResultTy parsePCRel32(OperandVector &Operands) { 545 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false); 546 } 547 OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) { 548 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true); 549 } 550 OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) { 551 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true); 552 } 553 }; 554 555 } // end anonymous namespace 556 557 #define GET_REGISTER_MATCHER 558 #define GET_SUBTARGET_FEATURE_NAME 559 #define GET_MATCHER_IMPLEMENTATION 560 #define GET_MNEMONIC_SPELL_CHECKER 561 #include "SystemZGenAsmMatcher.inc" 562 563 // Used for the .insn directives; contains information needed to parse the 564 // operands in the directive. 565 struct InsnMatchEntry { 566 StringRef Format; 567 uint64_t Opcode; 568 int32_t NumOperands; 569 MatchClassKind OperandKinds[5]; 570 }; 571 572 // For equal_range comparison. 573 struct CompareInsn { 574 bool operator() (const InsnMatchEntry &LHS, StringRef RHS) { 575 return LHS.Format < RHS; 576 } 577 bool operator() (StringRef LHS, const InsnMatchEntry &RHS) { 578 return LHS < RHS.Format; 579 } 580 bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) { 581 return LHS.Format < RHS.Format; 582 } 583 }; 584 585 // Table initializing information for parsing the .insn directive. 586 static struct InsnMatchEntry InsnMatchTable[] = { 587 /* Format, Opcode, NumOperands, OperandKinds */ 588 { "e", SystemZ::InsnE, 1, 589 { MCK_U16Imm } }, 590 { "ri", SystemZ::InsnRI, 3, 591 { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } }, 592 { "rie", SystemZ::InsnRIE, 4, 593 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } }, 594 { "ril", SystemZ::InsnRIL, 3, 595 { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } }, 596 { "rilu", SystemZ::InsnRILU, 3, 597 { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } }, 598 { "ris", SystemZ::InsnRIS, 5, 599 { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } }, 600 { "rr", SystemZ::InsnRR, 3, 601 { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } }, 602 { "rre", SystemZ::InsnRRE, 3, 603 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } }, 604 { "rrf", SystemZ::InsnRRF, 5, 605 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } }, 606 { "rrs", SystemZ::InsnRRS, 5, 607 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } }, 608 { "rs", SystemZ::InsnRS, 4, 609 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } }, 610 { "rse", SystemZ::InsnRSE, 4, 611 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } }, 612 { "rsi", SystemZ::InsnRSI, 4, 613 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } }, 614 { "rsy", SystemZ::InsnRSY, 4, 615 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } }, 616 { "rx", SystemZ::InsnRX, 3, 617 { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } }, 618 { "rxe", SystemZ::InsnRXE, 3, 619 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } }, 620 { "rxf", SystemZ::InsnRXF, 4, 621 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } }, 622 { "rxy", SystemZ::InsnRXY, 3, 623 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } }, 624 { "s", SystemZ::InsnS, 2, 625 { MCK_U32Imm, MCK_BDAddr64Disp12 } }, 626 { "si", SystemZ::InsnSI, 3, 627 { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } }, 628 { "sil", SystemZ::InsnSIL, 3, 629 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } }, 630 { "siy", SystemZ::InsnSIY, 3, 631 { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } }, 632 { "ss", SystemZ::InsnSS, 4, 633 { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }, 634 { "sse", SystemZ::InsnSSE, 3, 635 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } }, 636 { "ssf", SystemZ::InsnSSF, 4, 637 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } } 638 }; 639 640 static void printMCExpr(const MCExpr *E, raw_ostream &OS) { 641 if (!E) 642 return; 643 if (auto *CE = dyn_cast<MCConstantExpr>(E)) 644 OS << *CE; 645 else if (auto *UE = dyn_cast<MCUnaryExpr>(E)) 646 OS << *UE; 647 else if (auto *BE = dyn_cast<MCBinaryExpr>(E)) 648 OS << *BE; 649 else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E)) 650 OS << *SRE; 651 else 652 OS << *E; 653 } 654 655 void SystemZOperand::print(raw_ostream &OS) const { 656 switch (Kind) { 657 case KindToken: 658 OS << "Token:" << getToken(); 659 break; 660 case KindReg: 661 OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg()); 662 break; 663 case KindImm: 664 OS << "Imm:"; 665 printMCExpr(getImm(), OS); 666 break; 667 case KindImmTLS: 668 OS << "ImmTLS:"; 669 printMCExpr(getImmTLS().Imm, OS); 670 if (getImmTLS().Sym) { 671 OS << ", "; 672 printMCExpr(getImmTLS().Sym, OS); 673 } 674 break; 675 case KindMem: { 676 const MemOp &Op = getMem(); 677 OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp); 678 if (Op.Base) { 679 OS << "("; 680 if (Op.MemKind == BDLMem) 681 OS << *cast<MCConstantExpr>(Op.Length.Imm) << ","; 682 else if (Op.MemKind == BDRMem) 683 OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ","; 684 if (Op.Index) 685 OS << SystemZInstPrinter::getRegisterName(Op.Index) << ","; 686 OS << SystemZInstPrinter::getRegisterName(Op.Base); 687 OS << ")"; 688 } 689 break; 690 } 691 case KindInvalid: 692 break; 693 } 694 } 695 696 // Parse one register of the form %<prefix><number>. 697 bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) { 698 Reg.StartLoc = Parser.getTok().getLoc(); 699 700 // Eat the % prefix. 701 if (Parser.getTok().isNot(AsmToken::Percent)) 702 return Error(Parser.getTok().getLoc(), "register expected"); 703 const AsmToken &PercentTok = Parser.getTok(); 704 Parser.Lex(); 705 706 // Expect a register name. 707 if (Parser.getTok().isNot(AsmToken::Identifier)) { 708 if (RestoreOnFailure) 709 getLexer().UnLex(PercentTok); 710 return Error(Reg.StartLoc, "invalid register"); 711 } 712 713 // Check that there's a prefix. 714 StringRef Name = Parser.getTok().getString(); 715 if (Name.size() < 2) { 716 if (RestoreOnFailure) 717 getLexer().UnLex(PercentTok); 718 return Error(Reg.StartLoc, "invalid register"); 719 } 720 char Prefix = Name[0]; 721 722 // Treat the rest of the register name as a register number. 723 if (Name.substr(1).getAsInteger(10, Reg.Num)) { 724 if (RestoreOnFailure) 725 getLexer().UnLex(PercentTok); 726 return Error(Reg.StartLoc, "invalid register"); 727 } 728 729 // Look for valid combinations of prefix and number. 730 if (Prefix == 'r' && Reg.Num < 16) 731 Reg.Group = RegGR; 732 else if (Prefix == 'f' && Reg.Num < 16) 733 Reg.Group = RegFP; 734 else if (Prefix == 'v' && Reg.Num < 32) 735 Reg.Group = RegV; 736 else if (Prefix == 'a' && Reg.Num < 16) 737 Reg.Group = RegAR; 738 else if (Prefix == 'c' && Reg.Num < 16) 739 Reg.Group = RegCR; 740 else { 741 if (RestoreOnFailure) 742 getLexer().UnLex(PercentTok); 743 return Error(Reg.StartLoc, "invalid register"); 744 } 745 746 Reg.EndLoc = Parser.getTok().getLoc(); 747 Parser.Lex(); 748 return false; 749 } 750 751 // Parse a register of group Group. If Regs is nonnull, use it to map 752 // the raw register number to LLVM numbering, with zero entries 753 // indicating an invalid register. Allow FP Group if expecting 754 // RegV Group, since the f-prefix yields the FP group even while used 755 // with vector instructions. 756 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group, 757 const unsigned *Regs) { 758 if (parseRegister(Reg)) 759 return true; 760 if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV)) 761 return Error(Reg.StartLoc, "invalid operand for instruction"); 762 if (Regs && Regs[Reg.Num] == 0) 763 return Error(Reg.StartLoc, "invalid register pair"); 764 if (Regs) 765 Reg.Num = Regs[Reg.Num]; 766 return false; 767 } 768 769 // Parse a register and add it to Operands. The other arguments are as above. 770 OperandMatchResultTy 771 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group, 772 const unsigned *Regs, RegisterKind Kind) { 773 if (Parser.getTok().isNot(AsmToken::Percent)) 774 return MatchOperand_NoMatch; 775 776 Register Reg; 777 if (parseRegister(Reg, Group, Regs)) 778 return MatchOperand_ParseFail; 779 780 Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num, 781 Reg.StartLoc, Reg.EndLoc)); 782 return MatchOperand_Success; 783 } 784 785 // Parse any type of register (including integers) and add it to Operands. 786 OperandMatchResultTy 787 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) { 788 // Handle integer values. 789 if (Parser.getTok().is(AsmToken::Integer)) { 790 const MCExpr *Register; 791 SMLoc StartLoc = Parser.getTok().getLoc(); 792 if (Parser.parseExpression(Register)) 793 return MatchOperand_ParseFail; 794 795 if (auto *CE = dyn_cast<MCConstantExpr>(Register)) { 796 int64_t Value = CE->getValue(); 797 if (Value < 0 || Value > 15) { 798 Error(StartLoc, "invalid register"); 799 return MatchOperand_ParseFail; 800 } 801 } 802 803 SMLoc EndLoc = 804 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 805 806 Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc)); 807 } 808 else { 809 Register Reg; 810 if (parseRegister(Reg)) 811 return MatchOperand_ParseFail; 812 813 // Map to the correct register kind. 814 RegisterKind Kind; 815 unsigned RegNo; 816 if (Reg.Group == RegGR) { 817 Kind = GR64Reg; 818 RegNo = SystemZMC::GR64Regs[Reg.Num]; 819 } 820 else if (Reg.Group == RegFP) { 821 Kind = FP64Reg; 822 RegNo = SystemZMC::FP64Regs[Reg.Num]; 823 } 824 else if (Reg.Group == RegV) { 825 Kind = VR128Reg; 826 RegNo = SystemZMC::VR128Regs[Reg.Num]; 827 } 828 else if (Reg.Group == RegAR) { 829 Kind = AR32Reg; 830 RegNo = SystemZMC::AR32Regs[Reg.Num]; 831 } 832 else if (Reg.Group == RegCR) { 833 Kind = CR64Reg; 834 RegNo = SystemZMC::CR64Regs[Reg.Num]; 835 } 836 else { 837 return MatchOperand_ParseFail; 838 } 839 840 Operands.push_back(SystemZOperand::createReg(Kind, RegNo, 841 Reg.StartLoc, Reg.EndLoc)); 842 } 843 return MatchOperand_Success; 844 } 845 846 // Parse a memory operand into Reg1, Reg2, Disp, and Length. 847 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1, 848 bool &HaveReg2, Register &Reg2, 849 const MCExpr *&Disp, 850 const MCExpr *&Length) { 851 // Parse the displacement, which must always be present. 852 if (getParser().parseExpression(Disp)) 853 return true; 854 855 // Parse the optional base and index. 856 HaveReg1 = false; 857 HaveReg2 = false; 858 Length = nullptr; 859 if (getLexer().is(AsmToken::LParen)) { 860 Parser.Lex(); 861 862 if (getLexer().is(AsmToken::Percent)) { 863 // Parse the first register. 864 HaveReg1 = true; 865 if (parseRegister(Reg1)) 866 return true; 867 } else { 868 // Parse the length. 869 if (getParser().parseExpression(Length)) 870 return true; 871 } 872 873 // Check whether there's a second register. 874 if (getLexer().is(AsmToken::Comma)) { 875 Parser.Lex(); 876 HaveReg2 = true; 877 if (parseRegister(Reg2)) 878 return true; 879 } 880 881 // Consume the closing bracket. 882 if (getLexer().isNot(AsmToken::RParen)) 883 return Error(Parser.getTok().getLoc(), "unexpected token in address"); 884 Parser.Lex(); 885 } 886 return false; 887 } 888 889 // Verify that Reg is a valid address register (base or index). 890 bool 891 SystemZAsmParser::parseAddressRegister(Register &Reg) { 892 if (Reg.Group == RegV) { 893 Error(Reg.StartLoc, "invalid use of vector addressing"); 894 return true; 895 } else if (Reg.Group != RegGR) { 896 Error(Reg.StartLoc, "invalid address register"); 897 return true; 898 } 899 return false; 900 } 901 902 // Parse a memory operand and add it to Operands. The other arguments 903 // are as above. 904 OperandMatchResultTy 905 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind, 906 const unsigned *Regs, RegisterKind RegKind) { 907 SMLoc StartLoc = Parser.getTok().getLoc(); 908 unsigned Base = 0, Index = 0, LengthReg = 0; 909 Register Reg1, Reg2; 910 bool HaveReg1, HaveReg2; 911 const MCExpr *Disp; 912 const MCExpr *Length; 913 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length)) 914 return MatchOperand_ParseFail; 915 916 switch (MemKind) { 917 case BDMem: 918 // If we have Reg1, it must be an address register. 919 if (HaveReg1) { 920 if (parseAddressRegister(Reg1)) 921 return MatchOperand_ParseFail; 922 Base = Regs[Reg1.Num]; 923 } 924 // There must be no Reg2 or length. 925 if (Length) { 926 Error(StartLoc, "invalid use of length addressing"); 927 return MatchOperand_ParseFail; 928 } 929 if (HaveReg2) { 930 Error(StartLoc, "invalid use of indexed addressing"); 931 return MatchOperand_ParseFail; 932 } 933 break; 934 case BDXMem: 935 // If we have Reg1, it must be an address register. 936 if (HaveReg1) { 937 if (parseAddressRegister(Reg1)) 938 return MatchOperand_ParseFail; 939 // If the are two registers, the first one is the index and the 940 // second is the base. 941 if (HaveReg2) 942 Index = Regs[Reg1.Num]; 943 else 944 Base = Regs[Reg1.Num]; 945 } 946 // If we have Reg2, it must be an address register. 947 if (HaveReg2) { 948 if (parseAddressRegister(Reg2)) 949 return MatchOperand_ParseFail; 950 Base = Regs[Reg2.Num]; 951 } 952 // There must be no length. 953 if (Length) { 954 Error(StartLoc, "invalid use of length addressing"); 955 return MatchOperand_ParseFail; 956 } 957 break; 958 case BDLMem: 959 // If we have Reg2, it must be an address register. 960 if (HaveReg2) { 961 if (parseAddressRegister(Reg2)) 962 return MatchOperand_ParseFail; 963 Base = Regs[Reg2.Num]; 964 } 965 // We cannot support base+index addressing. 966 if (HaveReg1 && HaveReg2) { 967 Error(StartLoc, "invalid use of indexed addressing"); 968 return MatchOperand_ParseFail; 969 } 970 // We must have a length. 971 if (!Length) { 972 Error(StartLoc, "missing length in address"); 973 return MatchOperand_ParseFail; 974 } 975 break; 976 case BDRMem: 977 // We must have Reg1, and it must be a GPR. 978 if (!HaveReg1 || Reg1.Group != RegGR) { 979 Error(StartLoc, "invalid operand for instruction"); 980 return MatchOperand_ParseFail; 981 } 982 LengthReg = SystemZMC::GR64Regs[Reg1.Num]; 983 // If we have Reg2, it must be an address register. 984 if (HaveReg2) { 985 if (parseAddressRegister(Reg2)) 986 return MatchOperand_ParseFail; 987 Base = Regs[Reg2.Num]; 988 } 989 // There must be no length. 990 if (Length) { 991 Error(StartLoc, "invalid use of length addressing"); 992 return MatchOperand_ParseFail; 993 } 994 break; 995 case BDVMem: 996 // We must have Reg1, and it must be a vector register. 997 if (!HaveReg1 || Reg1.Group != RegV) { 998 Error(StartLoc, "vector index required in address"); 999 return MatchOperand_ParseFail; 1000 } 1001 Index = SystemZMC::VR128Regs[Reg1.Num]; 1002 // If we have Reg2, it must be an address register. 1003 if (HaveReg2) { 1004 if (parseAddressRegister(Reg2)) 1005 return MatchOperand_ParseFail; 1006 Base = Regs[Reg2.Num]; 1007 } 1008 // There must be no length. 1009 if (Length) { 1010 Error(StartLoc, "invalid use of length addressing"); 1011 return MatchOperand_ParseFail; 1012 } 1013 break; 1014 } 1015 1016 SMLoc EndLoc = 1017 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1018 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp, 1019 Index, Length, LengthReg, 1020 StartLoc, EndLoc)); 1021 return MatchOperand_Success; 1022 } 1023 1024 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) { 1025 StringRef IDVal = DirectiveID.getIdentifier(); 1026 1027 if (IDVal == ".insn") 1028 return ParseDirectiveInsn(DirectiveID.getLoc()); 1029 1030 return true; 1031 } 1032 1033 /// ParseDirectiveInsn 1034 /// ::= .insn [ format, encoding, (operands (, operands)*) ] 1035 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) { 1036 MCAsmParser &Parser = getParser(); 1037 1038 // Expect instruction format as identifier. 1039 StringRef Format; 1040 SMLoc ErrorLoc = Parser.getTok().getLoc(); 1041 if (Parser.parseIdentifier(Format)) 1042 return Error(ErrorLoc, "expected instruction format"); 1043 1044 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands; 1045 1046 // Find entry for this format in InsnMatchTable. 1047 auto EntryRange = 1048 std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable), 1049 Format, CompareInsn()); 1050 1051 // If first == second, couldn't find a match in the table. 1052 if (EntryRange.first == EntryRange.second) 1053 return Error(ErrorLoc, "unrecognized format"); 1054 1055 struct InsnMatchEntry *Entry = EntryRange.first; 1056 1057 // Format should match from equal_range. 1058 assert(Entry->Format == Format); 1059 1060 // Parse the following operands using the table's information. 1061 for (int i = 0; i < Entry->NumOperands; i++) { 1062 MatchClassKind Kind = Entry->OperandKinds[i]; 1063 1064 SMLoc StartLoc = Parser.getTok().getLoc(); 1065 1066 // Always expect commas as separators for operands. 1067 if (getLexer().isNot(AsmToken::Comma)) 1068 return Error(StartLoc, "unexpected token in directive"); 1069 Lex(); 1070 1071 // Parse operands. 1072 OperandMatchResultTy ResTy; 1073 if (Kind == MCK_AnyReg) 1074 ResTy = parseAnyReg(Operands); 1075 else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20) 1076 ResTy = parseBDXAddr64(Operands); 1077 else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20) 1078 ResTy = parseBDAddr64(Operands); 1079 else if (Kind == MCK_PCRel32) 1080 ResTy = parsePCRel32(Operands); 1081 else if (Kind == MCK_PCRel16) 1082 ResTy = parsePCRel16(Operands); 1083 else { 1084 // Only remaining operand kind is an immediate. 1085 const MCExpr *Expr; 1086 SMLoc StartLoc = Parser.getTok().getLoc(); 1087 1088 // Expect immediate expression. 1089 if (Parser.parseExpression(Expr)) 1090 return Error(StartLoc, "unexpected token in directive"); 1091 1092 SMLoc EndLoc = 1093 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1094 1095 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc)); 1096 ResTy = MatchOperand_Success; 1097 } 1098 1099 if (ResTy != MatchOperand_Success) 1100 return true; 1101 } 1102 1103 // Build the instruction with the parsed operands. 1104 MCInst Inst = MCInstBuilder(Entry->Opcode); 1105 1106 for (size_t i = 0; i < Operands.size(); i++) { 1107 MCParsedAsmOperand &Operand = *Operands[i]; 1108 MatchClassKind Kind = Entry->OperandKinds[i]; 1109 1110 // Verify operand. 1111 unsigned Res = validateOperandClass(Operand, Kind); 1112 if (Res != Match_Success) 1113 return Error(Operand.getStartLoc(), "unexpected operand type"); 1114 1115 // Add operands to instruction. 1116 SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand); 1117 if (ZOperand.isReg()) 1118 ZOperand.addRegOperands(Inst, 1); 1119 else if (ZOperand.isMem(BDMem)) 1120 ZOperand.addBDAddrOperands(Inst, 2); 1121 else if (ZOperand.isMem(BDXMem)) 1122 ZOperand.addBDXAddrOperands(Inst, 3); 1123 else if (ZOperand.isImm()) 1124 ZOperand.addImmOperands(Inst, 1); 1125 else 1126 llvm_unreachable("unexpected operand type"); 1127 } 1128 1129 // Emit as a regular instruction. 1130 Parser.getStreamer().emitInstruction(Inst, getSTI()); 1131 1132 return false; 1133 } 1134 1135 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, 1136 SMLoc &EndLoc, bool RestoreOnFailure) { 1137 Register Reg; 1138 if (parseRegister(Reg, RestoreOnFailure)) 1139 return true; 1140 if (Reg.Group == RegGR) 1141 RegNo = SystemZMC::GR64Regs[Reg.Num]; 1142 else if (Reg.Group == RegFP) 1143 RegNo = SystemZMC::FP64Regs[Reg.Num]; 1144 else if (Reg.Group == RegV) 1145 RegNo = SystemZMC::VR128Regs[Reg.Num]; 1146 else if (Reg.Group == RegAR) 1147 RegNo = SystemZMC::AR32Regs[Reg.Num]; 1148 else if (Reg.Group == RegCR) 1149 RegNo = SystemZMC::CR64Regs[Reg.Num]; 1150 StartLoc = Reg.StartLoc; 1151 EndLoc = Reg.EndLoc; 1152 return false; 1153 } 1154 1155 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, 1156 SMLoc &EndLoc) { 1157 return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false); 1158 } 1159 1160 OperandMatchResultTy SystemZAsmParser::tryParseRegister(unsigned &RegNo, 1161 SMLoc &StartLoc, 1162 SMLoc &EndLoc) { 1163 bool Result = 1164 ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true); 1165 bool PendingErrors = getParser().hasPendingError(); 1166 getParser().clearPendingErrors(); 1167 if (PendingErrors) 1168 return MatchOperand_ParseFail; 1169 if (Result) 1170 return MatchOperand_NoMatch; 1171 return MatchOperand_Success; 1172 } 1173 1174 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info, 1175 StringRef Name, SMLoc NameLoc, 1176 OperandVector &Operands) { 1177 Operands.push_back(SystemZOperand::createToken(Name, NameLoc)); 1178 1179 // Read the remaining operands. 1180 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1181 // Read the first operand. 1182 if (parseOperand(Operands, Name)) { 1183 return true; 1184 } 1185 1186 // Read any subsequent operands. 1187 while (getLexer().is(AsmToken::Comma)) { 1188 Parser.Lex(); 1189 if (parseOperand(Operands, Name)) { 1190 return true; 1191 } 1192 } 1193 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1194 SMLoc Loc = getLexer().getLoc(); 1195 return Error(Loc, "unexpected token in argument list"); 1196 } 1197 } 1198 1199 // Consume the EndOfStatement. 1200 Parser.Lex(); 1201 return false; 1202 } 1203 1204 bool SystemZAsmParser::parseOperand(OperandVector &Operands, 1205 StringRef Mnemonic) { 1206 // Check if the current operand has a custom associated parser, if so, try to 1207 // custom parse the operand, or fallback to the general approach. Force all 1208 // features to be available during the operand check, or else we will fail to 1209 // find the custom parser, and then we will later get an InvalidOperand error 1210 // instead of a MissingFeature errror. 1211 FeatureBitset AvailableFeatures = getAvailableFeatures(); 1212 FeatureBitset All; 1213 All.set(); 1214 setAvailableFeatures(All); 1215 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 1216 setAvailableFeatures(AvailableFeatures); 1217 if (ResTy == MatchOperand_Success) 1218 return false; 1219 1220 // If there wasn't a custom match, try the generic matcher below. Otherwise, 1221 // there was a match, but an error occurred, in which case, just return that 1222 // the operand parsing failed. 1223 if (ResTy == MatchOperand_ParseFail) 1224 return true; 1225 1226 // Check for a register. All real register operands should have used 1227 // a context-dependent parse routine, which gives the required register 1228 // class. The code is here to mop up other cases, like those where 1229 // the instruction isn't recognized. 1230 if (Parser.getTok().is(AsmToken::Percent)) { 1231 Register Reg; 1232 if (parseRegister(Reg)) 1233 return true; 1234 Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc)); 1235 return false; 1236 } 1237 1238 // The only other type of operand is an immediate or address. As above, 1239 // real address operands should have used a context-dependent parse routine, 1240 // so we treat any plain expression as an immediate. 1241 SMLoc StartLoc = Parser.getTok().getLoc(); 1242 Register Reg1, Reg2; 1243 bool HaveReg1, HaveReg2; 1244 const MCExpr *Expr; 1245 const MCExpr *Length; 1246 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length)) 1247 return true; 1248 // If the register combination is not valid for any instruction, reject it. 1249 // Otherwise, fall back to reporting an unrecognized instruction. 1250 if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV 1251 && parseAddressRegister(Reg1)) 1252 return true; 1253 if (HaveReg2 && parseAddressRegister(Reg2)) 1254 return true; 1255 1256 SMLoc EndLoc = 1257 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1258 if (HaveReg1 || HaveReg2 || Length) 1259 Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc)); 1260 else 1261 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc)); 1262 return false; 1263 } 1264 1265 static std::string SystemZMnemonicSpellCheck(StringRef S, 1266 const FeatureBitset &FBS, 1267 unsigned VariantID = 0); 1268 1269 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 1270 OperandVector &Operands, 1271 MCStreamer &Out, 1272 uint64_t &ErrorInfo, 1273 bool MatchingInlineAsm) { 1274 MCInst Inst; 1275 unsigned MatchResult; 1276 1277 FeatureBitset MissingFeatures; 1278 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, 1279 MissingFeatures, MatchingInlineAsm); 1280 switch (MatchResult) { 1281 case Match_Success: 1282 Inst.setLoc(IDLoc); 1283 Out.emitInstruction(Inst, getSTI()); 1284 return false; 1285 1286 case Match_MissingFeature: { 1287 assert(MissingFeatures.any() && "Unknown missing feature!"); 1288 // Special case the error message for the very common case where only 1289 // a single subtarget feature is missing 1290 std::string Msg = "instruction requires:"; 1291 for (unsigned I = 0, E = MissingFeatures.size(); I != E; ++I) { 1292 if (MissingFeatures[I]) { 1293 Msg += " "; 1294 Msg += getSubtargetFeatureName(I); 1295 } 1296 } 1297 return Error(IDLoc, Msg); 1298 } 1299 1300 case Match_InvalidOperand: { 1301 SMLoc ErrorLoc = IDLoc; 1302 if (ErrorInfo != ~0ULL) { 1303 if (ErrorInfo >= Operands.size()) 1304 return Error(IDLoc, "too few operands for instruction"); 1305 1306 ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc(); 1307 if (ErrorLoc == SMLoc()) 1308 ErrorLoc = IDLoc; 1309 } 1310 return Error(ErrorLoc, "invalid operand for instruction"); 1311 } 1312 1313 case Match_MnemonicFail: { 1314 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); 1315 std::string Suggestion = SystemZMnemonicSpellCheck( 1316 ((SystemZOperand &)*Operands[0]).getToken(), FBS); 1317 return Error(IDLoc, "invalid instruction" + Suggestion, 1318 ((SystemZOperand &)*Operands[0]).getLocRange()); 1319 } 1320 } 1321 1322 llvm_unreachable("Unexpected match type"); 1323 } 1324 1325 OperandMatchResultTy 1326 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal, 1327 int64_t MaxVal, bool AllowTLS) { 1328 MCContext &Ctx = getContext(); 1329 MCStreamer &Out = getStreamer(); 1330 const MCExpr *Expr; 1331 SMLoc StartLoc = Parser.getTok().getLoc(); 1332 if (getParser().parseExpression(Expr)) 1333 return MatchOperand_NoMatch; 1334 1335 auto isOutOfRangeConstant = [&](const MCExpr *E) -> bool { 1336 if (auto *CE = dyn_cast<MCConstantExpr>(E)) { 1337 int64_t Value = CE->getValue(); 1338 if ((Value & 1) || Value < MinVal || Value > MaxVal) 1339 return true; 1340 } 1341 return false; 1342 }; 1343 1344 // For consistency with the GNU assembler, treat immediates as offsets 1345 // from ".". 1346 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) { 1347 if (isOutOfRangeConstant(CE)) { 1348 Error(StartLoc, "offset out of range"); 1349 return MatchOperand_ParseFail; 1350 } 1351 int64_t Value = CE->getValue(); 1352 MCSymbol *Sym = Ctx.createTempSymbol(); 1353 Out.emitLabel(Sym); 1354 const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, 1355 Ctx); 1356 Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx); 1357 } 1358 1359 // For consistency with the GNU assembler, conservatively assume that a 1360 // constant offset must by itself be within the given size range. 1361 if (const auto *BE = dyn_cast<MCBinaryExpr>(Expr)) 1362 if (isOutOfRangeConstant(BE->getLHS()) || 1363 isOutOfRangeConstant(BE->getRHS())) { 1364 Error(StartLoc, "offset out of range"); 1365 return MatchOperand_ParseFail; 1366 } 1367 1368 // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol. 1369 const MCExpr *Sym = nullptr; 1370 if (AllowTLS && getLexer().is(AsmToken::Colon)) { 1371 Parser.Lex(); 1372 1373 if (Parser.getTok().isNot(AsmToken::Identifier)) { 1374 Error(Parser.getTok().getLoc(), "unexpected token"); 1375 return MatchOperand_ParseFail; 1376 } 1377 1378 MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None; 1379 StringRef Name = Parser.getTok().getString(); 1380 if (Name == "tls_gdcall") 1381 Kind = MCSymbolRefExpr::VK_TLSGD; 1382 else if (Name == "tls_ldcall") 1383 Kind = MCSymbolRefExpr::VK_TLSLDM; 1384 else { 1385 Error(Parser.getTok().getLoc(), "unknown TLS tag"); 1386 return MatchOperand_ParseFail; 1387 } 1388 Parser.Lex(); 1389 1390 if (Parser.getTok().isNot(AsmToken::Colon)) { 1391 Error(Parser.getTok().getLoc(), "unexpected token"); 1392 return MatchOperand_ParseFail; 1393 } 1394 Parser.Lex(); 1395 1396 if (Parser.getTok().isNot(AsmToken::Identifier)) { 1397 Error(Parser.getTok().getLoc(), "unexpected token"); 1398 return MatchOperand_ParseFail; 1399 } 1400 1401 StringRef Identifier = Parser.getTok().getString(); 1402 Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier), 1403 Kind, Ctx); 1404 Parser.Lex(); 1405 } 1406 1407 SMLoc EndLoc = 1408 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1409 1410 if (AllowTLS) 1411 Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym, 1412 StartLoc, EndLoc)); 1413 else 1414 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc)); 1415 1416 return MatchOperand_Success; 1417 } 1418 1419 // Force static initialization. 1420 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZAsmParser() { 1421 RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget()); 1422 } 1423