1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/SystemZInstPrinter.h" 10 #include "MCTargetDesc/SystemZMCTargetDesc.h" 11 #include "TargetInfo/SystemZTargetInfo.h" 12 #include "llvm/ADT/STLExtras.h" 13 #include "llvm/ADT/SmallVector.h" 14 #include "llvm/ADT/StringRef.h" 15 #include "llvm/MC/MCAsmInfo.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstBuilder.h" 20 #include "llvm/MC/MCParser/MCAsmLexer.h" 21 #include "llvm/MC/MCParser/MCAsmParser.h" 22 #include "llvm/MC/MCParser/MCAsmParserExtension.h" 23 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 24 #include "llvm/MC/MCParser/MCTargetAsmParser.h" 25 #include "llvm/MC/MCStreamer.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/Support/Casting.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/SMLoc.h" 30 #include "llvm/Support/TargetRegistry.h" 31 #include <algorithm> 32 #include <cassert> 33 #include <cstddef> 34 #include <cstdint> 35 #include <iterator> 36 #include <memory> 37 #include <string> 38 39 using namespace llvm; 40 41 // Return true if Expr is in the range [MinValue, MaxValue]. 42 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) { 43 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) { 44 int64_t Value = CE->getValue(); 45 return Value >= MinValue && Value <= MaxValue; 46 } 47 return false; 48 } 49 50 namespace { 51 52 enum RegisterKind { 53 GR32Reg, 54 GRH32Reg, 55 GR64Reg, 56 GR128Reg, 57 FP32Reg, 58 FP64Reg, 59 FP128Reg, 60 VR32Reg, 61 VR64Reg, 62 VR128Reg, 63 AR32Reg, 64 CR64Reg, 65 }; 66 67 enum MemoryKind { 68 BDMem, 69 BDXMem, 70 BDLMem, 71 BDRMem, 72 BDVMem 73 }; 74 75 class SystemZOperand : public MCParsedAsmOperand { 76 private: 77 enum OperandKind { 78 KindInvalid, 79 KindToken, 80 KindReg, 81 KindImm, 82 KindImmTLS, 83 KindMem 84 }; 85 86 OperandKind Kind; 87 SMLoc StartLoc, EndLoc; 88 89 // A string of length Length, starting at Data. 90 struct TokenOp { 91 const char *Data; 92 unsigned Length; 93 }; 94 95 // LLVM register Num, which has kind Kind. In some ways it might be 96 // easier for this class to have a register bank (general, floating-point 97 // or access) and a raw register number (0-15). This would postpone the 98 // interpretation of the operand to the add*() methods and avoid the need 99 // for context-dependent parsing. However, we do things the current way 100 // because of the virtual getReg() method, which needs to distinguish 101 // between (say) %r0 used as a single register and %r0 used as a pair. 102 // Context-dependent parsing can also give us slightly better error 103 // messages when invalid pairs like %r1 are used. 104 struct RegOp { 105 RegisterKind Kind; 106 unsigned Num; 107 }; 108 109 // Base + Disp + Index, where Base and Index are LLVM registers or 0. 110 // MemKind says what type of memory this is and RegKind says what type 111 // the base register has (GR32Reg or GR64Reg). Length is the operand 112 // length for D(L,B)-style operands, otherwise it is null. 113 struct MemOp { 114 unsigned Base : 12; 115 unsigned Index : 12; 116 unsigned MemKind : 4; 117 unsigned RegKind : 4; 118 const MCExpr *Disp; 119 union { 120 const MCExpr *Imm; 121 unsigned Reg; 122 } Length; 123 }; 124 125 // Imm is an immediate operand, and Sym is an optional TLS symbol 126 // for use with a __tls_get_offset marker relocation. 127 struct ImmTLSOp { 128 const MCExpr *Imm; 129 const MCExpr *Sym; 130 }; 131 132 union { 133 TokenOp Token; 134 RegOp Reg; 135 const MCExpr *Imm; 136 ImmTLSOp ImmTLS; 137 MemOp Mem; 138 }; 139 140 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 141 // Add as immediates when possible. Null MCExpr = 0. 142 if (!Expr) 143 Inst.addOperand(MCOperand::createImm(0)); 144 else if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) 145 Inst.addOperand(MCOperand::createImm(CE->getValue())); 146 else 147 Inst.addOperand(MCOperand::createExpr(Expr)); 148 } 149 150 public: 151 SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc) 152 : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {} 153 154 // Create particular kinds of operand. 155 static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc, 156 SMLoc EndLoc) { 157 return std::make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc); 158 } 159 160 static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) { 161 auto Op = std::make_unique<SystemZOperand>(KindToken, Loc, Loc); 162 Op->Token.Data = Str.data(); 163 Op->Token.Length = Str.size(); 164 return Op; 165 } 166 167 static std::unique_ptr<SystemZOperand> 168 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) { 169 auto Op = std::make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc); 170 Op->Reg.Kind = Kind; 171 Op->Reg.Num = Num; 172 return Op; 173 } 174 175 static std::unique_ptr<SystemZOperand> 176 createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) { 177 auto Op = std::make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc); 178 Op->Imm = Expr; 179 return Op; 180 } 181 182 static std::unique_ptr<SystemZOperand> 183 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base, 184 const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm, 185 unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) { 186 auto Op = std::make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc); 187 Op->Mem.MemKind = MemKind; 188 Op->Mem.RegKind = RegKind; 189 Op->Mem.Base = Base; 190 Op->Mem.Index = Index; 191 Op->Mem.Disp = Disp; 192 if (MemKind == BDLMem) 193 Op->Mem.Length.Imm = LengthImm; 194 if (MemKind == BDRMem) 195 Op->Mem.Length.Reg = LengthReg; 196 return Op; 197 } 198 199 static std::unique_ptr<SystemZOperand> 200 createImmTLS(const MCExpr *Imm, const MCExpr *Sym, 201 SMLoc StartLoc, SMLoc EndLoc) { 202 auto Op = std::make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc); 203 Op->ImmTLS.Imm = Imm; 204 Op->ImmTLS.Sym = Sym; 205 return Op; 206 } 207 208 // Token operands 209 bool isToken() const override { 210 return Kind == KindToken; 211 } 212 StringRef getToken() const { 213 assert(Kind == KindToken && "Not a token"); 214 return StringRef(Token.Data, Token.Length); 215 } 216 217 // Register operands. 218 bool isReg() const override { 219 return Kind == KindReg; 220 } 221 bool isReg(RegisterKind RegKind) const { 222 return Kind == KindReg && Reg.Kind == RegKind; 223 } 224 unsigned getReg() const override { 225 assert(Kind == KindReg && "Not a register"); 226 return Reg.Num; 227 } 228 229 // Immediate operands. 230 bool isImm() const override { 231 return Kind == KindImm; 232 } 233 bool isImm(int64_t MinValue, int64_t MaxValue) const { 234 return Kind == KindImm && inRange(Imm, MinValue, MaxValue); 235 } 236 const MCExpr *getImm() const { 237 assert(Kind == KindImm && "Not an immediate"); 238 return Imm; 239 } 240 241 // Immediate operands with optional TLS symbol. 242 bool isImmTLS() const { 243 return Kind == KindImmTLS; 244 } 245 246 const ImmTLSOp getImmTLS() const { 247 assert(Kind == KindImmTLS && "Not a TLS immediate"); 248 return ImmTLS; 249 } 250 251 // Memory operands. 252 bool isMem() const override { 253 return Kind == KindMem; 254 } 255 bool isMem(MemoryKind MemKind) const { 256 return (Kind == KindMem && 257 (Mem.MemKind == MemKind || 258 // A BDMem can be treated as a BDXMem in which the index 259 // register field is 0. 260 (Mem.MemKind == BDMem && MemKind == BDXMem))); 261 } 262 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { 263 return isMem(MemKind) && Mem.RegKind == RegKind; 264 } 265 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const { 266 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff); 267 } 268 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const { 269 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287); 270 } 271 bool isMemDisp12Len4(RegisterKind RegKind) const { 272 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10); 273 } 274 bool isMemDisp12Len8(RegisterKind RegKind) const { 275 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100); 276 } 277 278 const MemOp& getMem() const { 279 assert(Kind == KindMem && "Not a Mem operand"); 280 return Mem; 281 } 282 283 // Override MCParsedAsmOperand. 284 SMLoc getStartLoc() const override { return StartLoc; } 285 SMLoc getEndLoc() const override { return EndLoc; } 286 void print(raw_ostream &OS) const override; 287 288 /// getLocRange - Get the range between the first and last token of this 289 /// operand. 290 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 291 292 // Used by the TableGen code to add particular types of operand 293 // to an instruction. 294 void addRegOperands(MCInst &Inst, unsigned N) const { 295 assert(N == 1 && "Invalid number of operands"); 296 Inst.addOperand(MCOperand::createReg(getReg())); 297 } 298 void addImmOperands(MCInst &Inst, unsigned N) const { 299 assert(N == 1 && "Invalid number of operands"); 300 addExpr(Inst, getImm()); 301 } 302 void addBDAddrOperands(MCInst &Inst, unsigned N) const { 303 assert(N == 2 && "Invalid number of operands"); 304 assert(isMem(BDMem) && "Invalid operand type"); 305 Inst.addOperand(MCOperand::createReg(Mem.Base)); 306 addExpr(Inst, Mem.Disp); 307 } 308 void addBDXAddrOperands(MCInst &Inst, unsigned N) const { 309 assert(N == 3 && "Invalid number of operands"); 310 assert(isMem(BDXMem) && "Invalid operand type"); 311 Inst.addOperand(MCOperand::createReg(Mem.Base)); 312 addExpr(Inst, Mem.Disp); 313 Inst.addOperand(MCOperand::createReg(Mem.Index)); 314 } 315 void addBDLAddrOperands(MCInst &Inst, unsigned N) const { 316 assert(N == 3 && "Invalid number of operands"); 317 assert(isMem(BDLMem) && "Invalid operand type"); 318 Inst.addOperand(MCOperand::createReg(Mem.Base)); 319 addExpr(Inst, Mem.Disp); 320 addExpr(Inst, Mem.Length.Imm); 321 } 322 void addBDRAddrOperands(MCInst &Inst, unsigned N) const { 323 assert(N == 3 && "Invalid number of operands"); 324 assert(isMem(BDRMem) && "Invalid operand type"); 325 Inst.addOperand(MCOperand::createReg(Mem.Base)); 326 addExpr(Inst, Mem.Disp); 327 Inst.addOperand(MCOperand::createReg(Mem.Length.Reg)); 328 } 329 void addBDVAddrOperands(MCInst &Inst, unsigned N) const { 330 assert(N == 3 && "Invalid number of operands"); 331 assert(isMem(BDVMem) && "Invalid operand type"); 332 Inst.addOperand(MCOperand::createReg(Mem.Base)); 333 addExpr(Inst, Mem.Disp); 334 Inst.addOperand(MCOperand::createReg(Mem.Index)); 335 } 336 void addImmTLSOperands(MCInst &Inst, unsigned N) const { 337 assert(N == 2 && "Invalid number of operands"); 338 assert(Kind == KindImmTLS && "Invalid operand type"); 339 addExpr(Inst, ImmTLS.Imm); 340 if (ImmTLS.Sym) 341 addExpr(Inst, ImmTLS.Sym); 342 } 343 344 // Used by the TableGen code to check for particular operand types. 345 bool isGR32() const { return isReg(GR32Reg); } 346 bool isGRH32() const { return isReg(GRH32Reg); } 347 bool isGRX32() const { return false; } 348 bool isGR64() const { return isReg(GR64Reg); } 349 bool isGR128() const { return isReg(GR128Reg); } 350 bool isADDR32() const { return isReg(GR32Reg); } 351 bool isADDR64() const { return isReg(GR64Reg); } 352 bool isADDR128() const { return false; } 353 bool isFP32() const { return isReg(FP32Reg); } 354 bool isFP64() const { return isReg(FP64Reg); } 355 bool isFP128() const { return isReg(FP128Reg); } 356 bool isVR32() const { return isReg(VR32Reg); } 357 bool isVR64() const { return isReg(VR64Reg); } 358 bool isVF128() const { return false; } 359 bool isVR128() const { return isReg(VR128Reg); } 360 bool isAR32() const { return isReg(AR32Reg); } 361 bool isCR64() const { return isReg(CR64Reg); } 362 bool isAnyReg() const { return (isReg() || isImm(0, 15)); } 363 bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, GR32Reg); } 364 bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, GR32Reg); } 365 bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, GR64Reg); } 366 bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, GR64Reg); } 367 bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, GR64Reg); } 368 bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, GR64Reg); } 369 bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(GR64Reg); } 370 bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(GR64Reg); } 371 bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, GR64Reg); } 372 bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, GR64Reg); } 373 bool isU1Imm() const { return isImm(0, 1); } 374 bool isU2Imm() const { return isImm(0, 3); } 375 bool isU3Imm() const { return isImm(0, 7); } 376 bool isU4Imm() const { return isImm(0, 15); } 377 bool isU6Imm() const { return isImm(0, 63); } 378 bool isU8Imm() const { return isImm(0, 255); } 379 bool isS8Imm() const { return isImm(-128, 127); } 380 bool isU12Imm() const { return isImm(0, 4095); } 381 bool isU16Imm() const { return isImm(0, 65535); } 382 bool isS16Imm() const { return isImm(-32768, 32767); } 383 bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); } 384 bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); } 385 bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); } 386 }; 387 388 class SystemZAsmParser : public MCTargetAsmParser { 389 #define GET_ASSEMBLER_HEADER 390 #include "SystemZGenAsmMatcher.inc" 391 392 private: 393 MCAsmParser &Parser; 394 enum RegisterGroup { 395 RegGR, 396 RegFP, 397 RegV, 398 RegAR, 399 RegCR 400 }; 401 struct Register { 402 RegisterGroup Group; 403 unsigned Num; 404 SMLoc StartLoc, EndLoc; 405 }; 406 407 bool parseRegister(Register &Reg, bool RestoreOnFailure = false); 408 409 bool parseIntegerRegister(Register &Reg, RegisterGroup Group); 410 411 OperandMatchResultTy parseRegister(OperandVector &Operands, 412 RegisterKind Kind); 413 414 OperandMatchResultTy parseAnyRegister(OperandVector &Operands); 415 416 bool parseAddress(bool &HaveReg1, Register &Reg1, bool &HaveReg2, 417 Register &Reg2, const MCExpr *&Disp, const MCExpr *&Length, 418 bool HasLength = false, bool HasVectorIndex = false); 419 bool parseAddressRegister(Register &Reg); 420 421 bool ParseDirectiveInsn(SMLoc L); 422 423 OperandMatchResultTy parseAddress(OperandVector &Operands, 424 MemoryKind MemKind, 425 RegisterKind RegKind); 426 427 OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal, 428 int64_t MaxVal, bool AllowTLS); 429 430 bool parseOperand(OperandVector &Operands, StringRef Mnemonic); 431 432 // Both the hlasm and att variants still rely on the basic gnu asm 433 // format with respect to inputs, clobbers, outputs etc. 434 // 435 // However, calling the overriden getAssemblerDialect() method in 436 // AsmParser is problematic. It either returns the AssemblerDialect field 437 // in the MCAsmInfo instance if the AssemblerDialect field in AsmParser is 438 // unset, otherwise it returns the private AssemblerDialect field in 439 // AsmParser. 440 // 441 // The problematic part is because, we forcibly set the inline asm dialect 442 // in the AsmParser instance in AsmPrinterInlineAsm.cpp. Soo any query 443 // to the overriden getAssemblerDialect function in AsmParser.cpp, will 444 // not return the assembler dialect set in the respective MCAsmInfo instance. 445 // 446 // For this purpose, we explicitly query the SystemZMCAsmInfo instance 447 // here, to get the "correct" assembler dialect, and use it in various 448 // functions. 449 unsigned getMAIAssemblerDialect() { 450 return Parser.getContext().getAsmInfo()->getAssemblerDialect(); 451 } 452 453 public: 454 SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser, 455 const MCInstrInfo &MII, 456 const MCTargetOptions &Options) 457 : MCTargetAsmParser(Options, sti, MII), Parser(parser) { 458 MCAsmParserExtension::Initialize(Parser); 459 460 // Alias the .word directive to .short. 461 parser.addAliasForDirective(".word", ".short"); 462 463 // Initialize the set of available features. 464 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); 465 } 466 467 // Override MCTargetAsmParser. 468 bool ParseDirective(AsmToken DirectiveID) override; 469 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 470 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc, 471 bool RestoreOnFailure); 472 OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, 473 SMLoc &EndLoc) override; 474 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 475 SMLoc NameLoc, OperandVector &Operands) override; 476 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 477 OperandVector &Operands, MCStreamer &Out, 478 uint64_t &ErrorInfo, 479 bool MatchingInlineAsm) override; 480 481 // Used by the TableGen code to parse particular operand types. 482 OperandMatchResultTy parseGR32(OperandVector &Operands) { 483 return parseRegister(Operands, GR32Reg); 484 } 485 OperandMatchResultTy parseGRH32(OperandVector &Operands) { 486 return parseRegister(Operands, GRH32Reg); 487 } 488 OperandMatchResultTy parseGRX32(OperandVector &Operands) { 489 llvm_unreachable("GRX32 should only be used for pseudo instructions"); 490 } 491 OperandMatchResultTy parseGR64(OperandVector &Operands) { 492 return parseRegister(Operands, GR64Reg); 493 } 494 OperandMatchResultTy parseGR128(OperandVector &Operands) { 495 return parseRegister(Operands, GR128Reg); 496 } 497 OperandMatchResultTy parseADDR32(OperandVector &Operands) { 498 // For the AsmParser, we will accept %r0 for ADDR32 as well. 499 return parseRegister(Operands, GR32Reg); 500 } 501 OperandMatchResultTy parseADDR64(OperandVector &Operands) { 502 // For the AsmParser, we will accept %r0 for ADDR64 as well. 503 return parseRegister(Operands, GR64Reg); 504 } 505 OperandMatchResultTy parseADDR128(OperandVector &Operands) { 506 llvm_unreachable("Shouldn't be used as an operand"); 507 } 508 OperandMatchResultTy parseFP32(OperandVector &Operands) { 509 return parseRegister(Operands, FP32Reg); 510 } 511 OperandMatchResultTy parseFP64(OperandVector &Operands) { 512 return parseRegister(Operands, FP64Reg); 513 } 514 OperandMatchResultTy parseFP128(OperandVector &Operands) { 515 return parseRegister(Operands, FP128Reg); 516 } 517 OperandMatchResultTy parseVR32(OperandVector &Operands) { 518 return parseRegister(Operands, VR32Reg); 519 } 520 OperandMatchResultTy parseVR64(OperandVector &Operands) { 521 return parseRegister(Operands, VR64Reg); 522 } 523 OperandMatchResultTy parseVF128(OperandVector &Operands) { 524 llvm_unreachable("Shouldn't be used as an operand"); 525 } 526 OperandMatchResultTy parseVR128(OperandVector &Operands) { 527 return parseRegister(Operands, VR128Reg); 528 } 529 OperandMatchResultTy parseAR32(OperandVector &Operands) { 530 return parseRegister(Operands, AR32Reg); 531 } 532 OperandMatchResultTy parseCR64(OperandVector &Operands) { 533 return parseRegister(Operands, CR64Reg); 534 } 535 OperandMatchResultTy parseAnyReg(OperandVector &Operands) { 536 return parseAnyRegister(Operands); 537 } 538 OperandMatchResultTy parseBDAddr32(OperandVector &Operands) { 539 return parseAddress(Operands, BDMem, GR32Reg); 540 } 541 OperandMatchResultTy parseBDAddr64(OperandVector &Operands) { 542 return parseAddress(Operands, BDMem, GR64Reg); 543 } 544 OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) { 545 return parseAddress(Operands, BDXMem, GR64Reg); 546 } 547 OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) { 548 return parseAddress(Operands, BDLMem, GR64Reg); 549 } 550 OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) { 551 return parseAddress(Operands, BDRMem, GR64Reg); 552 } 553 OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) { 554 return parseAddress(Operands, BDVMem, GR64Reg); 555 } 556 OperandMatchResultTy parsePCRel12(OperandVector &Operands) { 557 return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false); 558 } 559 OperandMatchResultTy parsePCRel16(OperandVector &Operands) { 560 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false); 561 } 562 OperandMatchResultTy parsePCRel24(OperandVector &Operands) { 563 return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false); 564 } 565 OperandMatchResultTy parsePCRel32(OperandVector &Operands) { 566 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false); 567 } 568 OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) { 569 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true); 570 } 571 OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) { 572 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true); 573 } 574 }; 575 576 } // end anonymous namespace 577 578 #define GET_REGISTER_MATCHER 579 #define GET_SUBTARGET_FEATURE_NAME 580 #define GET_MATCHER_IMPLEMENTATION 581 #define GET_MNEMONIC_SPELL_CHECKER 582 #include "SystemZGenAsmMatcher.inc" 583 584 // Used for the .insn directives; contains information needed to parse the 585 // operands in the directive. 586 struct InsnMatchEntry { 587 StringRef Format; 588 uint64_t Opcode; 589 int32_t NumOperands; 590 MatchClassKind OperandKinds[7]; 591 }; 592 593 // For equal_range comparison. 594 struct CompareInsn { 595 bool operator() (const InsnMatchEntry &LHS, StringRef RHS) { 596 return LHS.Format < RHS; 597 } 598 bool operator() (StringRef LHS, const InsnMatchEntry &RHS) { 599 return LHS < RHS.Format; 600 } 601 bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) { 602 return LHS.Format < RHS.Format; 603 } 604 }; 605 606 // Table initializing information for parsing the .insn directive. 607 static struct InsnMatchEntry InsnMatchTable[] = { 608 /* Format, Opcode, NumOperands, OperandKinds */ 609 { "e", SystemZ::InsnE, 1, 610 { MCK_U16Imm } }, 611 { "ri", SystemZ::InsnRI, 3, 612 { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } }, 613 { "rie", SystemZ::InsnRIE, 4, 614 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } }, 615 { "ril", SystemZ::InsnRIL, 3, 616 { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } }, 617 { "rilu", SystemZ::InsnRILU, 3, 618 { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } }, 619 { "ris", SystemZ::InsnRIS, 5, 620 { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } }, 621 { "rr", SystemZ::InsnRR, 3, 622 { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } }, 623 { "rre", SystemZ::InsnRRE, 3, 624 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } }, 625 { "rrf", SystemZ::InsnRRF, 5, 626 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } }, 627 { "rrs", SystemZ::InsnRRS, 5, 628 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } }, 629 { "rs", SystemZ::InsnRS, 4, 630 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } }, 631 { "rse", SystemZ::InsnRSE, 4, 632 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } }, 633 { "rsi", SystemZ::InsnRSI, 4, 634 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } }, 635 { "rsy", SystemZ::InsnRSY, 4, 636 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } }, 637 { "rx", SystemZ::InsnRX, 3, 638 { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } }, 639 { "rxe", SystemZ::InsnRXE, 3, 640 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } }, 641 { "rxf", SystemZ::InsnRXF, 4, 642 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } }, 643 { "rxy", SystemZ::InsnRXY, 3, 644 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } }, 645 { "s", SystemZ::InsnS, 2, 646 { MCK_U32Imm, MCK_BDAddr64Disp12 } }, 647 { "si", SystemZ::InsnSI, 3, 648 { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } }, 649 { "sil", SystemZ::InsnSIL, 3, 650 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } }, 651 { "siy", SystemZ::InsnSIY, 3, 652 { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } }, 653 { "ss", SystemZ::InsnSS, 4, 654 { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }, 655 { "sse", SystemZ::InsnSSE, 3, 656 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } }, 657 { "ssf", SystemZ::InsnSSF, 4, 658 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }, 659 { "vri", SystemZ::InsnVRI, 6, 660 { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_U12Imm, MCK_U4Imm, MCK_U4Imm } }, 661 { "vrr", SystemZ::InsnVRR, 7, 662 { MCK_U48Imm, MCK_VR128, MCK_VR128, MCK_VR128, MCK_U4Imm, MCK_U4Imm, 663 MCK_U4Imm } }, 664 { "vrs", SystemZ::InsnVRS, 5, 665 { MCK_U48Imm, MCK_AnyReg, MCK_VR128, MCK_BDAddr64Disp12, MCK_U4Imm } }, 666 { "vrv", SystemZ::InsnVRV, 4, 667 { MCK_U48Imm, MCK_VR128, MCK_BDVAddr64Disp12, MCK_U4Imm } }, 668 { "vrx", SystemZ::InsnVRX, 4, 669 { MCK_U48Imm, MCK_VR128, MCK_BDXAddr64Disp12, MCK_U4Imm } }, 670 { "vsi", SystemZ::InsnVSI, 4, 671 { MCK_U48Imm, MCK_VR128, MCK_BDAddr64Disp12, MCK_U8Imm } } 672 }; 673 674 static void printMCExpr(const MCExpr *E, raw_ostream &OS) { 675 if (!E) 676 return; 677 if (auto *CE = dyn_cast<MCConstantExpr>(E)) 678 OS << *CE; 679 else if (auto *UE = dyn_cast<MCUnaryExpr>(E)) 680 OS << *UE; 681 else if (auto *BE = dyn_cast<MCBinaryExpr>(E)) 682 OS << *BE; 683 else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E)) 684 OS << *SRE; 685 else 686 OS << *E; 687 } 688 689 void SystemZOperand::print(raw_ostream &OS) const { 690 switch (Kind) { 691 case KindToken: 692 OS << "Token:" << getToken(); 693 break; 694 case KindReg: 695 OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg()); 696 break; 697 case KindImm: 698 OS << "Imm:"; 699 printMCExpr(getImm(), OS); 700 break; 701 case KindImmTLS: 702 OS << "ImmTLS:"; 703 printMCExpr(getImmTLS().Imm, OS); 704 if (getImmTLS().Sym) { 705 OS << ", "; 706 printMCExpr(getImmTLS().Sym, OS); 707 } 708 break; 709 case KindMem: { 710 const MemOp &Op = getMem(); 711 OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp); 712 if (Op.Base) { 713 OS << "("; 714 if (Op.MemKind == BDLMem) 715 OS << *cast<MCConstantExpr>(Op.Length.Imm) << ","; 716 else if (Op.MemKind == BDRMem) 717 OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ","; 718 if (Op.Index) 719 OS << SystemZInstPrinter::getRegisterName(Op.Index) << ","; 720 OS << SystemZInstPrinter::getRegisterName(Op.Base); 721 OS << ")"; 722 } 723 break; 724 } 725 case KindInvalid: 726 break; 727 } 728 } 729 730 // Parse one register of the form %<prefix><number>. 731 bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) { 732 Reg.StartLoc = Parser.getTok().getLoc(); 733 734 // Eat the % prefix. 735 if (Parser.getTok().isNot(AsmToken::Percent)) 736 return Error(Parser.getTok().getLoc(), "register expected"); 737 const AsmToken &PercentTok = Parser.getTok(); 738 Parser.Lex(); 739 740 // Expect a register name. 741 if (Parser.getTok().isNot(AsmToken::Identifier)) { 742 if (RestoreOnFailure) 743 getLexer().UnLex(PercentTok); 744 return Error(Reg.StartLoc, "invalid register"); 745 } 746 747 // Check that there's a prefix. 748 StringRef Name = Parser.getTok().getString(); 749 if (Name.size() < 2) { 750 if (RestoreOnFailure) 751 getLexer().UnLex(PercentTok); 752 return Error(Reg.StartLoc, "invalid register"); 753 } 754 char Prefix = Name[0]; 755 756 // Treat the rest of the register name as a register number. 757 if (Name.substr(1).getAsInteger(10, Reg.Num)) { 758 if (RestoreOnFailure) 759 getLexer().UnLex(PercentTok); 760 return Error(Reg.StartLoc, "invalid register"); 761 } 762 763 // Look for valid combinations of prefix and number. 764 if (Prefix == 'r' && Reg.Num < 16) 765 Reg.Group = RegGR; 766 else if (Prefix == 'f' && Reg.Num < 16) 767 Reg.Group = RegFP; 768 else if (Prefix == 'v' && Reg.Num < 32) 769 Reg.Group = RegV; 770 else if (Prefix == 'a' && Reg.Num < 16) 771 Reg.Group = RegAR; 772 else if (Prefix == 'c' && Reg.Num < 16) 773 Reg.Group = RegCR; 774 else { 775 if (RestoreOnFailure) 776 getLexer().UnLex(PercentTok); 777 return Error(Reg.StartLoc, "invalid register"); 778 } 779 780 Reg.EndLoc = Parser.getTok().getLoc(); 781 Parser.Lex(); 782 return false; 783 } 784 785 // Parse a register of kind Kind and add it to Operands. 786 OperandMatchResultTy 787 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterKind Kind) { 788 Register Reg; 789 RegisterGroup Group; 790 switch (Kind) { 791 case GR32Reg: 792 case GRH32Reg: 793 case GR64Reg: 794 case GR128Reg: 795 Group = RegGR; 796 break; 797 case FP32Reg: 798 case FP64Reg: 799 case FP128Reg: 800 Group = RegFP; 801 break; 802 case VR32Reg: 803 case VR64Reg: 804 case VR128Reg: 805 Group = RegV; 806 break; 807 case AR32Reg: 808 Group = RegAR; 809 break; 810 case CR64Reg: 811 Group = RegCR; 812 break; 813 } 814 815 // Handle register names of the form %<prefix><number> 816 if (Parser.getTok().is(AsmToken::Percent)) { 817 if (parseRegister(Reg)) 818 return MatchOperand_ParseFail; 819 820 // Check the parsed register group "Reg.Group" with the expected "Group" 821 // Have to error out if user specified wrong prefix. 822 switch (Group) { 823 case RegGR: 824 case RegFP: 825 case RegAR: 826 case RegCR: 827 if (Group != Reg.Group) { 828 Error(Reg.StartLoc, "invalid operand for instruction"); 829 return MatchOperand_ParseFail; 830 } 831 break; 832 case RegV: 833 if (Reg.Group != RegV && Reg.Group != RegFP) { 834 Error(Reg.StartLoc, "invalid operand for instruction"); 835 return MatchOperand_ParseFail; 836 } 837 break; 838 } 839 } else if (Parser.getTok().is(AsmToken::Integer)) { 840 if (parseIntegerRegister(Reg, Group)) 841 return MatchOperand_ParseFail; 842 } 843 // Otherwise we didn't match a register operand. 844 else 845 return MatchOperand_NoMatch; 846 847 // Determine the LLVM register number according to Kind. 848 const unsigned *Regs; 849 switch (Kind) { 850 case GR32Reg: Regs = SystemZMC::GR32Regs; break; 851 case GRH32Reg: Regs = SystemZMC::GRH32Regs; break; 852 case GR64Reg: Regs = SystemZMC::GR64Regs; break; 853 case GR128Reg: Regs = SystemZMC::GR128Regs; break; 854 case FP32Reg: Regs = SystemZMC::FP32Regs; break; 855 case FP64Reg: Regs = SystemZMC::FP64Regs; break; 856 case FP128Reg: Regs = SystemZMC::FP128Regs; break; 857 case VR32Reg: Regs = SystemZMC::VR32Regs; break; 858 case VR64Reg: Regs = SystemZMC::VR64Regs; break; 859 case VR128Reg: Regs = SystemZMC::VR128Regs; break; 860 case AR32Reg: Regs = SystemZMC::AR32Regs; break; 861 case CR64Reg: Regs = SystemZMC::CR64Regs; break; 862 } 863 if (Regs[Reg.Num] == 0) { 864 Error(Reg.StartLoc, "invalid register pair"); 865 return MatchOperand_ParseFail; 866 } 867 868 Operands.push_back( 869 SystemZOperand::createReg(Kind, Regs[Reg.Num], Reg.StartLoc, Reg.EndLoc)); 870 return MatchOperand_Success; 871 } 872 873 // Parse any type of register (including integers) and add it to Operands. 874 OperandMatchResultTy 875 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) { 876 SMLoc StartLoc = Parser.getTok().getLoc(); 877 878 // Handle integer values. 879 if (Parser.getTok().is(AsmToken::Integer)) { 880 const MCExpr *Register; 881 if (Parser.parseExpression(Register)) 882 return MatchOperand_ParseFail; 883 884 if (auto *CE = dyn_cast<MCConstantExpr>(Register)) { 885 int64_t Value = CE->getValue(); 886 if (Value < 0 || Value > 15) { 887 Error(StartLoc, "invalid register"); 888 return MatchOperand_ParseFail; 889 } 890 } 891 892 SMLoc EndLoc = 893 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 894 895 Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc)); 896 } 897 else { 898 Register Reg; 899 if (parseRegister(Reg)) 900 return MatchOperand_ParseFail; 901 902 if (Reg.Num > 15) { 903 Error(StartLoc, "invalid register"); 904 return MatchOperand_ParseFail; 905 } 906 907 // Map to the correct register kind. 908 RegisterKind Kind; 909 unsigned RegNo; 910 if (Reg.Group == RegGR) { 911 Kind = GR64Reg; 912 RegNo = SystemZMC::GR64Regs[Reg.Num]; 913 } 914 else if (Reg.Group == RegFP) { 915 Kind = FP64Reg; 916 RegNo = SystemZMC::FP64Regs[Reg.Num]; 917 } 918 else if (Reg.Group == RegV) { 919 Kind = VR128Reg; 920 RegNo = SystemZMC::VR128Regs[Reg.Num]; 921 } 922 else if (Reg.Group == RegAR) { 923 Kind = AR32Reg; 924 RegNo = SystemZMC::AR32Regs[Reg.Num]; 925 } 926 else if (Reg.Group == RegCR) { 927 Kind = CR64Reg; 928 RegNo = SystemZMC::CR64Regs[Reg.Num]; 929 } 930 else { 931 return MatchOperand_ParseFail; 932 } 933 934 Operands.push_back(SystemZOperand::createReg(Kind, RegNo, 935 Reg.StartLoc, Reg.EndLoc)); 936 } 937 return MatchOperand_Success; 938 } 939 940 bool SystemZAsmParser::parseIntegerRegister(Register &Reg, 941 RegisterGroup Group) { 942 Reg.StartLoc = Parser.getTok().getLoc(); 943 // We have an integer token 944 const MCExpr *Register; 945 if (Parser.parseExpression(Register)) 946 return true; 947 948 const auto *CE = dyn_cast<MCConstantExpr>(Register); 949 if (!CE) 950 return true; 951 952 int64_t MaxRegNum = (Group == RegV) ? 31 : 15; 953 int64_t Value = CE->getValue(); 954 if (Value < 0 || Value > MaxRegNum) { 955 Error(Parser.getTok().getLoc(), "invalid register"); 956 return true; 957 } 958 959 // Assign the Register Number 960 Reg.Num = (unsigned)Value; 961 Reg.Group = Group; 962 Reg.EndLoc = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 963 964 // At this point, successfully parsed an integer register. 965 return false; 966 } 967 968 // Parse a memory operand into Reg1, Reg2, Disp, and Length. 969 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1, 970 bool &HaveReg2, Register &Reg2, 971 const MCExpr *&Disp, const MCExpr *&Length, 972 bool HasLength, bool HasVectorIndex) { 973 // Parse the displacement, which must always be present. 974 if (getParser().parseExpression(Disp)) 975 return true; 976 977 // Parse the optional base and index. 978 HaveReg1 = false; 979 HaveReg2 = false; 980 Length = nullptr; 981 982 // If we have a scenario as below: 983 // vgef %v0, 0(0), 0 984 // This is an example of a "BDVMem" instruction type. 985 // 986 // So when we parse this as an integer register, the register group 987 // needs to be tied to "RegV". Usually when the prefix is passed in 988 // as %<prefix><reg-number> its easy to check which group it should belong to 989 // However, if we're passing in just the integer there's no real way to 990 // "check" what register group it should belong to. 991 // 992 // When the user passes in the register as an integer, the user assumes that 993 // the compiler is responsible for substituting it as the right kind of 994 // register. Whereas, when the user specifies a "prefix", the onus is on 995 // the user to make sure they pass in the right kind of register. 996 // 997 // The restriction only applies to the first Register (i.e. Reg1). Reg2 is 998 // always a general register. Reg1 should be of group RegV if "HasVectorIndex" 999 // (i.e. insn is of type BDVMem) is true. 1000 RegisterGroup RegGroup = HasVectorIndex ? RegV : RegGR; 1001 1002 if (getLexer().is(AsmToken::LParen)) { 1003 Parser.Lex(); 1004 1005 if (getLexer().is(AsmToken::Percent)) { 1006 // Parse the first register. 1007 HaveReg1 = true; 1008 if (parseRegister(Reg1)) 1009 return true; 1010 } 1011 // So if we have an integer as the first token in ([tok1], ..), it could: 1012 // 1. Refer to a "Register" (i.e X,R,V fields in BD[X|R|V]Mem type of 1013 // instructions) 1014 // 2. Refer to a "Length" field (i.e L field in BDLMem type of instructions) 1015 else if (getLexer().is(AsmToken::Integer)) { 1016 if (HasLength) { 1017 // Instruction has a "Length" field, safe to parse the first token as 1018 // the "Length" field 1019 if (getParser().parseExpression(Length)) 1020 return true; 1021 } else { 1022 // Otherwise, if the instruction has no "Length" field, parse the 1023 // token as a "Register". We don't have to worry about whether the 1024 // instruction is invalid here, because the caller will take care of 1025 // error reporting. 1026 HaveReg1 = true; 1027 if (parseIntegerRegister(Reg1, RegGroup)) 1028 return true; 1029 } 1030 } else { 1031 // If its not an integer or a percent token, then if the instruction 1032 // is reported to have a "Length" then, parse it as "Length". 1033 if (HasLength) { 1034 if (getParser().parseExpression(Length)) 1035 return true; 1036 } 1037 } 1038 1039 // Check whether there's a second register. 1040 if (getLexer().is(AsmToken::Comma)) { 1041 Parser.Lex(); 1042 HaveReg2 = true; 1043 1044 if (getLexer().is(AsmToken::Integer)) { 1045 if (parseIntegerRegister(Reg2, RegGR)) 1046 return true; 1047 } else { 1048 if (parseRegister(Reg2)) 1049 return true; 1050 } 1051 } 1052 1053 // Consume the closing bracket. 1054 if (getLexer().isNot(AsmToken::RParen)) 1055 return Error(Parser.getTok().getLoc(), "unexpected token in address"); 1056 Parser.Lex(); 1057 } 1058 return false; 1059 } 1060 1061 // Verify that Reg is a valid address register (base or index). 1062 bool 1063 SystemZAsmParser::parseAddressRegister(Register &Reg) { 1064 if (Reg.Group == RegV) { 1065 Error(Reg.StartLoc, "invalid use of vector addressing"); 1066 return true; 1067 } else if (Reg.Group != RegGR) { 1068 Error(Reg.StartLoc, "invalid address register"); 1069 return true; 1070 } 1071 return false; 1072 } 1073 1074 // Parse a memory operand and add it to Operands. The other arguments 1075 // are as above. 1076 OperandMatchResultTy 1077 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind, 1078 RegisterKind RegKind) { 1079 SMLoc StartLoc = Parser.getTok().getLoc(); 1080 unsigned Base = 0, Index = 0, LengthReg = 0; 1081 Register Reg1, Reg2; 1082 bool HaveReg1, HaveReg2; 1083 const MCExpr *Disp; 1084 const MCExpr *Length; 1085 1086 bool HasLength = (MemKind == BDLMem) ? true : false; 1087 bool HasVectorIndex = (MemKind == BDVMem) ? true : false; 1088 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length, HasLength, 1089 HasVectorIndex)) 1090 return MatchOperand_ParseFail; 1091 1092 const unsigned *Regs; 1093 switch (RegKind) { 1094 case GR32Reg: Regs = SystemZMC::GR32Regs; break; 1095 case GR64Reg: Regs = SystemZMC::GR64Regs; break; 1096 default: llvm_unreachable("invalid RegKind"); 1097 } 1098 1099 switch (MemKind) { 1100 case BDMem: 1101 // If we have Reg1, it must be an address register. 1102 if (HaveReg1) { 1103 if (parseAddressRegister(Reg1)) 1104 return MatchOperand_ParseFail; 1105 Base = Regs[Reg1.Num]; 1106 } 1107 // There must be no Reg2. 1108 if (HaveReg2) { 1109 Error(StartLoc, "invalid use of indexed addressing"); 1110 return MatchOperand_ParseFail; 1111 } 1112 break; 1113 case BDXMem: 1114 // If we have Reg1, it must be an address register. 1115 if (HaveReg1) { 1116 if (parseAddressRegister(Reg1)) 1117 return MatchOperand_ParseFail; 1118 // If the are two registers, the first one is the index and the 1119 // second is the base. 1120 if (HaveReg2) 1121 Index = Regs[Reg1.Num]; 1122 else 1123 Base = Regs[Reg1.Num]; 1124 } 1125 // If we have Reg2, it must be an address register. 1126 if (HaveReg2) { 1127 if (parseAddressRegister(Reg2)) 1128 return MatchOperand_ParseFail; 1129 Base = Regs[Reg2.Num]; 1130 } 1131 break; 1132 case BDLMem: 1133 // If we have Reg2, it must be an address register. 1134 if (HaveReg2) { 1135 if (parseAddressRegister(Reg2)) 1136 return MatchOperand_ParseFail; 1137 Base = Regs[Reg2.Num]; 1138 } 1139 // We cannot support base+index addressing. 1140 if (HaveReg1 && HaveReg2) { 1141 Error(StartLoc, "invalid use of indexed addressing"); 1142 return MatchOperand_ParseFail; 1143 } 1144 // We must have a length. 1145 if (!Length) { 1146 Error(StartLoc, "missing length in address"); 1147 return MatchOperand_ParseFail; 1148 } 1149 break; 1150 case BDRMem: 1151 // We must have Reg1, and it must be a GPR. 1152 if (!HaveReg1 || Reg1.Group != RegGR) { 1153 Error(StartLoc, "invalid operand for instruction"); 1154 return MatchOperand_ParseFail; 1155 } 1156 LengthReg = SystemZMC::GR64Regs[Reg1.Num]; 1157 // If we have Reg2, it must be an address register. 1158 if (HaveReg2) { 1159 if (parseAddressRegister(Reg2)) 1160 return MatchOperand_ParseFail; 1161 Base = Regs[Reg2.Num]; 1162 } 1163 break; 1164 case BDVMem: 1165 // We must have Reg1, and it must be a vector register. 1166 if (!HaveReg1 || Reg1.Group != RegV) { 1167 Error(StartLoc, "vector index required in address"); 1168 return MatchOperand_ParseFail; 1169 } 1170 Index = SystemZMC::VR128Regs[Reg1.Num]; 1171 // If we have Reg2, it must be an address register. 1172 if (HaveReg2) { 1173 if (parseAddressRegister(Reg2)) 1174 return MatchOperand_ParseFail; 1175 Base = Regs[Reg2.Num]; 1176 } 1177 break; 1178 } 1179 1180 SMLoc EndLoc = 1181 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1182 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp, 1183 Index, Length, LengthReg, 1184 StartLoc, EndLoc)); 1185 return MatchOperand_Success; 1186 } 1187 1188 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) { 1189 StringRef IDVal = DirectiveID.getIdentifier(); 1190 1191 if (IDVal == ".insn") 1192 return ParseDirectiveInsn(DirectiveID.getLoc()); 1193 1194 return true; 1195 } 1196 1197 /// ParseDirectiveInsn 1198 /// ::= .insn [ format, encoding, (operands (, operands)*) ] 1199 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) { 1200 MCAsmParser &Parser = getParser(); 1201 1202 // Expect instruction format as identifier. 1203 StringRef Format; 1204 SMLoc ErrorLoc = Parser.getTok().getLoc(); 1205 if (Parser.parseIdentifier(Format)) 1206 return Error(ErrorLoc, "expected instruction format"); 1207 1208 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands; 1209 1210 // Find entry for this format in InsnMatchTable. 1211 auto EntryRange = 1212 std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable), 1213 Format, CompareInsn()); 1214 1215 // If first == second, couldn't find a match in the table. 1216 if (EntryRange.first == EntryRange.second) 1217 return Error(ErrorLoc, "unrecognized format"); 1218 1219 struct InsnMatchEntry *Entry = EntryRange.first; 1220 1221 // Format should match from equal_range. 1222 assert(Entry->Format == Format); 1223 1224 // Parse the following operands using the table's information. 1225 for (int i = 0; i < Entry->NumOperands; i++) { 1226 MatchClassKind Kind = Entry->OperandKinds[i]; 1227 1228 SMLoc StartLoc = Parser.getTok().getLoc(); 1229 1230 // Always expect commas as separators for operands. 1231 if (getLexer().isNot(AsmToken::Comma)) 1232 return Error(StartLoc, "unexpected token in directive"); 1233 Lex(); 1234 1235 // Parse operands. 1236 OperandMatchResultTy ResTy; 1237 if (Kind == MCK_AnyReg) 1238 ResTy = parseAnyReg(Operands); 1239 else if (Kind == MCK_VR128) 1240 ResTy = parseVR128(Operands); 1241 else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20) 1242 ResTy = parseBDXAddr64(Operands); 1243 else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20) 1244 ResTy = parseBDAddr64(Operands); 1245 else if (Kind == MCK_BDVAddr64Disp12) 1246 ResTy = parseBDVAddr64(Operands); 1247 else if (Kind == MCK_PCRel32) 1248 ResTy = parsePCRel32(Operands); 1249 else if (Kind == MCK_PCRel16) 1250 ResTy = parsePCRel16(Operands); 1251 else { 1252 // Only remaining operand kind is an immediate. 1253 const MCExpr *Expr; 1254 SMLoc StartLoc = Parser.getTok().getLoc(); 1255 1256 // Expect immediate expression. 1257 if (Parser.parseExpression(Expr)) 1258 return Error(StartLoc, "unexpected token in directive"); 1259 1260 SMLoc EndLoc = 1261 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1262 1263 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc)); 1264 ResTy = MatchOperand_Success; 1265 } 1266 1267 if (ResTy != MatchOperand_Success) 1268 return true; 1269 } 1270 1271 // Build the instruction with the parsed operands. 1272 MCInst Inst = MCInstBuilder(Entry->Opcode); 1273 1274 for (size_t i = 0; i < Operands.size(); i++) { 1275 MCParsedAsmOperand &Operand = *Operands[i]; 1276 MatchClassKind Kind = Entry->OperandKinds[i]; 1277 1278 // Verify operand. 1279 unsigned Res = validateOperandClass(Operand, Kind); 1280 if (Res != Match_Success) 1281 return Error(Operand.getStartLoc(), "unexpected operand type"); 1282 1283 // Add operands to instruction. 1284 SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand); 1285 if (ZOperand.isReg()) 1286 ZOperand.addRegOperands(Inst, 1); 1287 else if (ZOperand.isMem(BDMem)) 1288 ZOperand.addBDAddrOperands(Inst, 2); 1289 else if (ZOperand.isMem(BDXMem)) 1290 ZOperand.addBDXAddrOperands(Inst, 3); 1291 else if (ZOperand.isMem(BDVMem)) 1292 ZOperand.addBDVAddrOperands(Inst, 3); 1293 else if (ZOperand.isImm()) 1294 ZOperand.addImmOperands(Inst, 1); 1295 else 1296 llvm_unreachable("unexpected operand type"); 1297 } 1298 1299 // Emit as a regular instruction. 1300 Parser.getStreamer().emitInstruction(Inst, getSTI()); 1301 1302 return false; 1303 } 1304 1305 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, 1306 SMLoc &EndLoc, bool RestoreOnFailure) { 1307 Register Reg; 1308 if (parseRegister(Reg, RestoreOnFailure)) 1309 return true; 1310 if (Reg.Group == RegGR) 1311 RegNo = SystemZMC::GR64Regs[Reg.Num]; 1312 else if (Reg.Group == RegFP) 1313 RegNo = SystemZMC::FP64Regs[Reg.Num]; 1314 else if (Reg.Group == RegV) 1315 RegNo = SystemZMC::VR128Regs[Reg.Num]; 1316 else if (Reg.Group == RegAR) 1317 RegNo = SystemZMC::AR32Regs[Reg.Num]; 1318 else if (Reg.Group == RegCR) 1319 RegNo = SystemZMC::CR64Regs[Reg.Num]; 1320 StartLoc = Reg.StartLoc; 1321 EndLoc = Reg.EndLoc; 1322 return false; 1323 } 1324 1325 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, 1326 SMLoc &EndLoc) { 1327 return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false); 1328 } 1329 1330 OperandMatchResultTy SystemZAsmParser::tryParseRegister(unsigned &RegNo, 1331 SMLoc &StartLoc, 1332 SMLoc &EndLoc) { 1333 bool Result = 1334 ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true); 1335 bool PendingErrors = getParser().hasPendingError(); 1336 getParser().clearPendingErrors(); 1337 if (PendingErrors) 1338 return MatchOperand_ParseFail; 1339 if (Result) 1340 return MatchOperand_NoMatch; 1341 return MatchOperand_Success; 1342 } 1343 1344 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info, 1345 StringRef Name, SMLoc NameLoc, 1346 OperandVector &Operands) { 1347 1348 // Apply mnemonic aliases first, before doing anything else, in 1349 // case the target uses it. 1350 applyMnemonicAliases(Name, getAvailableFeatures(), getMAIAssemblerDialect()); 1351 1352 Operands.push_back(SystemZOperand::createToken(Name, NameLoc)); 1353 1354 // Read the remaining operands. 1355 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1356 // Read the first operand. 1357 if (parseOperand(Operands, Name)) { 1358 return true; 1359 } 1360 1361 // Read any subsequent operands. 1362 while (getLexer().is(AsmToken::Comma)) { 1363 Parser.Lex(); 1364 if (parseOperand(Operands, Name)) { 1365 return true; 1366 } 1367 } 1368 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1369 SMLoc Loc = getLexer().getLoc(); 1370 return Error(Loc, "unexpected token in argument list"); 1371 } 1372 } 1373 1374 // Consume the EndOfStatement. 1375 Parser.Lex(); 1376 return false; 1377 } 1378 1379 bool SystemZAsmParser::parseOperand(OperandVector &Operands, 1380 StringRef Mnemonic) { 1381 // Check if the current operand has a custom associated parser, if so, try to 1382 // custom parse the operand, or fallback to the general approach. Force all 1383 // features to be available during the operand check, or else we will fail to 1384 // find the custom parser, and then we will later get an InvalidOperand error 1385 // instead of a MissingFeature errror. 1386 FeatureBitset AvailableFeatures = getAvailableFeatures(); 1387 FeatureBitset All; 1388 All.set(); 1389 setAvailableFeatures(All); 1390 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 1391 setAvailableFeatures(AvailableFeatures); 1392 if (ResTy == MatchOperand_Success) 1393 return false; 1394 1395 // If there wasn't a custom match, try the generic matcher below. Otherwise, 1396 // there was a match, but an error occurred, in which case, just return that 1397 // the operand parsing failed. 1398 if (ResTy == MatchOperand_ParseFail) 1399 return true; 1400 1401 // Check for a register. All real register operands should have used 1402 // a context-dependent parse routine, which gives the required register 1403 // class. The code is here to mop up other cases, like those where 1404 // the instruction isn't recognized. 1405 if (Parser.getTok().is(AsmToken::Percent)) { 1406 Register Reg; 1407 if (parseRegister(Reg)) 1408 return true; 1409 Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc)); 1410 return false; 1411 } 1412 1413 // The only other type of operand is an immediate or address. As above, 1414 // real address operands should have used a context-dependent parse routine, 1415 // so we treat any plain expression as an immediate. 1416 SMLoc StartLoc = Parser.getTok().getLoc(); 1417 Register Reg1, Reg2; 1418 bool HaveReg1, HaveReg2; 1419 const MCExpr *Expr; 1420 const MCExpr *Length; 1421 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length, 1422 /*HasLength*/ true, /*HasVectorIndex*/ true)) 1423 return true; 1424 // If the register combination is not valid for any instruction, reject it. 1425 // Otherwise, fall back to reporting an unrecognized instruction. 1426 if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV 1427 && parseAddressRegister(Reg1)) 1428 return true; 1429 if (HaveReg2 && parseAddressRegister(Reg2)) 1430 return true; 1431 1432 SMLoc EndLoc = 1433 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1434 if (HaveReg1 || HaveReg2 || Length) 1435 Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc)); 1436 else 1437 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc)); 1438 return false; 1439 } 1440 1441 static std::string SystemZMnemonicSpellCheck(StringRef S, 1442 const FeatureBitset &FBS, 1443 unsigned VariantID = 0); 1444 1445 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 1446 OperandVector &Operands, 1447 MCStreamer &Out, 1448 uint64_t &ErrorInfo, 1449 bool MatchingInlineAsm) { 1450 MCInst Inst; 1451 unsigned MatchResult; 1452 1453 unsigned Dialect = getMAIAssemblerDialect(); 1454 1455 FeatureBitset MissingFeatures; 1456 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures, 1457 MatchingInlineAsm, Dialect); 1458 switch (MatchResult) { 1459 case Match_Success: 1460 Inst.setLoc(IDLoc); 1461 Out.emitInstruction(Inst, getSTI()); 1462 return false; 1463 1464 case Match_MissingFeature: { 1465 assert(MissingFeatures.any() && "Unknown missing feature!"); 1466 // Special case the error message for the very common case where only 1467 // a single subtarget feature is missing 1468 std::string Msg = "instruction requires:"; 1469 for (unsigned I = 0, E = MissingFeatures.size(); I != E; ++I) { 1470 if (MissingFeatures[I]) { 1471 Msg += " "; 1472 Msg += getSubtargetFeatureName(I); 1473 } 1474 } 1475 return Error(IDLoc, Msg); 1476 } 1477 1478 case Match_InvalidOperand: { 1479 SMLoc ErrorLoc = IDLoc; 1480 if (ErrorInfo != ~0ULL) { 1481 if (ErrorInfo >= Operands.size()) 1482 return Error(IDLoc, "too few operands for instruction"); 1483 1484 ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc(); 1485 if (ErrorLoc == SMLoc()) 1486 ErrorLoc = IDLoc; 1487 } 1488 return Error(ErrorLoc, "invalid operand for instruction"); 1489 } 1490 1491 case Match_MnemonicFail: { 1492 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); 1493 std::string Suggestion = SystemZMnemonicSpellCheck( 1494 ((SystemZOperand &)*Operands[0]).getToken(), FBS, Dialect); 1495 return Error(IDLoc, "invalid instruction" + Suggestion, 1496 ((SystemZOperand &)*Operands[0]).getLocRange()); 1497 } 1498 } 1499 1500 llvm_unreachable("Unexpected match type"); 1501 } 1502 1503 OperandMatchResultTy 1504 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal, 1505 int64_t MaxVal, bool AllowTLS) { 1506 MCContext &Ctx = getContext(); 1507 MCStreamer &Out = getStreamer(); 1508 const MCExpr *Expr; 1509 SMLoc StartLoc = Parser.getTok().getLoc(); 1510 if (getParser().parseExpression(Expr)) 1511 return MatchOperand_NoMatch; 1512 1513 auto isOutOfRangeConstant = [&](const MCExpr *E) -> bool { 1514 if (auto *CE = dyn_cast<MCConstantExpr>(E)) { 1515 int64_t Value = CE->getValue(); 1516 if ((Value & 1) || Value < MinVal || Value > MaxVal) 1517 return true; 1518 } 1519 return false; 1520 }; 1521 1522 // For consistency with the GNU assembler, treat immediates as offsets 1523 // from ".". 1524 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) { 1525 if (isOutOfRangeConstant(CE)) { 1526 Error(StartLoc, "offset out of range"); 1527 return MatchOperand_ParseFail; 1528 } 1529 int64_t Value = CE->getValue(); 1530 MCSymbol *Sym = Ctx.createTempSymbol(); 1531 Out.emitLabel(Sym); 1532 const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, 1533 Ctx); 1534 Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx); 1535 } 1536 1537 // For consistency with the GNU assembler, conservatively assume that a 1538 // constant offset must by itself be within the given size range. 1539 if (const auto *BE = dyn_cast<MCBinaryExpr>(Expr)) 1540 if (isOutOfRangeConstant(BE->getLHS()) || 1541 isOutOfRangeConstant(BE->getRHS())) { 1542 Error(StartLoc, "offset out of range"); 1543 return MatchOperand_ParseFail; 1544 } 1545 1546 // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol. 1547 const MCExpr *Sym = nullptr; 1548 if (AllowTLS && getLexer().is(AsmToken::Colon)) { 1549 Parser.Lex(); 1550 1551 if (Parser.getTok().isNot(AsmToken::Identifier)) { 1552 Error(Parser.getTok().getLoc(), "unexpected token"); 1553 return MatchOperand_ParseFail; 1554 } 1555 1556 MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None; 1557 StringRef Name = Parser.getTok().getString(); 1558 if (Name == "tls_gdcall") 1559 Kind = MCSymbolRefExpr::VK_TLSGD; 1560 else if (Name == "tls_ldcall") 1561 Kind = MCSymbolRefExpr::VK_TLSLDM; 1562 else { 1563 Error(Parser.getTok().getLoc(), "unknown TLS tag"); 1564 return MatchOperand_ParseFail; 1565 } 1566 Parser.Lex(); 1567 1568 if (Parser.getTok().isNot(AsmToken::Colon)) { 1569 Error(Parser.getTok().getLoc(), "unexpected token"); 1570 return MatchOperand_ParseFail; 1571 } 1572 Parser.Lex(); 1573 1574 if (Parser.getTok().isNot(AsmToken::Identifier)) { 1575 Error(Parser.getTok().getLoc(), "unexpected token"); 1576 return MatchOperand_ParseFail; 1577 } 1578 1579 StringRef Identifier = Parser.getTok().getString(); 1580 Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier), 1581 Kind, Ctx); 1582 Parser.Lex(); 1583 } 1584 1585 SMLoc EndLoc = 1586 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1587 1588 if (AllowTLS) 1589 Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym, 1590 StartLoc, EndLoc)); 1591 else 1592 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc)); 1593 1594 return MatchOperand_Success; 1595 } 1596 1597 // Force static initialization. 1598 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZAsmParser() { 1599 RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget()); 1600 } 1601