1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/SystemZInstPrinter.h" 10 #include "MCTargetDesc/SystemZMCTargetDesc.h" 11 #include "TargetInfo/SystemZTargetInfo.h" 12 #include "llvm/ADT/STLExtras.h" 13 #include "llvm/ADT/SmallVector.h" 14 #include "llvm/ADT/StringRef.h" 15 #include "llvm/MC/MCContext.h" 16 #include "llvm/MC/MCExpr.h" 17 #include "llvm/MC/MCInst.h" 18 #include "llvm/MC/MCInstBuilder.h" 19 #include "llvm/MC/MCParser/MCAsmLexer.h" 20 #include "llvm/MC/MCParser/MCAsmParser.h" 21 #include "llvm/MC/MCParser/MCAsmParserExtension.h" 22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 23 #include "llvm/MC/MCParser/MCTargetAsmParser.h" 24 #include "llvm/MC/MCStreamer.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/Support/Casting.h" 27 #include "llvm/Support/ErrorHandling.h" 28 #include "llvm/Support/SMLoc.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include <algorithm> 31 #include <cassert> 32 #include <cstddef> 33 #include <cstdint> 34 #include <iterator> 35 #include <memory> 36 #include <string> 37 38 using namespace llvm; 39 40 // Return true if Expr is in the range [MinValue, MaxValue]. 41 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) { 42 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) { 43 int64_t Value = CE->getValue(); 44 return Value >= MinValue && Value <= MaxValue; 45 } 46 return false; 47 } 48 49 namespace { 50 51 enum RegisterKind { 52 GR32Reg, 53 GRH32Reg, 54 GR64Reg, 55 GR128Reg, 56 ADDR32Reg, 57 ADDR64Reg, 58 FP32Reg, 59 FP64Reg, 60 FP128Reg, 61 VR32Reg, 62 VR64Reg, 63 VR128Reg, 64 AR32Reg, 65 CR64Reg, 66 }; 67 68 enum MemoryKind { 69 BDMem, 70 BDXMem, 71 BDLMem, 72 BDRMem, 73 BDVMem 74 }; 75 76 class SystemZOperand : public MCParsedAsmOperand { 77 private: 78 enum OperandKind { 79 KindInvalid, 80 KindToken, 81 KindReg, 82 KindImm, 83 KindImmTLS, 84 KindMem 85 }; 86 87 OperandKind Kind; 88 SMLoc StartLoc, EndLoc; 89 90 // A string of length Length, starting at Data. 91 struct TokenOp { 92 const char *Data; 93 unsigned Length; 94 }; 95 96 // LLVM register Num, which has kind Kind. In some ways it might be 97 // easier for this class to have a register bank (general, floating-point 98 // or access) and a raw register number (0-15). This would postpone the 99 // interpretation of the operand to the add*() methods and avoid the need 100 // for context-dependent parsing. However, we do things the current way 101 // because of the virtual getReg() method, which needs to distinguish 102 // between (say) %r0 used as a single register and %r0 used as a pair. 103 // Context-dependent parsing can also give us slightly better error 104 // messages when invalid pairs like %r1 are used. 105 struct RegOp { 106 RegisterKind Kind; 107 unsigned Num; 108 }; 109 110 // Base + Disp + Index, where Base and Index are LLVM registers or 0. 111 // MemKind says what type of memory this is and RegKind says what type 112 // the base register has (ADDR32Reg or ADDR64Reg). Length is the operand 113 // length for D(L,B)-style operands, otherwise it is null. 114 struct MemOp { 115 unsigned Base : 12; 116 unsigned Index : 12; 117 unsigned MemKind : 4; 118 unsigned RegKind : 4; 119 const MCExpr *Disp; 120 union { 121 const MCExpr *Imm; 122 unsigned Reg; 123 } Length; 124 }; 125 126 // Imm is an immediate operand, and Sym is an optional TLS symbol 127 // for use with a __tls_get_offset marker relocation. 128 struct ImmTLSOp { 129 const MCExpr *Imm; 130 const MCExpr *Sym; 131 }; 132 133 union { 134 TokenOp Token; 135 RegOp Reg; 136 const MCExpr *Imm; 137 ImmTLSOp ImmTLS; 138 MemOp Mem; 139 }; 140 141 void addExpr(MCInst &Inst, const MCExpr *Expr) const { 142 // Add as immediates when possible. Null MCExpr = 0. 143 if (!Expr) 144 Inst.addOperand(MCOperand::createImm(0)); 145 else if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) 146 Inst.addOperand(MCOperand::createImm(CE->getValue())); 147 else 148 Inst.addOperand(MCOperand::createExpr(Expr)); 149 } 150 151 public: 152 SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc) 153 : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {} 154 155 // Create particular kinds of operand. 156 static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc, 157 SMLoc EndLoc) { 158 return std::make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc); 159 } 160 161 static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) { 162 auto Op = std::make_unique<SystemZOperand>(KindToken, Loc, Loc); 163 Op->Token.Data = Str.data(); 164 Op->Token.Length = Str.size(); 165 return Op; 166 } 167 168 static std::unique_ptr<SystemZOperand> 169 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) { 170 auto Op = std::make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc); 171 Op->Reg.Kind = Kind; 172 Op->Reg.Num = Num; 173 return Op; 174 } 175 176 static std::unique_ptr<SystemZOperand> 177 createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) { 178 auto Op = std::make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc); 179 Op->Imm = Expr; 180 return Op; 181 } 182 183 static std::unique_ptr<SystemZOperand> 184 createMem(MemoryKind MemKind, RegisterKind RegKind, unsigned Base, 185 const MCExpr *Disp, unsigned Index, const MCExpr *LengthImm, 186 unsigned LengthReg, SMLoc StartLoc, SMLoc EndLoc) { 187 auto Op = std::make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc); 188 Op->Mem.MemKind = MemKind; 189 Op->Mem.RegKind = RegKind; 190 Op->Mem.Base = Base; 191 Op->Mem.Index = Index; 192 Op->Mem.Disp = Disp; 193 if (MemKind == BDLMem) 194 Op->Mem.Length.Imm = LengthImm; 195 if (MemKind == BDRMem) 196 Op->Mem.Length.Reg = LengthReg; 197 return Op; 198 } 199 200 static std::unique_ptr<SystemZOperand> 201 createImmTLS(const MCExpr *Imm, const MCExpr *Sym, 202 SMLoc StartLoc, SMLoc EndLoc) { 203 auto Op = std::make_unique<SystemZOperand>(KindImmTLS, StartLoc, EndLoc); 204 Op->ImmTLS.Imm = Imm; 205 Op->ImmTLS.Sym = Sym; 206 return Op; 207 } 208 209 // Token operands 210 bool isToken() const override { 211 return Kind == KindToken; 212 } 213 StringRef getToken() const { 214 assert(Kind == KindToken && "Not a token"); 215 return StringRef(Token.Data, Token.Length); 216 } 217 218 // Register operands. 219 bool isReg() const override { 220 return Kind == KindReg; 221 } 222 bool isReg(RegisterKind RegKind) const { 223 return Kind == KindReg && Reg.Kind == RegKind; 224 } 225 unsigned getReg() const override { 226 assert(Kind == KindReg && "Not a register"); 227 return Reg.Num; 228 } 229 230 // Immediate operands. 231 bool isImm() const override { 232 return Kind == KindImm; 233 } 234 bool isImm(int64_t MinValue, int64_t MaxValue) const { 235 return Kind == KindImm && inRange(Imm, MinValue, MaxValue); 236 } 237 const MCExpr *getImm() const { 238 assert(Kind == KindImm && "Not an immediate"); 239 return Imm; 240 } 241 242 // Immediate operands with optional TLS symbol. 243 bool isImmTLS() const { 244 return Kind == KindImmTLS; 245 } 246 247 const ImmTLSOp getImmTLS() const { 248 assert(Kind == KindImmTLS && "Not a TLS immediate"); 249 return ImmTLS; 250 } 251 252 // Memory operands. 253 bool isMem() const override { 254 return Kind == KindMem; 255 } 256 bool isMem(MemoryKind MemKind) const { 257 return (Kind == KindMem && 258 (Mem.MemKind == MemKind || 259 // A BDMem can be treated as a BDXMem in which the index 260 // register field is 0. 261 (Mem.MemKind == BDMem && MemKind == BDXMem))); 262 } 263 bool isMem(MemoryKind MemKind, RegisterKind RegKind) const { 264 return isMem(MemKind) && Mem.RegKind == RegKind; 265 } 266 bool isMemDisp12(MemoryKind MemKind, RegisterKind RegKind) const { 267 return isMem(MemKind, RegKind) && inRange(Mem.Disp, 0, 0xfff); 268 } 269 bool isMemDisp20(MemoryKind MemKind, RegisterKind RegKind) const { 270 return isMem(MemKind, RegKind) && inRange(Mem.Disp, -524288, 524287); 271 } 272 bool isMemDisp12Len4(RegisterKind RegKind) const { 273 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x10); 274 } 275 bool isMemDisp12Len8(RegisterKind RegKind) const { 276 return isMemDisp12(BDLMem, RegKind) && inRange(Mem.Length.Imm, 1, 0x100); 277 } 278 279 const MemOp& getMem() const { 280 assert(Kind == KindMem && "Not a Mem operand"); 281 return Mem; 282 } 283 284 // Override MCParsedAsmOperand. 285 SMLoc getStartLoc() const override { return StartLoc; } 286 SMLoc getEndLoc() const override { return EndLoc; } 287 void print(raw_ostream &OS) const override; 288 289 /// getLocRange - Get the range between the first and last token of this 290 /// operand. 291 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 292 293 // Used by the TableGen code to add particular types of operand 294 // to an instruction. 295 void addRegOperands(MCInst &Inst, unsigned N) const { 296 assert(N == 1 && "Invalid number of operands"); 297 Inst.addOperand(MCOperand::createReg(getReg())); 298 } 299 void addImmOperands(MCInst &Inst, unsigned N) const { 300 assert(N == 1 && "Invalid number of operands"); 301 addExpr(Inst, getImm()); 302 } 303 void addBDAddrOperands(MCInst &Inst, unsigned N) const { 304 assert(N == 2 && "Invalid number of operands"); 305 assert(isMem(BDMem) && "Invalid operand type"); 306 Inst.addOperand(MCOperand::createReg(Mem.Base)); 307 addExpr(Inst, Mem.Disp); 308 } 309 void addBDXAddrOperands(MCInst &Inst, unsigned N) const { 310 assert(N == 3 && "Invalid number of operands"); 311 assert(isMem(BDXMem) && "Invalid operand type"); 312 Inst.addOperand(MCOperand::createReg(Mem.Base)); 313 addExpr(Inst, Mem.Disp); 314 Inst.addOperand(MCOperand::createReg(Mem.Index)); 315 } 316 void addBDLAddrOperands(MCInst &Inst, unsigned N) const { 317 assert(N == 3 && "Invalid number of operands"); 318 assert(isMem(BDLMem) && "Invalid operand type"); 319 Inst.addOperand(MCOperand::createReg(Mem.Base)); 320 addExpr(Inst, Mem.Disp); 321 addExpr(Inst, Mem.Length.Imm); 322 } 323 void addBDRAddrOperands(MCInst &Inst, unsigned N) const { 324 assert(N == 3 && "Invalid number of operands"); 325 assert(isMem(BDRMem) && "Invalid operand type"); 326 Inst.addOperand(MCOperand::createReg(Mem.Base)); 327 addExpr(Inst, Mem.Disp); 328 Inst.addOperand(MCOperand::createReg(Mem.Length.Reg)); 329 } 330 void addBDVAddrOperands(MCInst &Inst, unsigned N) const { 331 assert(N == 3 && "Invalid number of operands"); 332 assert(isMem(BDVMem) && "Invalid operand type"); 333 Inst.addOperand(MCOperand::createReg(Mem.Base)); 334 addExpr(Inst, Mem.Disp); 335 Inst.addOperand(MCOperand::createReg(Mem.Index)); 336 } 337 void addImmTLSOperands(MCInst &Inst, unsigned N) const { 338 assert(N == 2 && "Invalid number of operands"); 339 assert(Kind == KindImmTLS && "Invalid operand type"); 340 addExpr(Inst, ImmTLS.Imm); 341 if (ImmTLS.Sym) 342 addExpr(Inst, ImmTLS.Sym); 343 } 344 345 // Used by the TableGen code to check for particular operand types. 346 bool isGR32() const { return isReg(GR32Reg); } 347 bool isGRH32() const { return isReg(GRH32Reg); } 348 bool isGRX32() const { return false; } 349 bool isGR64() const { return isReg(GR64Reg); } 350 bool isGR128() const { return isReg(GR128Reg); } 351 bool isADDR32() const { return isReg(ADDR32Reg); } 352 bool isADDR64() const { return isReg(ADDR64Reg); } 353 bool isADDR128() const { return false; } 354 bool isFP32() const { return isReg(FP32Reg); } 355 bool isFP64() const { return isReg(FP64Reg); } 356 bool isFP128() const { return isReg(FP128Reg); } 357 bool isVR32() const { return isReg(VR32Reg); } 358 bool isVR64() const { return isReg(VR64Reg); } 359 bool isVF128() const { return false; } 360 bool isVR128() const { return isReg(VR128Reg); } 361 bool isAR32() const { return isReg(AR32Reg); } 362 bool isCR64() const { return isReg(CR64Reg); } 363 bool isAnyReg() const { return (isReg() || isImm(0, 15)); } 364 bool isBDAddr32Disp12() const { return isMemDisp12(BDMem, ADDR32Reg); } 365 bool isBDAddr32Disp20() const { return isMemDisp20(BDMem, ADDR32Reg); } 366 bool isBDAddr64Disp12() const { return isMemDisp12(BDMem, ADDR64Reg); } 367 bool isBDAddr64Disp20() const { return isMemDisp20(BDMem, ADDR64Reg); } 368 bool isBDXAddr64Disp12() const { return isMemDisp12(BDXMem, ADDR64Reg); } 369 bool isBDXAddr64Disp20() const { return isMemDisp20(BDXMem, ADDR64Reg); } 370 bool isBDLAddr64Disp12Len4() const { return isMemDisp12Len4(ADDR64Reg); } 371 bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); } 372 bool isBDRAddr64Disp12() const { return isMemDisp12(BDRMem, ADDR64Reg); } 373 bool isBDVAddr64Disp12() const { return isMemDisp12(BDVMem, ADDR64Reg); } 374 bool isU1Imm() const { return isImm(0, 1); } 375 bool isU2Imm() const { return isImm(0, 3); } 376 bool isU3Imm() const { return isImm(0, 7); } 377 bool isU4Imm() const { return isImm(0, 15); } 378 bool isU6Imm() const { return isImm(0, 63); } 379 bool isU8Imm() const { return isImm(0, 255); } 380 bool isS8Imm() const { return isImm(-128, 127); } 381 bool isU12Imm() const { return isImm(0, 4095); } 382 bool isU16Imm() const { return isImm(0, 65535); } 383 bool isS16Imm() const { return isImm(-32768, 32767); } 384 bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); } 385 bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); } 386 bool isU48Imm() const { return isImm(0, (1LL << 48) - 1); } 387 }; 388 389 class SystemZAsmParser : public MCTargetAsmParser { 390 #define GET_ASSEMBLER_HEADER 391 #include "SystemZGenAsmMatcher.inc" 392 393 private: 394 MCAsmParser &Parser; 395 enum RegisterGroup { 396 RegGR, 397 RegFP, 398 RegV, 399 RegAR, 400 RegCR 401 }; 402 struct Register { 403 RegisterGroup Group; 404 unsigned Num; 405 SMLoc StartLoc, EndLoc; 406 }; 407 408 bool parseRegister(Register &Reg, bool RestoreOnFailure = false); 409 410 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs, 411 bool IsAddress = false); 412 413 OperandMatchResultTy parseRegister(OperandVector &Operands, 414 RegisterGroup Group, const unsigned *Regs, 415 RegisterKind Kind); 416 417 OperandMatchResultTy parseAnyRegister(OperandVector &Operands); 418 419 bool parseAddress(bool &HaveReg1, Register &Reg1, 420 bool &HaveReg2, Register &Reg2, 421 const MCExpr *&Disp, const MCExpr *&Length); 422 bool parseAddressRegister(Register &Reg); 423 424 bool ParseDirectiveInsn(SMLoc L); 425 426 OperandMatchResultTy parseAddress(OperandVector &Operands, 427 MemoryKind MemKind, const unsigned *Regs, 428 RegisterKind RegKind); 429 430 OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal, 431 int64_t MaxVal, bool AllowTLS); 432 433 bool parseOperand(OperandVector &Operands, StringRef Mnemonic); 434 435 public: 436 SystemZAsmParser(const MCSubtargetInfo &sti, MCAsmParser &parser, 437 const MCInstrInfo &MII, 438 const MCTargetOptions &Options) 439 : MCTargetAsmParser(Options, sti, MII), Parser(parser) { 440 MCAsmParserExtension::Initialize(Parser); 441 442 // Alias the .word directive to .short. 443 parser.addAliasForDirective(".word", ".short"); 444 445 // Initialize the set of available features. 446 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits())); 447 } 448 449 // Override MCTargetAsmParser. 450 bool ParseDirective(AsmToken DirectiveID) override; 451 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 452 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc, 453 bool RestoreOnFailure); 454 OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, 455 SMLoc &EndLoc) override; 456 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 457 SMLoc NameLoc, OperandVector &Operands) override; 458 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 459 OperandVector &Operands, MCStreamer &Out, 460 uint64_t &ErrorInfo, 461 bool MatchingInlineAsm) override; 462 463 // Used by the TableGen code to parse particular operand types. 464 OperandMatchResultTy parseGR32(OperandVector &Operands) { 465 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg); 466 } 467 OperandMatchResultTy parseGRH32(OperandVector &Operands) { 468 return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg); 469 } 470 OperandMatchResultTy parseGRX32(OperandVector &Operands) { 471 llvm_unreachable("GRX32 should only be used for pseudo instructions"); 472 } 473 OperandMatchResultTy parseGR64(OperandVector &Operands) { 474 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg); 475 } 476 OperandMatchResultTy parseGR128(OperandVector &Operands) { 477 return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg); 478 } 479 OperandMatchResultTy parseADDR32(OperandVector &Operands) { 480 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg); 481 } 482 OperandMatchResultTy parseADDR64(OperandVector &Operands) { 483 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg); 484 } 485 OperandMatchResultTy parseADDR128(OperandVector &Operands) { 486 llvm_unreachable("Shouldn't be used as an operand"); 487 } 488 OperandMatchResultTy parseFP32(OperandVector &Operands) { 489 return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg); 490 } 491 OperandMatchResultTy parseFP64(OperandVector &Operands) { 492 return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg); 493 } 494 OperandMatchResultTy parseFP128(OperandVector &Operands) { 495 return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg); 496 } 497 OperandMatchResultTy parseVR32(OperandVector &Operands) { 498 return parseRegister(Operands, RegV, SystemZMC::VR32Regs, VR32Reg); 499 } 500 OperandMatchResultTy parseVR64(OperandVector &Operands) { 501 return parseRegister(Operands, RegV, SystemZMC::VR64Regs, VR64Reg); 502 } 503 OperandMatchResultTy parseVF128(OperandVector &Operands) { 504 llvm_unreachable("Shouldn't be used as an operand"); 505 } 506 OperandMatchResultTy parseVR128(OperandVector &Operands) { 507 return parseRegister(Operands, RegV, SystemZMC::VR128Regs, VR128Reg); 508 } 509 OperandMatchResultTy parseAR32(OperandVector &Operands) { 510 return parseRegister(Operands, RegAR, SystemZMC::AR32Regs, AR32Reg); 511 } 512 OperandMatchResultTy parseCR64(OperandVector &Operands) { 513 return parseRegister(Operands, RegCR, SystemZMC::CR64Regs, CR64Reg); 514 } 515 OperandMatchResultTy parseAnyReg(OperandVector &Operands) { 516 return parseAnyRegister(Operands); 517 } 518 OperandMatchResultTy parseBDAddr32(OperandVector &Operands) { 519 return parseAddress(Operands, BDMem, SystemZMC::GR32Regs, ADDR32Reg); 520 } 521 OperandMatchResultTy parseBDAddr64(OperandVector &Operands) { 522 return parseAddress(Operands, BDMem, SystemZMC::GR64Regs, ADDR64Reg); 523 } 524 OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) { 525 return parseAddress(Operands, BDXMem, SystemZMC::GR64Regs, ADDR64Reg); 526 } 527 OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) { 528 return parseAddress(Operands, BDLMem, SystemZMC::GR64Regs, ADDR64Reg); 529 } 530 OperandMatchResultTy parseBDRAddr64(OperandVector &Operands) { 531 return parseAddress(Operands, BDRMem, SystemZMC::GR64Regs, ADDR64Reg); 532 } 533 OperandMatchResultTy parseBDVAddr64(OperandVector &Operands) { 534 return parseAddress(Operands, BDVMem, SystemZMC::GR64Regs, ADDR64Reg); 535 } 536 OperandMatchResultTy parsePCRel12(OperandVector &Operands) { 537 return parsePCRel(Operands, -(1LL << 12), (1LL << 12) - 1, false); 538 } 539 OperandMatchResultTy parsePCRel16(OperandVector &Operands) { 540 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, false); 541 } 542 OperandMatchResultTy parsePCRel24(OperandVector &Operands) { 543 return parsePCRel(Operands, -(1LL << 24), (1LL << 24) - 1, false); 544 } 545 OperandMatchResultTy parsePCRel32(OperandVector &Operands) { 546 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, false); 547 } 548 OperandMatchResultTy parsePCRelTLS16(OperandVector &Operands) { 549 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1, true); 550 } 551 OperandMatchResultTy parsePCRelTLS32(OperandVector &Operands) { 552 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1, true); 553 } 554 }; 555 556 } // end anonymous namespace 557 558 #define GET_REGISTER_MATCHER 559 #define GET_SUBTARGET_FEATURE_NAME 560 #define GET_MATCHER_IMPLEMENTATION 561 #define GET_MNEMONIC_SPELL_CHECKER 562 #include "SystemZGenAsmMatcher.inc" 563 564 // Used for the .insn directives; contains information needed to parse the 565 // operands in the directive. 566 struct InsnMatchEntry { 567 StringRef Format; 568 uint64_t Opcode; 569 int32_t NumOperands; 570 MatchClassKind OperandKinds[5]; 571 }; 572 573 // For equal_range comparison. 574 struct CompareInsn { 575 bool operator() (const InsnMatchEntry &LHS, StringRef RHS) { 576 return LHS.Format < RHS; 577 } 578 bool operator() (StringRef LHS, const InsnMatchEntry &RHS) { 579 return LHS < RHS.Format; 580 } 581 bool operator() (const InsnMatchEntry &LHS, const InsnMatchEntry &RHS) { 582 return LHS.Format < RHS.Format; 583 } 584 }; 585 586 // Table initializing information for parsing the .insn directive. 587 static struct InsnMatchEntry InsnMatchTable[] = { 588 /* Format, Opcode, NumOperands, OperandKinds */ 589 { "e", SystemZ::InsnE, 1, 590 { MCK_U16Imm } }, 591 { "ri", SystemZ::InsnRI, 3, 592 { MCK_U32Imm, MCK_AnyReg, MCK_S16Imm } }, 593 { "rie", SystemZ::InsnRIE, 4, 594 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } }, 595 { "ril", SystemZ::InsnRIL, 3, 596 { MCK_U48Imm, MCK_AnyReg, MCK_PCRel32 } }, 597 { "rilu", SystemZ::InsnRILU, 3, 598 { MCK_U48Imm, MCK_AnyReg, MCK_U32Imm } }, 599 { "ris", SystemZ::InsnRIS, 5, 600 { MCK_U48Imm, MCK_AnyReg, MCK_S8Imm, MCK_U4Imm, MCK_BDAddr64Disp12 } }, 601 { "rr", SystemZ::InsnRR, 3, 602 { MCK_U16Imm, MCK_AnyReg, MCK_AnyReg } }, 603 { "rre", SystemZ::InsnRRE, 3, 604 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg } }, 605 { "rrf", SystemZ::InsnRRF, 5, 606 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm } }, 607 { "rrs", SystemZ::InsnRRS, 5, 608 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_U4Imm, MCK_BDAddr64Disp12 } }, 609 { "rs", SystemZ::InsnRS, 4, 610 { MCK_U32Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } }, 611 { "rse", SystemZ::InsnRSE, 4, 612 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp12 } }, 613 { "rsi", SystemZ::InsnRSI, 4, 614 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_PCRel16 } }, 615 { "rsy", SystemZ::InsnRSY, 4, 616 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDAddr64Disp20 } }, 617 { "rx", SystemZ::InsnRX, 3, 618 { MCK_U32Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } }, 619 { "rxe", SystemZ::InsnRXE, 3, 620 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp12 } }, 621 { "rxf", SystemZ::InsnRXF, 4, 622 { MCK_U48Imm, MCK_AnyReg, MCK_AnyReg, MCK_BDXAddr64Disp12 } }, 623 { "rxy", SystemZ::InsnRXY, 3, 624 { MCK_U48Imm, MCK_AnyReg, MCK_BDXAddr64Disp20 } }, 625 { "s", SystemZ::InsnS, 2, 626 { MCK_U32Imm, MCK_BDAddr64Disp12 } }, 627 { "si", SystemZ::InsnSI, 3, 628 { MCK_U32Imm, MCK_BDAddr64Disp12, MCK_S8Imm } }, 629 { "sil", SystemZ::InsnSIL, 3, 630 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_U16Imm } }, 631 { "siy", SystemZ::InsnSIY, 3, 632 { MCK_U48Imm, MCK_BDAddr64Disp20, MCK_U8Imm } }, 633 { "ss", SystemZ::InsnSS, 4, 634 { MCK_U48Imm, MCK_BDXAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } }, 635 { "sse", SystemZ::InsnSSE, 3, 636 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12 } }, 637 { "ssf", SystemZ::InsnSSF, 4, 638 { MCK_U48Imm, MCK_BDAddr64Disp12, MCK_BDAddr64Disp12, MCK_AnyReg } } 639 }; 640 641 static void printMCExpr(const MCExpr *E, raw_ostream &OS) { 642 if (!E) 643 return; 644 if (auto *CE = dyn_cast<MCConstantExpr>(E)) 645 OS << *CE; 646 else if (auto *UE = dyn_cast<MCUnaryExpr>(E)) 647 OS << *UE; 648 else if (auto *BE = dyn_cast<MCBinaryExpr>(E)) 649 OS << *BE; 650 else if (auto *SRE = dyn_cast<MCSymbolRefExpr>(E)) 651 OS << *SRE; 652 else 653 OS << *E; 654 } 655 656 void SystemZOperand::print(raw_ostream &OS) const { 657 switch (Kind) { 658 case KindToken: 659 OS << "Token:" << getToken(); 660 break; 661 case KindReg: 662 OS << "Reg:" << SystemZInstPrinter::getRegisterName(getReg()); 663 break; 664 case KindImm: 665 OS << "Imm:"; 666 printMCExpr(getImm(), OS); 667 break; 668 case KindImmTLS: 669 OS << "ImmTLS:"; 670 printMCExpr(getImmTLS().Imm, OS); 671 if (getImmTLS().Sym) { 672 OS << ", "; 673 printMCExpr(getImmTLS().Sym, OS); 674 } 675 break; 676 case KindMem: { 677 const MemOp &Op = getMem(); 678 OS << "Mem:" << *cast<MCConstantExpr>(Op.Disp); 679 if (Op.Base) { 680 OS << "("; 681 if (Op.MemKind == BDLMem) 682 OS << *cast<MCConstantExpr>(Op.Length.Imm) << ","; 683 else if (Op.MemKind == BDRMem) 684 OS << SystemZInstPrinter::getRegisterName(Op.Length.Reg) << ","; 685 if (Op.Index) 686 OS << SystemZInstPrinter::getRegisterName(Op.Index) << ","; 687 OS << SystemZInstPrinter::getRegisterName(Op.Base); 688 OS << ")"; 689 } 690 break; 691 } 692 case KindInvalid: 693 break; 694 } 695 } 696 697 // Parse one register of the form %<prefix><number>. 698 bool SystemZAsmParser::parseRegister(Register &Reg, bool RestoreOnFailure) { 699 Reg.StartLoc = Parser.getTok().getLoc(); 700 701 // Eat the % prefix. 702 if (Parser.getTok().isNot(AsmToken::Percent)) 703 return Error(Parser.getTok().getLoc(), "register expected"); 704 const AsmToken &PercentTok = Parser.getTok(); 705 Parser.Lex(); 706 707 // Expect a register name. 708 if (Parser.getTok().isNot(AsmToken::Identifier)) { 709 if (RestoreOnFailure) 710 getLexer().UnLex(PercentTok); 711 return Error(Reg.StartLoc, "invalid register"); 712 } 713 714 // Check that there's a prefix. 715 StringRef Name = Parser.getTok().getString(); 716 if (Name.size() < 2) { 717 if (RestoreOnFailure) 718 getLexer().UnLex(PercentTok); 719 return Error(Reg.StartLoc, "invalid register"); 720 } 721 char Prefix = Name[0]; 722 723 // Treat the rest of the register name as a register number. 724 if (Name.substr(1).getAsInteger(10, Reg.Num)) { 725 if (RestoreOnFailure) 726 getLexer().UnLex(PercentTok); 727 return Error(Reg.StartLoc, "invalid register"); 728 } 729 730 // Look for valid combinations of prefix and number. 731 if (Prefix == 'r' && Reg.Num < 16) 732 Reg.Group = RegGR; 733 else if (Prefix == 'f' && Reg.Num < 16) 734 Reg.Group = RegFP; 735 else if (Prefix == 'v' && Reg.Num < 32) 736 Reg.Group = RegV; 737 else if (Prefix == 'a' && Reg.Num < 16) 738 Reg.Group = RegAR; 739 else if (Prefix == 'c' && Reg.Num < 16) 740 Reg.Group = RegCR; 741 else { 742 if (RestoreOnFailure) 743 getLexer().UnLex(PercentTok); 744 return Error(Reg.StartLoc, "invalid register"); 745 } 746 747 Reg.EndLoc = Parser.getTok().getLoc(); 748 Parser.Lex(); 749 return false; 750 } 751 752 // Parse a register of group Group. If Regs is nonnull, use it to map 753 // the raw register number to LLVM numbering, with zero entries 754 // indicating an invalid register. IsAddress says whether the 755 // register appears in an address context. Allow FP Group if expecting 756 // RegV Group, since the f-prefix yields the FP group even while used 757 // with vector instructions. 758 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group, 759 const unsigned *Regs, bool IsAddress) { 760 if (parseRegister(Reg)) 761 return true; 762 if (Reg.Group != Group && !(Reg.Group == RegFP && Group == RegV)) 763 return Error(Reg.StartLoc, "invalid operand for instruction"); 764 if (Regs && Regs[Reg.Num] == 0) 765 return Error(Reg.StartLoc, "invalid register pair"); 766 if (Reg.Num == 0 && IsAddress) 767 return Error(Reg.StartLoc, "%r0 used in an address"); 768 if (Regs) 769 Reg.Num = Regs[Reg.Num]; 770 return false; 771 } 772 773 // Parse a register and add it to Operands. The other arguments are as above. 774 OperandMatchResultTy 775 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group, 776 const unsigned *Regs, RegisterKind Kind) { 777 if (Parser.getTok().isNot(AsmToken::Percent)) 778 return MatchOperand_NoMatch; 779 780 Register Reg; 781 bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg); 782 if (parseRegister(Reg, Group, Regs, IsAddress)) 783 return MatchOperand_ParseFail; 784 785 Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num, 786 Reg.StartLoc, Reg.EndLoc)); 787 return MatchOperand_Success; 788 } 789 790 // Parse any type of register (including integers) and add it to Operands. 791 OperandMatchResultTy 792 SystemZAsmParser::parseAnyRegister(OperandVector &Operands) { 793 // Handle integer values. 794 if (Parser.getTok().is(AsmToken::Integer)) { 795 const MCExpr *Register; 796 SMLoc StartLoc = Parser.getTok().getLoc(); 797 if (Parser.parseExpression(Register)) 798 return MatchOperand_ParseFail; 799 800 if (auto *CE = dyn_cast<MCConstantExpr>(Register)) { 801 int64_t Value = CE->getValue(); 802 if (Value < 0 || Value > 15) { 803 Error(StartLoc, "invalid register"); 804 return MatchOperand_ParseFail; 805 } 806 } 807 808 SMLoc EndLoc = 809 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 810 811 Operands.push_back(SystemZOperand::createImm(Register, StartLoc, EndLoc)); 812 } 813 else { 814 Register Reg; 815 if (parseRegister(Reg)) 816 return MatchOperand_ParseFail; 817 818 // Map to the correct register kind. 819 RegisterKind Kind; 820 unsigned RegNo; 821 if (Reg.Group == RegGR) { 822 Kind = GR64Reg; 823 RegNo = SystemZMC::GR64Regs[Reg.Num]; 824 } 825 else if (Reg.Group == RegFP) { 826 Kind = FP64Reg; 827 RegNo = SystemZMC::FP64Regs[Reg.Num]; 828 } 829 else if (Reg.Group == RegV) { 830 Kind = VR128Reg; 831 RegNo = SystemZMC::VR128Regs[Reg.Num]; 832 } 833 else if (Reg.Group == RegAR) { 834 Kind = AR32Reg; 835 RegNo = SystemZMC::AR32Regs[Reg.Num]; 836 } 837 else if (Reg.Group == RegCR) { 838 Kind = CR64Reg; 839 RegNo = SystemZMC::CR64Regs[Reg.Num]; 840 } 841 else { 842 return MatchOperand_ParseFail; 843 } 844 845 Operands.push_back(SystemZOperand::createReg(Kind, RegNo, 846 Reg.StartLoc, Reg.EndLoc)); 847 } 848 return MatchOperand_Success; 849 } 850 851 // Parse a memory operand into Reg1, Reg2, Disp, and Length. 852 bool SystemZAsmParser::parseAddress(bool &HaveReg1, Register &Reg1, 853 bool &HaveReg2, Register &Reg2, 854 const MCExpr *&Disp, 855 const MCExpr *&Length) { 856 // Parse the displacement, which must always be present. 857 if (getParser().parseExpression(Disp)) 858 return true; 859 860 // Parse the optional base and index. 861 HaveReg1 = false; 862 HaveReg2 = false; 863 Length = nullptr; 864 if (getLexer().is(AsmToken::LParen)) { 865 Parser.Lex(); 866 867 if (getLexer().is(AsmToken::Percent)) { 868 // Parse the first register. 869 HaveReg1 = true; 870 if (parseRegister(Reg1)) 871 return true; 872 } else { 873 // Parse the length. 874 if (getParser().parseExpression(Length)) 875 return true; 876 } 877 878 // Check whether there's a second register. 879 if (getLexer().is(AsmToken::Comma)) { 880 Parser.Lex(); 881 HaveReg2 = true; 882 if (parseRegister(Reg2)) 883 return true; 884 } 885 886 // Consume the closing bracket. 887 if (getLexer().isNot(AsmToken::RParen)) 888 return Error(Parser.getTok().getLoc(), "unexpected token in address"); 889 Parser.Lex(); 890 } 891 return false; 892 } 893 894 // Verify that Reg is a valid address register (base or index). 895 bool 896 SystemZAsmParser::parseAddressRegister(Register &Reg) { 897 if (Reg.Group == RegV) { 898 Error(Reg.StartLoc, "invalid use of vector addressing"); 899 return true; 900 } else if (Reg.Group != RegGR) { 901 Error(Reg.StartLoc, "invalid address register"); 902 return true; 903 } else if (Reg.Num == 0) { 904 Error(Reg.StartLoc, "%r0 used in an address"); 905 return true; 906 } 907 return false; 908 } 909 910 // Parse a memory operand and add it to Operands. The other arguments 911 // are as above. 912 OperandMatchResultTy 913 SystemZAsmParser::parseAddress(OperandVector &Operands, MemoryKind MemKind, 914 const unsigned *Regs, RegisterKind RegKind) { 915 SMLoc StartLoc = Parser.getTok().getLoc(); 916 unsigned Base = 0, Index = 0, LengthReg = 0; 917 Register Reg1, Reg2; 918 bool HaveReg1, HaveReg2; 919 const MCExpr *Disp; 920 const MCExpr *Length; 921 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Disp, Length)) 922 return MatchOperand_ParseFail; 923 924 switch (MemKind) { 925 case BDMem: 926 // If we have Reg1, it must be an address register. 927 if (HaveReg1) { 928 if (parseAddressRegister(Reg1)) 929 return MatchOperand_ParseFail; 930 Base = Regs[Reg1.Num]; 931 } 932 // There must be no Reg2 or length. 933 if (Length) { 934 Error(StartLoc, "invalid use of length addressing"); 935 return MatchOperand_ParseFail; 936 } 937 if (HaveReg2) { 938 Error(StartLoc, "invalid use of indexed addressing"); 939 return MatchOperand_ParseFail; 940 } 941 break; 942 case BDXMem: 943 // If we have Reg1, it must be an address register. 944 if (HaveReg1) { 945 if (parseAddressRegister(Reg1)) 946 return MatchOperand_ParseFail; 947 // If the are two registers, the first one is the index and the 948 // second is the base. 949 if (HaveReg2) 950 Index = Regs[Reg1.Num]; 951 else 952 Base = Regs[Reg1.Num]; 953 } 954 // If we have Reg2, it must be an address register. 955 if (HaveReg2) { 956 if (parseAddressRegister(Reg2)) 957 return MatchOperand_ParseFail; 958 Base = Regs[Reg2.Num]; 959 } 960 // There must be no length. 961 if (Length) { 962 Error(StartLoc, "invalid use of length addressing"); 963 return MatchOperand_ParseFail; 964 } 965 break; 966 case BDLMem: 967 // If we have Reg2, it must be an address register. 968 if (HaveReg2) { 969 if (parseAddressRegister(Reg2)) 970 return MatchOperand_ParseFail; 971 Base = Regs[Reg2.Num]; 972 } 973 // We cannot support base+index addressing. 974 if (HaveReg1 && HaveReg2) { 975 Error(StartLoc, "invalid use of indexed addressing"); 976 return MatchOperand_ParseFail; 977 } 978 // We must have a length. 979 if (!Length) { 980 Error(StartLoc, "missing length in address"); 981 return MatchOperand_ParseFail; 982 } 983 break; 984 case BDRMem: 985 // We must have Reg1, and it must be a GPR. 986 if (!HaveReg1 || Reg1.Group != RegGR) { 987 Error(StartLoc, "invalid operand for instruction"); 988 return MatchOperand_ParseFail; 989 } 990 LengthReg = SystemZMC::GR64Regs[Reg1.Num]; 991 // If we have Reg2, it must be an address register. 992 if (HaveReg2) { 993 if (parseAddressRegister(Reg2)) 994 return MatchOperand_ParseFail; 995 Base = Regs[Reg2.Num]; 996 } 997 // There must be no length. 998 if (Length) { 999 Error(StartLoc, "invalid use of length addressing"); 1000 return MatchOperand_ParseFail; 1001 } 1002 break; 1003 case BDVMem: 1004 // We must have Reg1, and it must be a vector register. 1005 if (!HaveReg1 || Reg1.Group != RegV) { 1006 Error(StartLoc, "vector index required in address"); 1007 return MatchOperand_ParseFail; 1008 } 1009 Index = SystemZMC::VR128Regs[Reg1.Num]; 1010 // If we have Reg2, it must be an address register. 1011 if (HaveReg2) { 1012 if (parseAddressRegister(Reg2)) 1013 return MatchOperand_ParseFail; 1014 Base = Regs[Reg2.Num]; 1015 } 1016 // There must be no length. 1017 if (Length) { 1018 Error(StartLoc, "invalid use of length addressing"); 1019 return MatchOperand_ParseFail; 1020 } 1021 break; 1022 } 1023 1024 SMLoc EndLoc = 1025 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1026 Operands.push_back(SystemZOperand::createMem(MemKind, RegKind, Base, Disp, 1027 Index, Length, LengthReg, 1028 StartLoc, EndLoc)); 1029 return MatchOperand_Success; 1030 } 1031 1032 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) { 1033 StringRef IDVal = DirectiveID.getIdentifier(); 1034 1035 if (IDVal == ".insn") 1036 return ParseDirectiveInsn(DirectiveID.getLoc()); 1037 1038 return true; 1039 } 1040 1041 /// ParseDirectiveInsn 1042 /// ::= .insn [ format, encoding, (operands (, operands)*) ] 1043 bool SystemZAsmParser::ParseDirectiveInsn(SMLoc L) { 1044 MCAsmParser &Parser = getParser(); 1045 1046 // Expect instruction format as identifier. 1047 StringRef Format; 1048 SMLoc ErrorLoc = Parser.getTok().getLoc(); 1049 if (Parser.parseIdentifier(Format)) 1050 return Error(ErrorLoc, "expected instruction format"); 1051 1052 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 8> Operands; 1053 1054 // Find entry for this format in InsnMatchTable. 1055 auto EntryRange = 1056 std::equal_range(std::begin(InsnMatchTable), std::end(InsnMatchTable), 1057 Format, CompareInsn()); 1058 1059 // If first == second, couldn't find a match in the table. 1060 if (EntryRange.first == EntryRange.second) 1061 return Error(ErrorLoc, "unrecognized format"); 1062 1063 struct InsnMatchEntry *Entry = EntryRange.first; 1064 1065 // Format should match from equal_range. 1066 assert(Entry->Format == Format); 1067 1068 // Parse the following operands using the table's information. 1069 for (int i = 0; i < Entry->NumOperands; i++) { 1070 MatchClassKind Kind = Entry->OperandKinds[i]; 1071 1072 SMLoc StartLoc = Parser.getTok().getLoc(); 1073 1074 // Always expect commas as separators for operands. 1075 if (getLexer().isNot(AsmToken::Comma)) 1076 return Error(StartLoc, "unexpected token in directive"); 1077 Lex(); 1078 1079 // Parse operands. 1080 OperandMatchResultTy ResTy; 1081 if (Kind == MCK_AnyReg) 1082 ResTy = parseAnyReg(Operands); 1083 else if (Kind == MCK_BDXAddr64Disp12 || Kind == MCK_BDXAddr64Disp20) 1084 ResTy = parseBDXAddr64(Operands); 1085 else if (Kind == MCK_BDAddr64Disp12 || Kind == MCK_BDAddr64Disp20) 1086 ResTy = parseBDAddr64(Operands); 1087 else if (Kind == MCK_PCRel32) 1088 ResTy = parsePCRel32(Operands); 1089 else if (Kind == MCK_PCRel16) 1090 ResTy = parsePCRel16(Operands); 1091 else { 1092 // Only remaining operand kind is an immediate. 1093 const MCExpr *Expr; 1094 SMLoc StartLoc = Parser.getTok().getLoc(); 1095 1096 // Expect immediate expression. 1097 if (Parser.parseExpression(Expr)) 1098 return Error(StartLoc, "unexpected token in directive"); 1099 1100 SMLoc EndLoc = 1101 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1102 1103 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc)); 1104 ResTy = MatchOperand_Success; 1105 } 1106 1107 if (ResTy != MatchOperand_Success) 1108 return true; 1109 } 1110 1111 // Build the instruction with the parsed operands. 1112 MCInst Inst = MCInstBuilder(Entry->Opcode); 1113 1114 for (size_t i = 0; i < Operands.size(); i++) { 1115 MCParsedAsmOperand &Operand = *Operands[i]; 1116 MatchClassKind Kind = Entry->OperandKinds[i]; 1117 1118 // Verify operand. 1119 unsigned Res = validateOperandClass(Operand, Kind); 1120 if (Res != Match_Success) 1121 return Error(Operand.getStartLoc(), "unexpected operand type"); 1122 1123 // Add operands to instruction. 1124 SystemZOperand &ZOperand = static_cast<SystemZOperand &>(Operand); 1125 if (ZOperand.isReg()) 1126 ZOperand.addRegOperands(Inst, 1); 1127 else if (ZOperand.isMem(BDMem)) 1128 ZOperand.addBDAddrOperands(Inst, 2); 1129 else if (ZOperand.isMem(BDXMem)) 1130 ZOperand.addBDXAddrOperands(Inst, 3); 1131 else if (ZOperand.isImm()) 1132 ZOperand.addImmOperands(Inst, 1); 1133 else 1134 llvm_unreachable("unexpected operand type"); 1135 } 1136 1137 // Emit as a regular instruction. 1138 Parser.getStreamer().EmitInstruction(Inst, getSTI()); 1139 1140 return false; 1141 } 1142 1143 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, 1144 SMLoc &EndLoc, bool RestoreOnFailure) { 1145 Register Reg; 1146 if (parseRegister(Reg, RestoreOnFailure)) 1147 return true; 1148 if (Reg.Group == RegGR) 1149 RegNo = SystemZMC::GR64Regs[Reg.Num]; 1150 else if (Reg.Group == RegFP) 1151 RegNo = SystemZMC::FP64Regs[Reg.Num]; 1152 else if (Reg.Group == RegV) 1153 RegNo = SystemZMC::VR128Regs[Reg.Num]; 1154 else if (Reg.Group == RegAR) 1155 RegNo = SystemZMC::AR32Regs[Reg.Num]; 1156 else if (Reg.Group == RegCR) 1157 RegNo = SystemZMC::CR64Regs[Reg.Num]; 1158 StartLoc = Reg.StartLoc; 1159 EndLoc = Reg.EndLoc; 1160 return false; 1161 } 1162 1163 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc, 1164 SMLoc &EndLoc) { 1165 return ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/false); 1166 } 1167 1168 OperandMatchResultTy SystemZAsmParser::tryParseRegister(unsigned &RegNo, 1169 SMLoc &StartLoc, 1170 SMLoc &EndLoc) { 1171 bool Result = 1172 ParseRegister(RegNo, StartLoc, EndLoc, /*RestoreOnFailure=*/true); 1173 bool PendingErrors = getParser().hasPendingError(); 1174 getParser().clearPendingErrors(); 1175 if (PendingErrors) 1176 return MatchOperand_ParseFail; 1177 if (Result) 1178 return MatchOperand_NoMatch; 1179 return MatchOperand_Success; 1180 } 1181 1182 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info, 1183 StringRef Name, SMLoc NameLoc, 1184 OperandVector &Operands) { 1185 Operands.push_back(SystemZOperand::createToken(Name, NameLoc)); 1186 1187 // Read the remaining operands. 1188 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1189 // Read the first operand. 1190 if (parseOperand(Operands, Name)) { 1191 return true; 1192 } 1193 1194 // Read any subsequent operands. 1195 while (getLexer().is(AsmToken::Comma)) { 1196 Parser.Lex(); 1197 if (parseOperand(Operands, Name)) { 1198 return true; 1199 } 1200 } 1201 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1202 SMLoc Loc = getLexer().getLoc(); 1203 return Error(Loc, "unexpected token in argument list"); 1204 } 1205 } 1206 1207 // Consume the EndOfStatement. 1208 Parser.Lex(); 1209 return false; 1210 } 1211 1212 bool SystemZAsmParser::parseOperand(OperandVector &Operands, 1213 StringRef Mnemonic) { 1214 // Check if the current operand has a custom associated parser, if so, try to 1215 // custom parse the operand, or fallback to the general approach. Force all 1216 // features to be available during the operand check, or else we will fail to 1217 // find the custom parser, and then we will later get an InvalidOperand error 1218 // instead of a MissingFeature errror. 1219 FeatureBitset AvailableFeatures = getAvailableFeatures(); 1220 FeatureBitset All; 1221 All.set(); 1222 setAvailableFeatures(All); 1223 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic); 1224 setAvailableFeatures(AvailableFeatures); 1225 if (ResTy == MatchOperand_Success) 1226 return false; 1227 1228 // If there wasn't a custom match, try the generic matcher below. Otherwise, 1229 // there was a match, but an error occurred, in which case, just return that 1230 // the operand parsing failed. 1231 if (ResTy == MatchOperand_ParseFail) 1232 return true; 1233 1234 // Check for a register. All real register operands should have used 1235 // a context-dependent parse routine, which gives the required register 1236 // class. The code is here to mop up other cases, like those where 1237 // the instruction isn't recognized. 1238 if (Parser.getTok().is(AsmToken::Percent)) { 1239 Register Reg; 1240 if (parseRegister(Reg)) 1241 return true; 1242 Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc)); 1243 return false; 1244 } 1245 1246 // The only other type of operand is an immediate or address. As above, 1247 // real address operands should have used a context-dependent parse routine, 1248 // so we treat any plain expression as an immediate. 1249 SMLoc StartLoc = Parser.getTok().getLoc(); 1250 Register Reg1, Reg2; 1251 bool HaveReg1, HaveReg2; 1252 const MCExpr *Expr; 1253 const MCExpr *Length; 1254 if (parseAddress(HaveReg1, Reg1, HaveReg2, Reg2, Expr, Length)) 1255 return true; 1256 // If the register combination is not valid for any instruction, reject it. 1257 // Otherwise, fall back to reporting an unrecognized instruction. 1258 if (HaveReg1 && Reg1.Group != RegGR && Reg1.Group != RegV 1259 && parseAddressRegister(Reg1)) 1260 return true; 1261 if (HaveReg2 && parseAddressRegister(Reg2)) 1262 return true; 1263 1264 SMLoc EndLoc = 1265 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1266 if (HaveReg1 || HaveReg2 || Length) 1267 Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc)); 1268 else 1269 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc)); 1270 return false; 1271 } 1272 1273 static std::string SystemZMnemonicSpellCheck(StringRef S, 1274 const FeatureBitset &FBS, 1275 unsigned VariantID = 0); 1276 1277 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 1278 OperandVector &Operands, 1279 MCStreamer &Out, 1280 uint64_t &ErrorInfo, 1281 bool MatchingInlineAsm) { 1282 MCInst Inst; 1283 unsigned MatchResult; 1284 1285 FeatureBitset MissingFeatures; 1286 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, 1287 MissingFeatures, MatchingInlineAsm); 1288 switch (MatchResult) { 1289 case Match_Success: 1290 Inst.setLoc(IDLoc); 1291 Out.EmitInstruction(Inst, getSTI()); 1292 return false; 1293 1294 case Match_MissingFeature: { 1295 assert(MissingFeatures.any() && "Unknown missing feature!"); 1296 // Special case the error message for the very common case where only 1297 // a single subtarget feature is missing 1298 std::string Msg = "instruction requires:"; 1299 for (unsigned I = 0, E = MissingFeatures.size(); I != E; ++I) { 1300 if (MissingFeatures[I]) { 1301 Msg += " "; 1302 Msg += getSubtargetFeatureName(I); 1303 } 1304 } 1305 return Error(IDLoc, Msg); 1306 } 1307 1308 case Match_InvalidOperand: { 1309 SMLoc ErrorLoc = IDLoc; 1310 if (ErrorInfo != ~0ULL) { 1311 if (ErrorInfo >= Operands.size()) 1312 return Error(IDLoc, "too few operands for instruction"); 1313 1314 ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc(); 1315 if (ErrorLoc == SMLoc()) 1316 ErrorLoc = IDLoc; 1317 } 1318 return Error(ErrorLoc, "invalid operand for instruction"); 1319 } 1320 1321 case Match_MnemonicFail: { 1322 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); 1323 std::string Suggestion = SystemZMnemonicSpellCheck( 1324 ((SystemZOperand &)*Operands[0]).getToken(), FBS); 1325 return Error(IDLoc, "invalid instruction" + Suggestion, 1326 ((SystemZOperand &)*Operands[0]).getLocRange()); 1327 } 1328 } 1329 1330 llvm_unreachable("Unexpected match type"); 1331 } 1332 1333 OperandMatchResultTy 1334 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal, 1335 int64_t MaxVal, bool AllowTLS) { 1336 MCContext &Ctx = getContext(); 1337 MCStreamer &Out = getStreamer(); 1338 const MCExpr *Expr; 1339 SMLoc StartLoc = Parser.getTok().getLoc(); 1340 if (getParser().parseExpression(Expr)) 1341 return MatchOperand_NoMatch; 1342 1343 auto isOutOfRangeConstant = [&](const MCExpr *E) -> bool { 1344 if (auto *CE = dyn_cast<MCConstantExpr>(E)) { 1345 int64_t Value = CE->getValue(); 1346 if ((Value & 1) || Value < MinVal || Value > MaxVal) 1347 return true; 1348 } 1349 return false; 1350 }; 1351 1352 // For consistency with the GNU assembler, treat immediates as offsets 1353 // from ".". 1354 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) { 1355 if (isOutOfRangeConstant(CE)) { 1356 Error(StartLoc, "offset out of range"); 1357 return MatchOperand_ParseFail; 1358 } 1359 int64_t Value = CE->getValue(); 1360 MCSymbol *Sym = Ctx.createTempSymbol(); 1361 Out.EmitLabel(Sym); 1362 const MCExpr *Base = MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, 1363 Ctx); 1364 Expr = Value == 0 ? Base : MCBinaryExpr::createAdd(Base, Expr, Ctx); 1365 } 1366 1367 // For consistency with the GNU assembler, conservatively assume that a 1368 // constant offset must by itself be within the given size range. 1369 if (const auto *BE = dyn_cast<MCBinaryExpr>(Expr)) 1370 if (isOutOfRangeConstant(BE->getLHS()) || 1371 isOutOfRangeConstant(BE->getRHS())) { 1372 Error(StartLoc, "offset out of range"); 1373 return MatchOperand_ParseFail; 1374 } 1375 1376 // Optionally match :tls_gdcall: or :tls_ldcall: followed by a TLS symbol. 1377 const MCExpr *Sym = nullptr; 1378 if (AllowTLS && getLexer().is(AsmToken::Colon)) { 1379 Parser.Lex(); 1380 1381 if (Parser.getTok().isNot(AsmToken::Identifier)) { 1382 Error(Parser.getTok().getLoc(), "unexpected token"); 1383 return MatchOperand_ParseFail; 1384 } 1385 1386 MCSymbolRefExpr::VariantKind Kind = MCSymbolRefExpr::VK_None; 1387 StringRef Name = Parser.getTok().getString(); 1388 if (Name == "tls_gdcall") 1389 Kind = MCSymbolRefExpr::VK_TLSGD; 1390 else if (Name == "tls_ldcall") 1391 Kind = MCSymbolRefExpr::VK_TLSLDM; 1392 else { 1393 Error(Parser.getTok().getLoc(), "unknown TLS tag"); 1394 return MatchOperand_ParseFail; 1395 } 1396 Parser.Lex(); 1397 1398 if (Parser.getTok().isNot(AsmToken::Colon)) { 1399 Error(Parser.getTok().getLoc(), "unexpected token"); 1400 return MatchOperand_ParseFail; 1401 } 1402 Parser.Lex(); 1403 1404 if (Parser.getTok().isNot(AsmToken::Identifier)) { 1405 Error(Parser.getTok().getLoc(), "unexpected token"); 1406 return MatchOperand_ParseFail; 1407 } 1408 1409 StringRef Identifier = Parser.getTok().getString(); 1410 Sym = MCSymbolRefExpr::create(Ctx.getOrCreateSymbol(Identifier), 1411 Kind, Ctx); 1412 Parser.Lex(); 1413 } 1414 1415 SMLoc EndLoc = 1416 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1417 1418 if (AllowTLS) 1419 Operands.push_back(SystemZOperand::createImmTLS(Expr, Sym, 1420 StartLoc, EndLoc)); 1421 else 1422 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc)); 1423 1424 return MatchOperand_Success; 1425 } 1426 1427 // Force static initialization. 1428 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeSystemZAsmParser() { 1429 RegisterMCAsmParser<SystemZAsmParser> X(getTheSystemZTarget()); 1430 } 1431